diff -ruw linux-4.14.127/arch/arm64/boot/dts/marvell/Makefile linux-4.14.127-fbx/arch/arm64/boot/dts/marvell/Makefile --- linux-4.14.127/arch/arm64/boot/dts/marvell/Makefile 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/arch/arm64/boot/dts/marvell/Makefile 2019-02-15 14:29:36.054632721 +0100 @@ -10,6 +10,15 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-db.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-8080-db.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_exp1_dsl_lte.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_exp2_ftth_p2p.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_exp2_ftth_pon.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_exp1_test_module.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_exp2_test_module.dtb + +# export symbols in DTBs file to allow overlay usage +DTC_FLAGS += -@ always := $(dtb-y) subdir-y := $(dts-dirs) diff -ruw linux-4.14.127/arch/arm64/boot/dts/marvell/armada-3720-db.dts linux-4.14.127-fbx/arch/arm64/boot/dts/marvell/armada-3720-db.dts --- linux-4.14.127/arch/arm64/boot/dts/marvell/armada-3720-db.dts 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/arch/arm64/boot/dts/marvell/armada-3720-db.dts 2019-02-15 14:29:36.054632721 +0100 @@ -94,6 +94,16 @@ 3300000 0x0>; enable-active-high; }; + + vcc_sd_reg2: regulator-vmcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_sd2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpio = <&gpio_exp 4 GPIO_ACTIVE_HIGH>; + }; }; /* Gigabit module on CON19(V2.0)/CON21(V1.4) */ @@ -179,6 +189,7 @@ bus-width = <4>; marvell,pad-type = "sd"; vqmmc-supply = <&vcc_sd_reg1>; + vmmc-supply = <&vcc_sd_reg2>; status = "okay"; }; @@ -216,7 +227,7 @@ /* * Exported on the micro USB connector CON30(V2.0)/CON32(V1.4) through - * an FTDI + * an FTDI (also on CON24(V2.0)/CON26(V1.4)). */ &uart0 { pinctrl-names = "default"; @@ -224,6 +235,13 @@ status = "okay"; }; +/* CON26(V2.0)/CON28(V1.4) */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + /* CON27(V2.0)/CON29(V1.4) */ &usb2 { status = "okay"; diff -ruw linux-4.14.127/arch/arm64/boot/dts/marvell/armada-37xx.dtsi linux-4.14.127-fbx/arch/arm64/boot/dts/marvell/armada-37xx.dtsi --- linux-4.14.127/arch/arm64/boot/dts/marvell/armada-37xx.dtsi 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/arch/arm64/boot/dts/marvell/armada-37xx.dtsi 2019-02-15 14:29:36.054632721 +0100 @@ -55,6 +55,7 @@ aliases { serial0 = &uart0; + serial1 = &uart1; }; cpus { @@ -134,8 +135,24 @@ uart0: serial@12000 { compatible = "marvell,armada-3700-uart"; - reg = <0x12000 0x400>; - interrupts = ; + reg = <0x12000 0x200>; + clocks = <&xtalclk>; + interrupts = + , + , + ; + interrupt-names = "uart-sum", "uart-tx", "uart-rx"; + status = "disabled"; + }; + + uart1: serial@12200 { + compatible = "marvell,armada-3700-uart-ext"; + reg = <0x12200 0x30>; + clocks = <&xtalclk>; + interrupts = + , + ; + interrupt-names = "uart-tx", "uart-rx"; status = "disabled"; }; @@ -183,7 +200,6 @@ , , ; - }; xtalclk: xtal-clk { diff -ruw linux-4.14.127/arch/arm64/boot/dts/marvell/armada-7040-db.dts linux-4.14.127-fbx/arch/arm64/boot/dts/marvell/armada-7040-db.dts --- linux-4.14.127/arch/arm64/boot/dts/marvell/armada-7040-db.dts 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/arch/arm64/boot/dts/marvell/armada-7040-db.dts 2019-02-15 14:29:36.054632721 +0100 @@ -130,6 +130,8 @@ &uart0 { status = "okay"; + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; }; @@ -150,6 +152,36 @@ }; }; +&cpm_nand { + /* + * SPI on CPM and NAND have common pins on this board. We can + * use only one at a time. To enable the NAND (whihch will + * disable the SPI), the "status = "okay";" line have to be + * added here. + */ + num-cs = <1>; + pinctrl-0 = <&nand_pins>, <&nand_rb>; + pinctrl-names = "default"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + + partition@0 { + label = "U-Boot"; + reg = <0 0x200000>; + }; + partition@200000 { + label = "Linux"; + reg = <0x200000 0xe00000>; + }; + partition@1000000 { + label = "Filesystem"; + reg = <0x1000000 0x3f000000>; + }; +}; + + &cpm_spi1 { status = "okay"; @@ -221,10 +253,21 @@ status = "okay"; }; +&cpm_eth0 { + status = "okay"; + /* Network PHY */ + phy-mode = "10gbase-kr"; + /* Generic PHY, providing serdes lanes */ + phys = <&cpm_comphy2 0>; +}; + &cpm_eth1 { status = "okay"; + /* Network PHY */ phy = <&phy0>; phy-mode = "sgmii"; + /* Generic PHY, providing serdes lanes */ + phys = <&cpm_comphy0 1>; }; &cpm_eth2 { diff -ruw linux-4.14.127/arch/arm64/boot/dts/marvell/armada-70x0.dtsi linux-4.14.127-fbx/arch/arm64/boot/dts/marvell/armada-70x0.dtsi --- linux-4.14.127/arch/arm64/boot/dts/marvell/armada-70x0.dtsi 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/arch/arm64/boot/dts/marvell/armada-70x0.dtsi 2019-02-15 14:29:36.054632721 +0100 @@ -64,5 +64,19 @@ &cpm_syscon0 { cpm_pinctrl: pinctrl { compatible = "marvell,armada-7k-pinctrl"; + + nand_pins: nand-pins { + marvell,pins = + "mpp15", "mpp16", "mpp17", "mpp18", + "mpp19", "mpp20", "mpp21", "mpp22", + "mpp23", "mpp24", "mpp25", "mpp26", + "mpp27"; + marvell,function = "dev"; + }; + + nand_rb: nand-rb { + marvell,pins = "mpp13"; + marvell,function = "nf"; + }; }; }; diff -ruw linux-4.14.127/arch/arm64/boot/dts/marvell/armada-8040-db.dts linux-4.14.127-fbx/arch/arm64/boot/dts/marvell/armada-8040-db.dts --- linux-4.14.127/arch/arm64/boot/dts/marvell/armada-8040-db.dts 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/arch/arm64/boot/dts/marvell/armada-8040-db.dts 2019-02-15 14:29:36.054632721 +0100 @@ -146,6 +146,8 @@ /* Accessible over the mini-USB CON9 connector on the main board */ &uart0 { status = "okay"; + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; }; @@ -207,6 +209,11 @@ status = "okay"; }; +&cpm_eth0 { + status = "okay"; + phy-mode = "10gbase-kr"; +}; + &cpm_eth2 { status = "okay"; phy = <&phy1>; @@ -251,6 +258,11 @@ status = "okay"; }; +&cps_eth0 { + status = "okay"; + phy-mode = "10gbase-kr"; +}; + &cps_eth1 { status = "okay"; phy = <&phy0>; diff -ruw linux-4.14.127/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts linux-4.14.127-fbx/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts --- linux-4.14.127/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts 2019-02-15 14:29:36.054632721 +0100 @@ -107,6 +107,8 @@ &uart0 { status = "okay"; + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; }; &ap_sdhci0 { diff -ruw linux-4.14.127/arch/arm64/boot/dts/marvell/armada-ap806.dtsi linux-4.14.127-fbx/arch/arm64/boot/dts/marvell/armada-ap806.dtsi --- linux-4.14.127/arch/arm64/boot/dts/marvell/armada-ap806.dtsi 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/arch/arm64/boot/dts/marvell/armada-ap806.dtsi 2019-07-22 10:44:47.682826276 +0200 @@ -258,6 +258,12 @@ }; + watchdog: watchdog@600000 { + compatible = "arm,sbsa-gwdt"; + reg = <0x610000 0x1000>, <0x600000 0x1000>; + interrupts = ; + }; + ap_sdhci0: sdhci@6e0000 { compatible = "marvell,armada-ap806-sdhci"; reg = <0x6e0000 0x300>; @@ -280,6 +286,11 @@ ap_pinctrl: pinctrl { compatible = "marvell,ap806-pinctrl"; + + uart0_pins: uart0-pins { + marvell,pins = "mpp11", "mpp19"; + marvell,function = "uart0"; + }; }; ap_gpio: gpio@1040 { @@ -291,6 +302,11 @@ gpio-ranges = <&ap_pinctrl 0 0 20>; }; }; + + ap_hwmon: ap806-hwmon@6f8084 { + compatible = "marvell,ap806-hwmon"; + reg = <0x6f8084 0xc>; + }; }; }; }; diff -ruw linux-4.14.127/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi linux-4.14.127-fbx/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi --- linux-4.14.127/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi 2019-02-15 14:29:36.054632721 +0100 @@ -76,9 +76,10 @@ , , , - ; + , + ; interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", - "tx-cpu3", "rx-shared"; + "tx-cpu3", "rx-shared", "link"; port-id = <0>; gop-port-id = <0>; status = "disabled"; @@ -89,9 +90,10 @@ , , , - ; + , + ; interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", - "tx-cpu3", "rx-shared"; + "tx-cpu3", "rx-shared", "link"; port-id = <1>; gop-port-id = <2>; status = "disabled"; @@ -102,9 +104,10 @@ , , , - ; + , + ; interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", - "tx-cpu3", "rx-shared"; + "tx-cpu3", "rx-shared", "link"; port-id = <2>; gop-port-id = <3>; status = "disabled"; @@ -117,6 +120,11 @@ marvell,system-controller = <&cpm_syscon0>; #address-cells = <1>; #size-cells = <0>; + marvell,cp_mgmt = <&cpm_mgmt>; + marvell,sar = <&cpm_mgmt>; + + clocks = <&cpm_clk 1 9>, <&cpm_clk 1 5>; + clock-names = "gop_clk", "mg_clk"; cpm_comphy0: phy@0 { reg = <0>; @@ -175,6 +183,11 @@ msi-parent = <&gicp>; }; + cpm_mgmt: system-controller@400000 { + compatible = "syscon", "simple-mfd"; + reg = <0x400000 0x300>; + }; + cpm_rtc: rtc@284000 { compatible = "marvell,armada-8k-rtc"; reg = <0x284000 0x20>, <0x284080 0x24>; @@ -184,7 +197,7 @@ cpm_syscon0: system-controller@440000 { compatible = "syscon", "simple-mfd"; - reg = <0x440000 0x1000>; + reg = <0x440000 0x2000>; cpm_clk: clock { compatible = "marvell,cp110-clock"; @@ -243,12 +256,55 @@ }; cpm_sata0: sata@540000 { + #size-cells = <0>; + #address-cells = <1>; compatible = "marvell,armada-8k-ahci", "generic-ahci"; reg = <0x540000 0x30000>; interrupts = ; clocks = <&cpm_clk 1 15>; status = "disabled"; + comreset_u = <0x17>; + comwake = <0x6>; + dma-coherent; + }; + + cpm_uart0: uart@702000 { + compatible = "snps,dw-apb-uart"; + reg = <0x702000 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + status = "disabled"; + clock-frequency = <(250 * 1000 * 1000)>; + }; + + cpm_uart1: uart@702100 { + compatible = "snps,dw-apb-uart"; + reg = <0x702100 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + status = "disabled"; + clock-frequency = <(250 * 1000 * 1000)>; + }; + + cpm_uart2: uart@702200 { + compatible = "snps,dw-apb-uart"; + reg = <0x702200 0x200>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + status = "disabled"; + clock-frequency = <(250 * 1000 * 1000)>; + }; + + cpm_utmi: utmi@580000 { + compatible = "marvell,cp110-utmi-phy"; + #phy-cells = <1>; + reg = <0x580000 0x2000>; + reg-names = "utmi-unit"; + marvell,system-controller = <&cpm_syscon0>; }; cpm_xor0: xor@6a0000 { @@ -289,6 +345,11 @@ status = "disabled"; }; + cpm_hwmon: cp110-hwmon@0x400070 { + compatible = "marvell,cp110-hwmon"; + reg = <0x400070 0xc>; + }; + cpm_i2c0: i2c@701000 { compatible = "marvell,mv78230-i2c"; reg = <0x701000 0x20>; @@ -309,24 +370,36 @@ status = "disabled"; }; + cpm_mss_i2c: i2c@211000 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x211000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&cpm_clk 1 21>; + status = "disabled"; + }; + cpm_nand: nand@720000 { /* * Due to the limiation of the pin available * this controller is only usable on the CPM * for A7K and on the CPS for A8K. */ - compatible = "marvell,armada370-nand"; + compatible = "marvell,armada-8k-nand", + "marvell,armada370-nand"; reg = <0x720000 0x54>; #address-cells = <1>; #size-cells = <1>; interrupts = ; clocks = <&cpm_clk 1 2>; + marvell,system-controller = <&cpm_syscon0>; status = "disabled"; }; cpm_trng: trng@760000 { - compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76"; - reg = <0x760000 0x7d>; + compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip150"; + reg = <0x760000 0x10000>; interrupts = ; clocks = <&cpm_clk 1 25>; status = "okay"; diff -ruw linux-4.14.127/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi linux-4.14.127-fbx/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi --- linux-4.14.127/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi 2019-02-15 14:29:36.054632721 +0100 @@ -76,9 +76,10 @@ , , , - ; + , + ; interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", - "tx-cpu3", "rx-shared"; + "tx-cpu3", "rx-shared", "link"; port-id = <0>; gop-port-id = <0>; status = "disabled"; @@ -89,9 +90,10 @@ , , , - ; + , + ; interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", - "tx-cpu3", "rx-shared"; + "tx-cpu3", "rx-shared", "link"; port-id = <1>; gop-port-id = <2>; status = "disabled"; @@ -102,9 +104,10 @@ , , , - ; + , + ; interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", - "tx-cpu3", "rx-shared"; + "tx-cpu3", "rx-shared", "link"; port-id = <2>; gop-port-id = <3>; status = "disabled"; @@ -118,6 +121,13 @@ #address-cells = <1>; #size-cells = <0>; + marvell,cp_mgmt = <&cps_mgmt>; + /* always use Master CP S@R */ + marvell,sar = <&cpm_mgmt>; + + clocks = <&cps_clk 1 9>, <&cps_clk 1 5>; + clock-names = "gop_clk", "mg_clk"; + cps_comphy0: phy@0 { reg = <0>; #phy-cells = <1>; @@ -175,6 +185,11 @@ msi-parent = <&gicp>; }; + cps_mgmt: system-controller@400000 { + compatible = "syscon", "simple-mfd"; + reg = <0x400000 0x300>; + }; + cps_rtc: rtc@284000 { compatible = "marvell,armada-8k-rtc"; reg = <0x284000 0x20>, <0x284080 0x24>; @@ -184,11 +199,12 @@ cps_syscon0: system-controller@440000 { compatible = "syscon", "simple-mfd"; - reg = <0x440000 0x1000>; + reg = <0x440000 0x2000>; cps_clk: clock { compatible = "marvell,cp110-clock"; #clock-cells = <2>; + fbx,ignore-eip150; }; cps_gpio1: gpio@100 { @@ -244,12 +260,55 @@ }; cps_sata0: sata@540000 { + #size-cells = <0>; + #address-cells = <1>; compatible = "marvell,armada-8k-ahci", "generic-ahci"; reg = <0x540000 0x30000>; interrupts = ; clocks = <&cps_clk 1 15>; status = "disabled"; + comreset_u = <0x17>; + comwake = <0x6>; + dma-coherent; + }; + + cps_uart0: uart@702000 { + compatible = "snps,dw-apb-uart"; + reg = <0x702000 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + status = "disabled"; + clock-frequency = <(250 * 1000 * 1000)>; + }; + + cps_uart1: uart@702100 { + compatible = "snps,dw-apb-uart"; + reg = <0x702100 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + status = "disabled"; + clock-frequency = <(250 * 1000 * 1000)>; + }; + + cps_uart2: uart@702200 { + compatible = "snps,dw-apb-uart"; + reg = <0x702200 0x200>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + status = "disabled"; + clock-frequency = <(250 * 1000 * 1000)>; + }; + + cps_utmi: utmi@580000 { + compatible = "marvell,cp110-utmi-phy"; + #phy-cells = <1>; + reg = <0x580000 0x2000>; + reg-names = "utmi-unit"; + marvell,system-controller = <&cps_syscon0>; }; cps_xor0: xor@6a0000 { @@ -290,6 +349,11 @@ status = "disabled"; }; + cps_hwmon: cp110-hwmon@0x400070 { + compatible = "marvell,cp110-hwmon"; + reg = <0x400070 0xc>; + }; + cps_i2c0: i2c@701000 { compatible = "marvell,mv78230-i2c"; reg = <0x701000 0x20>; @@ -310,13 +374,24 @@ status = "disabled"; }; + cps_mss_i2c: i2c@211000 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x211000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&cps_clk 1 21>; + status = "disabled"; + }; + cps_nand: nand@720000 { /* * Due to the limiation of the pin available * this controller is only usable on the CPM * for A7K and on the CPS for A8K. */ - compatible = "marvell,armada370-nand"; + compatible = "marvell,armada370-nand", + "marvell,armada370-nand"; reg = <0x720000 0x54>; #address-cells = <1>; #size-cells = <1>; @@ -326,8 +401,8 @@ }; cps_trng: trng@760000 { - compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76"; - reg = <0x760000 0x7d>; + compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip150"; + reg = <0x760000 0x10000>; interrupts = ; clocks = <&cps_clk 1 25>; status = "okay"; @@ -355,6 +430,19 @@ */ status = "disabled"; }; + + cps_tdm0: tdmmc@7a0000 { + compatible = "marvell,armada-a8k-tdm"; + reg = <0x7a0000 0x20000>, + <0x440400 0x20>; + reg-names = "tdm_regs", "pll_regs"; + interrupts = , + , + ; + clocks = <&cps_clk 1 1>; + clock-names = "gateclk"; + status = "disabled"; + }; }; cps_pcie0: pcie@f4600000 { diff -ruw linux-4.14.127/arch/arm64/include/asm/memory.h linux-4.14.127-fbx/arch/arm64/include/asm/memory.h --- linux-4.14.127/arch/arm64/include/asm/memory.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/arch/arm64/include/asm/memory.h 2019-03-29 17:33:21.517534857 +0100 @@ -86,7 +86,7 @@ */ #ifdef CONFIG_KASAN #define KASAN_SHADOW_SIZE (UL(1) << (VA_BITS - 3)) -#define KASAN_THREAD_SHIFT 1 +#define KASAN_THREAD_SHIFT 2 #else #define KASAN_SHADOW_SIZE (0) #define KASAN_THREAD_SHIFT 0 diff -ruw linux-4.14.127/block/blk-core.c linux-4.14.127-fbx/block/blk-core.c --- linux-4.14.127/block/blk-core.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/block/blk-core.c 2019-07-22 10:44:47.754826572 +0200 @@ -2450,7 +2450,7 @@ } } -void blk_account_io_done(struct request *req) +void blk_account_io_done(struct request *req, int error) { /* * Account IO completion. flush_rq isn't accounted as a @@ -2466,6 +2466,8 @@ cpu = part_stat_lock(); part = req->part; + if (error < 0) + part_stat_inc(cpu, part, io_errors[rw]); part_stat_inc(cpu, part, ios[rw]); part_stat_add(cpu, part, ticks[rw], duration); part_round_stats(req->q, cpu, part); @@ -2873,7 +2875,7 @@ if (req->rq_flags & RQF_DONTPREP) blk_unprep_request(req); - blk_account_io_done(req); + blk_account_io_done(req, error); if (req->end_io) { wbt_done(req->q->rq_wb, &req->issue_stat); diff -ruw linux-4.14.127/block/blk-flush.c linux-4.14.127-fbx/block/blk-flush.c --- linux-4.14.127/block/blk-flush.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/block/blk-flush.c 2019-05-10 11:02:36.872381263 +0200 @@ -173,10 +173,21 @@ BUG_ON(rq->flush.seq & seq); rq->flush.seq |= seq; - if (likely(!error)) + if (likely(!error)) { seq = blk_flush_cur_seq(rq); - else + } else { seq = REQ_FSEQ_DONE; + printk_once(KERN_ERR "%s: flush failed: data integrity problem\n", + rq->rq_disk ? rq->rq_disk->disk_name : "?"); + /* + * returning an error to the FS is wrong: the data is all + * there, it just might not be written out in the expected + * order and thus have a window where the integrity is suspect + * in a crash. Given the small likelihood of actually + * crashing, we should just log a warning here. + */ + error = 0; + } switch (seq) { case REQ_FSEQ_PREFLUSH: diff -ruw linux-4.14.127/block/blk-mq.c linux-4.14.127-fbx/block/blk-mq.c --- linux-4.14.127/block/blk-mq.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/block/blk-mq.c 2019-07-22 10:44:47.754826572 +0200 @@ -512,7 +512,7 @@ inline void __blk_mq_end_request(struct request *rq, blk_status_t error) { - blk_account_io_done(rq); + blk_account_io_done(rq, error); if (rq->end_io) { wbt_done(rq->q->rq_wb, &rq->issue_stat); diff -ruw linux-4.14.127/block/blk.h linux-4.14.127-fbx/block/blk.h --- linux-4.14.127/block/blk.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/block/blk.h 2019-02-15 14:29:37.234637398 +0100 @@ -117,7 +117,7 @@ void blk_account_io_start(struct request *req, bool new_io); void blk_account_io_completion(struct request *req, unsigned int bytes); -void blk_account_io_done(struct request *req); +void blk_account_io_done(struct request *req, int error); /* * Internal atomic flags for request handling diff -ruw linux-4.14.127/block/partition-generic.c linux-4.14.127-fbx/block/partition-generic.c --- linux-4.14.127/block/partition-generic.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/block/partition-generic.c 2019-02-15 14:29:37.238637413 +0100 @@ -130,7 +130,7 @@ return sprintf(buf, "%8lu %8lu %8llu %8u " "%8lu %8lu %8llu %8u " - "%8u %8u %8u" + "%8u %8u %8u %8lu %lu" "\n", part_stat_read(p, ios[READ]), part_stat_read(p, merges[READ]), @@ -142,7 +142,9 @@ jiffies_to_msecs(part_stat_read(p, ticks[WRITE])), inflight[0], jiffies_to_msecs(part_stat_read(p, io_ticks)), - jiffies_to_msecs(part_stat_read(p, time_in_queue))); + jiffies_to_msecs(part_stat_read(p, time_in_queue)), + part_stat_read(p, io_errors[READ]), + part_stat_read(p, io_errors[WRITE])); } ssize_t part_inflight_show(struct device *dev, struct device_attribute *attr, @@ -337,7 +339,7 @@ queue_limit_discard_alignment(&disk->queue->limits, start); p->nr_sects = len; p->partno = partno; - p->policy = get_disk_ro(disk); + p->policy = get_disk_ro(disk) || (flags & ADDPART_FLAG_RO); if (info) { struct partition_meta_info *pinfo = alloc_part_info(disk); diff -ruw linux-4.14.127/block/partitions/Kconfig linux-4.14.127-fbx/block/partitions/Kconfig --- linux-4.14.127/block/partitions/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/block/partitions/Kconfig 2019-02-15 14:29:37.242637429 +0100 @@ -268,3 +268,11 @@ help Say Y here if you want to read the partition table from bootargs. The format for the command line is just like mtdparts. + +config OF_PARTITION + bool "Device tree partition support" if PARTITION_ADVANCED + depends on OF + +config OF_PARTITION_IGNORE_RO + bool "ignore read-only flag" + depends on OF_PARTITION diff -ruw linux-4.14.127/block/partitions/Makefile linux-4.14.127-fbx/block/partitions/Makefile --- linux-4.14.127/block/partitions/Makefile 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/block/partitions/Makefile 2019-02-15 14:29:37.242637429 +0100 @@ -21,3 +21,4 @@ obj-$(CONFIG_EFI_PARTITION) += efi.o obj-$(CONFIG_KARMA_PARTITION) += karma.o obj-$(CONFIG_SYSV68_PARTITION) += sysv68.o +obj-$(CONFIG_OF_PARTITION) += dt.o diff -ruw linux-4.14.127/block/partitions/check.c linux-4.14.127-fbx/block/partitions/check.c --- linux-4.14.127/block/partitions/check.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/block/partitions/check.c 2019-02-15 14:29:37.242637429 +0100 @@ -24,6 +24,7 @@ #include "acorn.h" #include "amiga.h" #include "atari.h" +#include "dt.h" #include "ldm.h" #include "mac.h" #include "msdos.h" @@ -40,6 +41,10 @@ int warn_no_part = 1; /*This is ugly: should make genhd removable media aware*/ static int (*check_part[])(struct parsed_partitions *) = { +#ifdef CONFIG_OF_PARTITION + dt_partition, +#endif + /* * Probe partition formats with tables at disk address 0 * that also have an ADFS boot block at 0xdc0. diff -ruw linux-4.14.127/drivers/Kconfig linux-4.14.127-fbx/drivers/Kconfig --- linux-4.14.127/drivers/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/Kconfig 2019-02-15 14:29:37.278637572 +0100 @@ -9,6 +9,8 @@ source "drivers/connector/Kconfig" +source "drivers/fbxprocfs/Kconfig" + source "drivers/mtd/Kconfig" source "drivers/of/Kconfig" @@ -69,6 +71,10 @@ source "drivers/gpio/Kconfig" +source "drivers/fbxgpio/Kconfig" + +source "drivers/fbxjtag/Kconfig" + source "drivers/w1/Kconfig" source "drivers/power/Kconfig" @@ -77,6 +83,8 @@ source "drivers/thermal/Kconfig" +source "drivers/fbxwatchdog/Kconfig" + source "drivers/watchdog/Kconfig" source "drivers/ssb/Kconfig" diff -ruw linux-4.14.127/drivers/Makefile linux-4.14.127-fbx/drivers/Makefile --- linux-4.14.127/drivers/Makefile 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/Makefile 2019-02-15 14:29:37.278637572 +0100 @@ -16,6 +16,8 @@ obj-$(CONFIG_GPIOLIB) += gpio/ obj-y += pwm/ +obj-$(CONFIG_FREEBOX_GPIO) += fbxgpio/ +obj-$(CONFIG_FREEBOX_JTAG) += fbxjtag/ obj-$(CONFIG_PCI) += pci/ obj-$(CONFIG_PCI_ENDPOINT) += pci/endpoint/ # PCI dwc controller drivers @@ -120,6 +122,7 @@ obj-y += power/ obj-$(CONFIG_HWMON) += hwmon/ obj-$(CONFIG_THERMAL) += thermal/ +obj-$(CONFIG_FREEBOX_WATCHDOG) += fbxwatchdog/ obj-$(CONFIG_WATCHDOG) += watchdog/ obj-$(CONFIG_MD) += md/ obj-$(CONFIG_BT) += bluetooth/ @@ -183,3 +186,5 @@ obj-$(CONFIG_FSI) += fsi/ obj-$(CONFIG_TEE) += tee/ obj-$(CONFIG_MULTIPLEXER) += mux/ + +obj-$(CONFIG_FREEBOX_PROCFS) += fbxprocfs/ diff -ruw linux-4.14.127/drivers/ata/ahci.h linux-4.14.127-fbx/drivers/ata/ahci.h --- linux-4.14.127/drivers/ata/ahci.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/ata/ahci.h 2019-02-15 14:29:37.362637904 +0100 @@ -373,6 +373,9 @@ /* only required for per-port MSI(-X) support */ int (*get_irq_vector)(struct ata_host *host, int port); + + u32 comreset_u; + u32 comwake; }; extern int ahci_ignore_sss; diff -ruw linux-4.14.127/drivers/ata/ahci_mvebu.c linux-4.14.127-fbx/drivers/ata/ahci_mvebu.c --- linux-4.14.127/drivers/ata/ahci_mvebu.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/ata/ahci_mvebu.c 2019-02-15 14:29:37.362637904 +0100 @@ -17,6 +17,8 @@ #include #include #include +#include + #include "ahci.h" #define DRV_NAME "ahci-mvebu" @@ -28,6 +30,15 @@ #define AHCI_WINDOW_BASE(win) (0x64 + ((win) << 4)) #define AHCI_WINDOW_SIZE(win) (0x68 + ((win) << 4)) +#define SATA_CONTROL_REG 0x0 +# define SATA_CTRL_PDOWN_P0 (1 << 6) +# define SATA_CTRL_PDOWN_P1 (1 << 14) +# define SATA_CTRL_EN_P1 (1 << 22) +# define SATA_CTRL_SSU_EN (1 << 23) + +static int phytune_mode = 0; +module_param(phytune_mode, int, 0600); + static void ahci_mvebu_mbus_config(struct ahci_host_priv *hpriv, const struct mbus_dram_target_info *dram) { @@ -62,6 +73,20 @@ writel(0x80, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_DATA); } +static void vendor_indirect_writel(struct ahci_host_priv *hpriv, + u32 data, u32 reg) +{ + writel(reg, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_ADDR); + writel(data, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_DATA); +} + +static u32 vendor_indirect_readl(struct ahci_host_priv *hpriv, + u32 reg) +{ + writel(reg, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_ADDR); + return readl(hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_DATA); +} + /** * ahci_mvebu_stop_engine * @@ -152,6 +177,93 @@ AHCI_SHT(DRV_NAME), }; +static int ahci_mvebu_pll_power_up(struct platform_device *pdev, + struct ahci_host_priv *hpriv) +{ + u32 sata_ctrl; + int i; + + sata_ctrl = vendor_indirect_readl(hpriv, SATA_CONTROL_REG); + sata_ctrl |= SATA_CTRL_PDOWN_P0; + sata_ctrl |= SATA_CTRL_PDOWN_P1; + sata_ctrl &= ~SATA_CTRL_SSU_EN; + sata_ctrl &= ~SATA_CTRL_EN_P1; + vendor_indirect_writel(hpriv, sata_ctrl, SATA_CONTROL_REG); + + for (i = 0; i < hpriv->nports; ++i) { + int error; + + error = phy_power_off(hpriv->phys[i]); + if (error) { + dev_err(&pdev->dev, "unable to power down phy%d\n", i); + return error; + } + + error = phy_power_on(hpriv->phys[i]); + if (error) { + dev_err(&pdev->dev, "unable to power up phy%d\n", i); + return error; + } + } + + sata_ctrl = vendor_indirect_readl(hpriv, SATA_CONTROL_REG); + sata_ctrl &= ~SATA_CTRL_PDOWN_P0; + sata_ctrl &= ~SATA_CTRL_PDOWN_P1; + sata_ctrl |= SATA_CTRL_SSU_EN; + sata_ctrl |= SATA_CTRL_EN_P1; + vendor_indirect_writel(hpriv, sata_ctrl, SATA_CONTROL_REG); + + msleep(500); + + /* Check if comphy PLL is locked */ + for (i = 0; i < hpriv->nports; i++) { + int err = phy_is_pll_locked(hpriv->phys[i]); + if (err) { + dev_err(&pdev->dev, "port %d: comphy PLL is not locked for SATA. Unable to power on SATA comphy\n", + i); + return err; + } + } + + return 0; +} + +#define PORT_INDIRECT_PHY_ADDR(__p) ((__p) * 0x80 + 0x178) +#define PORT_INDIRECT_PHY_DATA(__p) ((__p) * 0x80 + 0x17c) + +#define INDIRECT_PHY_CONTROL 0x0a +#define INDIRECT_PHY_CTRL_NEG_RX_CLK (1 << 13) +#define INDIRECT_PHY_CTRL_NEG_TX_CLK (1 << 12) + +static inline void indirect_phy_write(void __iomem *mmio, int port, + u32 value, u32 phy_off) +{ + writel(phy_off, mmio + PORT_INDIRECT_PHY_ADDR(port)); + writel(value, mmio + PORT_INDIRECT_PHY_DATA(port)); +} + +static inline u32 indirect_phy_read(void __iomem *mmio, int port, u32 phy_off) +{ + writel(phy_off, mmio + PORT_INDIRECT_PHY_ADDR(port)); + return readl(mmio + PORT_INDIRECT_PHY_DATA(port)); +} + +static void ahci_mvebu_tune_clk_edge(struct platform_device *pdev, + struct ahci_host_priv *hpriv) +{ + int i; + + for (i = 0; i < hpriv->nports; ++i) { + u32 v; + + dev_dbg(&pdev->dev, "inverting RX/TX clk on port %d\n", i); + v = indirect_phy_read(hpriv->mmio, i, INDIRECT_PHY_CONTROL); + v &= ~INDIRECT_PHY_CTRL_NEG_TX_CLK; + v &= ~INDIRECT_PHY_CTRL_NEG_RX_CLK; + indirect_phy_write(hpriv->mmio, i, v, INDIRECT_PHY_CONTROL); + } +} + static int ahci_mvebu_probe(struct platform_device *pdev) { struct ahci_host_priv *hpriv; @@ -162,6 +274,22 @@ if (IS_ERR(hpriv)) return PTR_ERR(hpriv); + if (of_device_is_compatible(pdev->dev.of_node, + "marvell,armada-8k-ahci")) { + /* + * switch the CP110 PHYs mode to SATA mode before + * ahci_platform_enable_resources() tries to power them + * on. + */ + int i; + + for (i = 0; i < hpriv->nports; ++i) { + rc = phy_set_mode(hpriv->phys[i], PHY_MODE_SATA); + if (rc) + goto disable_resources; + } + } + rc = ahci_platform_enable_resources(hpriv); if (rc) return rc; @@ -178,10 +306,31 @@ ahci_mvebu_regret_option(hpriv); } + if (of_device_is_compatible(pdev->dev.of_node, + "marvell,armada-8k-ahci")) { + ahci_mvebu_pll_power_up(pdev, hpriv); + ahci_mvebu_regret_option(hpriv); + ahci_mvebu_tune_clk_edge(pdev, hpriv); + } + + /* + * comreset and comwake parameters, later configured in + * ahci_port_init(). + */ + if (of_property_read_u32(pdev->dev.of_node, "comwake", + &hpriv->comwake)) + hpriv->comwake = 0; + + if (of_property_read_u32(pdev->dev.of_node, "comreset_u", + &hpriv->comreset_u)) + hpriv->comreset_u = 0; + + if (!phytune_mode) { rc = ahci_platform_init_host(pdev, hpriv, &ahci_mvebu_port_info, &ahci_platform_sht); if (rc) goto disable_resources; + } return 0; @@ -193,6 +342,7 @@ static const struct of_device_id ahci_mvebu_of_match[] = { { .compatible = "marvell,armada-380-ahci", }, { .compatible = "marvell,armada-3700-ahci", }, + { .compatible = "marvell,armada-8k-ahci", }, { }, }; MODULE_DEVICE_TABLE(of, ahci_mvebu_of_match); diff -ruw linux-4.14.127/drivers/ata/libahci.c linux-4.14.127-fbx/drivers/ata/libahci.c --- linux-4.14.127/drivers/ata/libahci.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/ata/libahci.c 2019-02-15 14:29:37.366637920 +0100 @@ -1197,6 +1197,47 @@ return sprintf(buf, "%d\n", emp->blink_policy); } +#define PORT_OOB_INDIRECT_ADDR 0x78 +#define PORT_OOB_INDIRECT_DATA 0x7c + +#define COM_PARAM_REG 0x48 +#define COMWAKE_MASK 0xf +#define COMRST_MASK 0x3f +#define COMWAKE_VAL(x) (((x) & 0xf) << 12) +#define COMRST_VAL(x) (((x) & 0x3f) << 0) + +static void write_phy_indirect(void __iomem *pmmio, u32 v, u32 reg) +{ + writel(reg, pmmio + PORT_OOB_INDIRECT_ADDR); + writel(v, pmmio + PORT_OOB_INDIRECT_DATA); +} + +static u32 read_phy_indirect(void __iomem *pmmio, u32 reg) +{ + writel(reg, pmmio + PORT_OOB_INDIRECT_ADDR); + return readl(pmmio + PORT_OOB_INDIRECT_DATA); +} + +static void comwake_comrst_config(void __iomem *pmmio, u32 comwake, u32 comrst) +{ + u32 v; + + v = read_phy_indirect(pmmio, COM_PARAM_REG); + + if (comwake) { + v &= ~COMWAKE_VAL(COMWAKE_MASK); + v |= COMWAKE_VAL(comwake); + } + + if (comrst) { + v &= ~COMRST_VAL(COMRST_MASK); + v |= COMRST_VAL(comrst); + } + + write_phy_indirect(pmmio, v, COM_PARAM_REG); +} + + static void ahci_port_init(struct device *dev, struct ata_port *ap, int port_no, void __iomem *mmio, void __iomem *port_mmio) @@ -1211,6 +1252,8 @@ if (rc) dev_warn(dev, "%s (%d)\n", emsg, rc); + comwake_comrst_config(port_mmio, hpriv->comwake, hpriv->comreset_u); + /* clear SError */ tmp = readl(port_mmio + PORT_SCR_ERR); VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); diff -ruw linux-4.14.127/drivers/ata/libata-core.c linux-4.14.127-fbx/drivers/ata/libata-core.c --- linux-4.14.127/drivers/ata/libata-core.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/ata/libata-core.c 2019-02-15 14:29:37.366637920 +0100 @@ -4486,6 +4486,8 @@ /* https://bugzilla.kernel.org/show_bug.cgi?id=15573 */ { "C300-CTFDDAC128MAG", "0001", ATA_HORKAGE_NONCQ, }, + { "Boot ROM", NULL, ATA_HORKAGE_NODMA }, + /* Some Sandisk SSDs lock up hard with NCQ enabled. Reported on SD7SN6S256G and SD8SN8U256G */ { "SanDisk SD[78]SN*G", NULL, ATA_HORKAGE_NONCQ, }, diff -ruw linux-4.14.127/drivers/ata/libata-scsi.c linux-4.14.127-fbx/drivers/ata/libata-scsi.c --- linux-4.14.127/drivers/ata/libata-scsi.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/ata/libata-scsi.c 2019-02-15 14:29:37.370637936 +0100 @@ -4551,7 +4551,7 @@ shost->max_host_blocked = 1; rc = scsi_add_host_with_dma(ap->scsi_host, - &ap->tdev, ap->host->dev); + host->dev, host->dev); if (rc) goto err_add; } diff -ruw linux-4.14.127/drivers/base/firmware_class.c linux-4.14.127-fbx/drivers/base/firmware_class.c --- linux-4.14.127/drivers/base/firmware_class.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/base/firmware_class.c 2019-02-15 14:29:37.410638095 +0100 @@ -1221,6 +1221,7 @@ "Direct firmware load for %s failed with error %d\n", name, ret); if (opt_flags & FW_OPT_USERHELPER) { + if (!(opt_flags & FW_OPT_NO_WARN)) dev_warn(device, "Falling back to user helper\n"); ret = fw_load_from_user_helper(fw, name, device, opt_flags); @@ -1274,6 +1275,22 @@ } EXPORT_SYMBOL(request_firmware); +int +request_firmware_nowarn(const struct firmware **firmware_p, const char *name, + struct device *device) +{ + int ret; + + /* Need to pin this module until return */ + __module_get(THIS_MODULE); + ret = _request_firmware(firmware_p, name, device, NULL, 0, + FW_OPT_UEVENT | FW_OPT_NO_WARN | + FW_OPT_FALLBACK); + module_put(THIS_MODULE); + return ret; +} +EXPORT_SYMBOL(request_firmware_nowarn); + /** * request_firmware_direct: - load firmware directly without usermode helper * @firmware_p: pointer to firmware image diff -ruw linux-4.14.127/drivers/base/regmap/internal.h linux-4.14.127-fbx/drivers/base/regmap/internal.h --- linux-4.14.127/drivers/base/regmap/internal.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/base/regmap/internal.h 2019-02-15 14:29:37.418638127 +0100 @@ -281,4 +281,6 @@ return reg >> map->reg_stride_order; } +void *regmap_mmio_ctx_get_base(const void *priv); + #endif diff -ruw linux-4.14.127/drivers/base/regmap/regmap-mmio.c linux-4.14.127-fbx/drivers/base/regmap/regmap-mmio.c --- linux-4.14.127/drivers/base/regmap/regmap-mmio.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/base/regmap/regmap-mmio.c 2019-02-15 14:29:37.418638127 +0100 @@ -244,6 +244,9 @@ if (!ctx) return ERR_PTR(-ENOMEM); + printk("regmap_mmio_gen_context: ctx:%p regs:%p\n", + ctx, regs); + ctx->regs = regs; ctx->val_bytes = config->val_bits / 8; ctx->clk = ERR_PTR(-ENODEV); @@ -363,4 +366,10 @@ } EXPORT_SYMBOL_GPL(__devm_regmap_init_mmio_clk); +void *regmap_mmio_ctx_get_base(const void *priv) +{ + struct regmap_mmio_context *ctx = (struct regmap_mmio_context *)priv; + return ctx->regs; +} + MODULE_LICENSE("GPL v2"); diff -ruw linux-4.14.127/drivers/base/regmap/regmap.c linux-4.14.127-fbx/drivers/base/regmap/regmap.c --- linux-4.14.127/drivers/base/regmap/regmap.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/base/regmap/regmap.c 2019-02-15 14:29:37.418638127 +0100 @@ -2919,6 +2919,15 @@ } EXPORT_SYMBOL_GPL(regmap_parse_val); +#ifdef CONFIG_REGMAP_MMIO +void *regmap_get_mmio_base_address(struct regmap *map) +{ + return regmap_mmio_ctx_get_base(map->bus_context); +} + +EXPORT_SYMBOL_GPL(regmap_get_mmio_base_address); +#endif + static int __init regmap_initcall(void) { regmap_debugfs_initcall(); diff -ruw linux-4.14.127/drivers/char/Kconfig linux-4.14.127-fbx/drivers/char/Kconfig --- linux-4.14.127/drivers/char/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/char/Kconfig 2019-05-10 11:02:36.920381458 +0200 @@ -26,6 +26,15 @@ kind of kernel debugging operations. When in doubt, say "N". +config DEVPHYSMEM + bool "/dev/physmem virtual device support" + default n + help + Say Y here if you want to support the /dev/physmem device. The + /dev/physmem device allows unprivileged access to physical memory + unused by the kernel. + When in doubt, say "N". + config SGI_SNSC bool "SGI Altix system controller communication support" depends on (IA64_SGI_SN2 || IA64_GENERIC) diff -ruw linux-4.14.127/drivers/char/hw_random/Kconfig linux-4.14.127-fbx/drivers/char/hw_random/Kconfig --- linux-4.14.127/drivers/char/hw_random/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/char/hw_random/Kconfig 2019-02-15 14:29:37.478638365 +0100 @@ -75,7 +75,7 @@ config HW_RANDOM_BCM63XX tristate "Broadcom BCM63xx Random Number Generator support" - depends on BCM63XX || BMIPS_GENERIC + depends on BCM63XX || BMIPS_GENERIC || ARCH_BCM_63XX default HW_RANDOM ---help--- This driver provides kernel-side support for the Random Number diff -ruw linux-4.14.127/drivers/char/hw_random/omap-rng.c linux-4.14.127-fbx/drivers/char/hw_random/omap-rng.c --- linux-4.14.127/drivers/char/hw_random/omap-rng.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/char/hw_random/omap-rng.c 2019-07-22 10:44:47.782826686 +0200 @@ -66,6 +66,22 @@ #define OMAP4_RNG_OUTPUT_SIZE 0x8 #define EIP76_RNG_OUTPUT_SIZE 0x10 +/* + * EIP-150 interrupt management registers: + * + * EIP-150 has an EIP-76 (TRNG) and EIP-28 (PKA) in the same block, + * and a couple of registers aggretating interrupt sources from both + * TRNG and PKA. + * + * This doesn't make any attempt at implementing any support for the + * PKA block. This would require another driver and proper interrupt + * sharing between the two. + * + */ +#define EIP150_IRQ_MASK 0x8008 +#define EIP150_IRQ_ACK 0x8010 +#define EIP150_TRNG_MASK (1 << 3) + enum { RNG_OUTPUT_0_REG = 0, RNG_OUTPUT_1_REG, @@ -142,6 +158,7 @@ u32 (*data_present)(struct omap_rng_dev *priv); int (*init)(struct omap_rng_dev *priv); void (*cleanup)(struct omap_rng_dev *priv); + bool hw_is_eip150; }; struct omap_rng_dev { @@ -266,8 +283,21 @@ omap_rng_write(priv, RNG_FRODETUNE_REG, 0x0); omap_rng_write(priv, RNG_FROENABLE_REG, RNG_REG_FROENABLE_MASK); - /* Enable TRNG */ - val = RNG_CONTROL_ENABLE_TRNG_MASK; + /* Setup alarm/shutdown threshold */ + val = RNG_ALARM_THRESHOLD << RNG_ALARMCNT_ALARM_TH_SHIFT; + val |= RNG_SHUTDOWN_THRESHOLD << RNG_ALARMCNT_SHUTDOWN_TH_SHIFT; + omap_rng_write(priv, RNG_ALARMCNT_REG, val); + + /* + * Enable TRNG, we potentially need to preserve + * RNG_SHUTDOWN_OFLO_MASK + */ + if (priv->pdata->regs[RNG_INTMASK_REG]) + val = 0; + else + val = omap_rng_read(priv, RNG_CONTROL_REG) & + RNG_SHUTDOWN_OFLO_MASK; + val |= RNG_CONTROL_ENABLE_TRNG_MASK; omap_rng_write(priv, RNG_CONTROL_REG, val); return 0; @@ -331,6 +361,12 @@ omap_rng_write(priv, RNG_INTACK_REG, RNG_REG_INTACK_SHUTDOWN_OFLO_MASK); + /* + * ack irq at the EIP-150 level + */ + if (priv->pdata->hw_is_eip150) + writel(EIP150_TRNG_MASK, priv->base + EIP150_IRQ_ACK); + return IRQ_HANDLED; } @@ -350,6 +386,15 @@ .cleanup = omap4_rng_cleanup, }; +static struct omap_rng_pdata eip150_rng_pdata = { + .regs = (u16 *)reg_map_eip76, + .data_size = EIP76_RNG_OUTPUT_SIZE, + .data_present = omap4_rng_data_present, + .init = eip76_rng_init, + .cleanup = omap4_rng_cleanup, + .hw_is_eip150 = true, +}; + static const struct of_device_id omap_rng_of_match[] = { { .compatible = "ti,omap2-rng", @@ -363,6 +408,10 @@ .compatible = "inside-secure,safexcel-eip76", .data = &eip76_rng_pdata, }, + { + .compatible = "inside-secure,safexcel-eip150", + .data = &eip150_rng_pdata, + }, {}, }; MODULE_DEVICE_TABLE(of, omap_rng_of_match); @@ -382,7 +431,8 @@ priv->pdata = match->data; if (of_device_is_compatible(dev->of_node, "ti,omap4-rng") || - of_device_is_compatible(dev->of_node, "inside-secure,safexcel-eip76")) { + of_device_is_compatible(dev->of_node, "inside-secure,safexcel-eip76") || + of_device_is_compatible(dev->of_node, "inside-secure,safexcel-eip150")) { irq = platform_get_irq(pdev, 0); if (irq < 0) { dev_err(dev, "%s: error getting IRQ resource - %d\n", @@ -410,6 +460,12 @@ else omap_rng_write(priv, RNG_CONTROL_REG, RNG_SHUTDOWN_OFLO_MASK); + + /* + * unmask IRQ at EIP-150 level + */ + if (priv->pdata->hw_is_eip150) + writel(EIP150_TRNG_MASK, priv->base + EIP150_IRQ_MASK); } return 0; } diff -ruw linux-4.14.127/drivers/char/mem.c linux-4.14.127-fbx/drivers/char/mem.c --- linux-4.14.127/drivers/char/mem.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/char/mem.c 2019-02-15 14:29:37.494638428 +0100 @@ -29,6 +29,7 @@ #include #include #include +#include #include @@ -415,6 +416,14 @@ return mmap_mem(file, vma); } +static int mmap_physmem(struct file * file, struct vm_area_struct * vma) +{ + if (vma->vm_pgoff < max_pfn && !capable(CAP_SYS_RAWIO)) + return -EPERM; + + return mmap_mem(file, vma); +} + /* * This function reads the *virtual* memory as seen by the kernel. */ @@ -783,6 +792,11 @@ return capable(CAP_SYS_RAWIO) ? 0 : -EPERM; } +static int open_physmem(struct inode * inode, struct file * filp) +{ + return 0; +} + #define zero_lseek null_lseek #define full_lseek null_lseek #define write_zero write_null @@ -848,6 +862,14 @@ .write = write_full, }; +static const struct file_operations __maybe_unused physmem_fops = { + .mmap = mmap_physmem, + .open = open_physmem, +#ifndef CONFIG_MMU + .get_unmapped_area = get_unmapped_area_mem, +#endif +}; + static const struct memdev { const char *name; umode_t mode; @@ -871,6 +893,9 @@ #ifdef CONFIG_PRINTK [11] = { "kmsg", 0644, &kmsg_fops, 0 }, #endif +#ifdef CONFIG_DEVPHYSMEM + [16] = { "physmem", 0, &physmem_fops, FMODE_UNSIGNED_OFFSET }, +#endif }; static int memory_open(struct inode *inode, struct file *filp) diff -ruw linux-4.14.127/drivers/clk/mvebu/cp110-system-controller.c linux-4.14.127-fbx/drivers/clk/mvebu/cp110-system-controller.c --- linux-4.14.127/drivers/clk/mvebu/cp110-system-controller.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/clk/mvebu/cp110-system-controller.c 2019-02-15 14:29:37.546638634 +0100 @@ -244,6 +244,10 @@ u32 nand_clk_ctrl; int i, ret; char *gate_name[ARRAY_SIZE(gate_base_names)]; + bool ignore_eip150; + + ignore_eip150 = of_property_read_bool(pdev->dev.of_node, + "fbx,ignore-eip150"); regmap = syscon_node_to_regmap(syscon_node); if (IS_ERR(regmap)) @@ -340,6 +344,11 @@ if (gate_name[i] == NULL) continue; + if (ignore_eip150 && i == CP110_GATE_EIP150) { + dev_info(&pdev->dev, "ignoring EIP150 gate clock.\n"); + continue; + } + switch (i) { case CP110_GATE_AUDIO: case CP110_GATE_COMM_UNIT: diff -ruw linux-4.14.127/drivers/gpio/gpio-mvebu.c linux-4.14.127-fbx/drivers/gpio/gpio-mvebu.c --- linux-4.14.127/drivers/gpio/gpio-mvebu.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/gpio/gpio-mvebu.c 2019-02-15 14:29:37.766639506 +0100 @@ -66,6 +66,11 @@ #define GPIO_LEVEL_MASK_OFF 0x001c #define GPIO_BLINK_CNT_SELECT_OFF 0x0020 +#define GPIO_CONTROL_SET_OFF 0x0028 +#define GPIO_CONTROL_CLR_OFF 0x002c +#define GPIO_DATAOUT_SET_OFF 0x0030 +#define GPIO_DATAOUT_CLR_OFF 0x0034 + /* * PWM register offsets. */ @@ -110,11 +115,13 @@ struct mvebu_gpio_chip { struct gpio_chip chip; struct regmap *regs; + void __iomem *base; u32 offset; struct regmap *percpu_regs; int irqbase; struct irq_domain *domain; int soc_variant; + int broken_mpp33_dir_wa; /* Used for PWM support */ struct clk *clk; @@ -300,6 +307,18 @@ { struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); + if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) { + unsigned int off; + + if (value) + off = GPIO_DATAOUT_SET_OFF; + else + off = GPIO_DATAOUT_CLR_OFF; + + writel(BIT(pin), mvchip->base + off + mvchip->offset); + return; + } + regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, BIT(pin), value ? BIT(pin) : 0); } @@ -335,10 +354,31 @@ BIT(pin), value ? BIT(pin) : 0); } +static int mvebu_gpio_get_direction(struct gpio_chip *chip, unsigned int pin) +{ + struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); + int offset; + u32 u; + + offset = 0; + if (pin == 1 && mvchip->broken_mpp33_dir_wa) { + /* + * See comment in mvebu_gpio_direction_output(). + */ + offset = -0x40; + } + + regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset + offset, &u); + if ((u & BIT(pin)) == 0) + return GPIOF_DIR_OUT; + else + return GPIOF_DIR_IN; +} + static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin) { struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); - int ret; + int offset, ret; /* * Check with the pinctrl driver whether this pin is usable as @@ -348,7 +388,16 @@ if (ret) return ret; - regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, + offset = 0; + if (pin == 1 && mvchip->broken_mpp33_dir_wa) { + /* + * See comment in mvebu_gpio_direction_output(). + */ + offset = -0x40; + } + + regmap_update_bits(mvchip->regs, + GPIO_IO_CONF_OFF + mvchip->offset + offset, BIT(pin), BIT(pin)); return 0; @@ -358,7 +407,7 @@ int value) { struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); - int ret; + int offset, ret; /* * Check with the pinctrl driver whether this pin is usable as @@ -371,7 +420,17 @@ mvebu_gpio_blink(chip, pin, 0); mvebu_gpio_set(chip, pin, value); - regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, + offset = 0; + if (pin == 1 && mvchip->broken_mpp33_dir_wa) { + /* + * gpio33 direction bit is not controlled from the + * gpio block 0, but from gpio block 1 instead + */ + offset = -0x40; + } + + regmap_update_bits(mvchip->regs, + GPIO_IO_CONF_OFF + mvchip->offset + offset, BIT(pin), 0); return 0; @@ -1045,6 +1104,8 @@ if (IS_ERR(mvchip->regs)) return PTR_ERR(mvchip->regs); + mvchip->base = base; + /* * For the legacy SoCs, the regmap directly maps to the GPIO * registers, so no offset is needed. @@ -1078,6 +1139,8 @@ if (IS_ERR(mvchip->regs)) return PTR_ERR(mvchip->regs); + mvchip->base = regmap_get_mmio_base_address(mvchip->regs); + if (of_property_read_u32(pdev->dev.of_node, "offset", &mvchip->offset)) return -EINVAL; @@ -1095,6 +1158,7 @@ bool have_irqs; int soc_variant; int i, cpu, id; + uint32_t broken_mpp33_dir = 0; int err; match = of_match_device(mvebu_gpio_of_match, &pdev->dev); @@ -1118,6 +1182,12 @@ return -ENODEV; } + of_property_read_u32(pdev->dev.of_node, "marvell,broken-mpp33-dir", + &broken_mpp33_dir); + if (broken_mpp33_dir) + dev_notice(&pdev->dev, "using direction set work around for " + "MPP 33.\n"); + id = of_alias_get_id(pdev->dev.of_node, "gpio"); if (id < 0) { dev_err(&pdev->dev, "Couldn't get OF id\n"); @@ -1129,11 +1199,13 @@ if (!IS_ERR(mvchip->clk)) clk_prepare_enable(mvchip->clk); + mvchip->broken_mpp33_dir_wa = broken_mpp33_dir; mvchip->soc_variant = soc_variant; mvchip->chip.label = dev_name(&pdev->dev); mvchip->chip.parent = &pdev->dev; mvchip->chip.request = gpiochip_generic_request; mvchip->chip.free = gpiochip_generic_free; + mvchip->chip.get_direction = mvebu_gpio_get_direction; mvchip->chip.direction_input = mvebu_gpio_direction_input; mvchip->chip.get = mvebu_gpio_get; mvchip->chip.direction_output = mvebu_gpio_direction_output; diff -ruw linux-4.14.127/drivers/hid/Kconfig linux-4.14.127-fbx/drivers/hid/Kconfig --- linux-4.14.127/drivers/hid/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/hid/Kconfig 2019-02-15 14:29:38.646642994 +0100 @@ -374,6 +374,11 @@ ---help--- Support for Waltop tablets. +config HID_FBX_REMOTE_AUDIO + tristate "Freebox BLE remote audio driver" + depends on HID + select SND_PCM + config HID_GYRATION tristate "Gyration remote control" depends on HID diff -ruw linux-4.14.127/drivers/hid/Makefile linux-4.14.127-fbx/drivers/hid/Makefile --- linux-4.14.127/drivers/hid/Makefile 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/hid/Makefile 2019-02-15 14:29:38.646642994 +0100 @@ -45,6 +45,7 @@ obj-$(CONFIG_HID_GEMBIRD) += hid-gembird.o obj-$(CONFIG_HID_GFRM) += hid-gfrm.o obj-$(CONFIG_HID_GT683R) += hid-gt683r.o +obj-$(CONFIG_HID_FBX_REMOTE_AUDIO) += hid-fbx-remote-audio.o obj-$(CONFIG_HID_GYRATION) += hid-gyration.o obj-$(CONFIG_HID_HOLTEK) += hid-holtek-kbd.o obj-$(CONFIG_HID_HOLTEK) += hid-holtek-mouse.o diff -ruw linux-4.14.127/drivers/hid/hid-core.c linux-4.14.127-fbx/drivers/hid/hid-core.c --- linux-4.14.127/drivers/hid/hid-core.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/hid/hid-core.c 2019-07-22 10:44:47.838826916 +0200 @@ -2404,6 +2404,7 @@ #if IS_ENABLED(CONFIG_HID_ZYDACRON) { HID_USB_DEVICE(USB_VENDOR_ID_ZYDACRON, USB_DEVICE_ID_ZYDACRON_REMOTE_CONTROL) }, #endif + { HID_BLUETOOTH_DEVICE(0x10eb, 0x0023) }, { } }; diff -ruw linux-4.14.127/drivers/hwmon/Kconfig linux-4.14.127-fbx/drivers/hwmon/Kconfig --- linux-4.14.127/drivers/hwmon/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/hwmon/Kconfig 2019-02-15 14:29:38.678643121 +0100 @@ -1869,6 +1869,13 @@ If you say yes here you get support for the temperature and power sensors for APM X-Gene SoC. +config SENSORS_KIRKWOOD_CORETEMP + tristate "Kirkwood core temperature censor" + depends on MACH_KIRKWOOD + +config SENSORS_AP806 + tristate "Marvell AP806/CP110 hardware monitoring driver" + if ACPI comment "ACPI drivers" diff -ruw linux-4.14.127/drivers/hwmon/Makefile linux-4.14.127-fbx/drivers/hwmon/Makefile --- linux-4.14.127/drivers/hwmon/Makefile 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/hwmon/Makefile 2019-02-15 14:29:38.678643121 +0100 @@ -171,6 +171,9 @@ obj-$(CONFIG_SENSORS_WM831X) += wm831x-hwmon.o obj-$(CONFIG_SENSORS_WM8350) += wm8350-hwmon.o obj-$(CONFIG_SENSORS_XGENE) += xgene-hwmon.o +obj-$(CONFIG_SENSORS_KIRKWOOD_CORETEMP)+= kirkwood-coretemp.o + +obj-$(CONFIG_SENSORS_AP806) += ap806-hwmon.o obj-$(CONFIG_PMBUS) += pmbus/ diff -ruw linux-4.14.127/drivers/hwmon/adt7475.c linux-4.14.127-fbx/drivers/hwmon/adt7475.c --- linux-4.14.127/drivers/hwmon/adt7475.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/hwmon/adt7475.c 2019-02-15 14:29:38.686643152 +0100 @@ -131,7 +131,19 @@ /* Macro to read the registers */ -#define adt7475_read(reg) i2c_smbus_read_byte_data(client, (reg)) +static inline s32 __adt7475_read(const struct i2c_client *client, u8 cmd) +{ + s32 ret; + + ret = i2c_smbus_read_byte_data(client, cmd); + if (ret < 0) { + printk("__adt7475_read error: %d\n", ret); + return 0; + } + return ret; +} + +#define adt7475_read(reg) __adt7475_read(client, (reg)) /* Macros to easily index the registers */ diff -ruw linux-4.14.127/drivers/i2c/busses/Kconfig linux-4.14.127-fbx/drivers/i2c/busses/Kconfig --- linux-4.14.127/drivers/i2c/busses/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/i2c/busses/Kconfig 2019-02-15 14:29:38.726643311 +0100 @@ -1294,6 +1294,10 @@ to SLIMpro (On chip coprocessor) mailbox mechanism. If unsure, say N. +config I2C_WP3 + tristate "Wintegra WP3 I2C controll" + depends on WINTEGRA_WINPATH3 + config SCx200_ACB tristate "Geode ACCESS.bus support" depends on X86_32 && PCI diff -ruw linux-4.14.127/drivers/i2c/busses/Makefile linux-4.14.127-fbx/drivers/i2c/busses/Makefile --- linux-4.14.127/drivers/i2c/busses/Makefile 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/i2c/busses/Makefile 2019-02-15 14:29:38.726643311 +0100 @@ -113,6 +113,7 @@ obj-$(CONFIG_I2C_XLP9XX) += i2c-xlp9xx.o obj-$(CONFIG_I2C_RCAR) += i2c-rcar.o obj-$(CONFIG_I2C_ZX2967) += i2c-zx2967.o +obj-$(CONFIG_I2C_WP3) += i2c-wp3.o # External I2C/SMBus adapter drivers obj-$(CONFIG_I2C_DIOLAN_U2C) += i2c-diolan-u2c.o diff -ruw linux-4.14.127/drivers/i2c/busses/i2c-mv64xxx.c linux-4.14.127-fbx/drivers/i2c/busses/i2c-mv64xxx.c --- linux-4.14.127/drivers/i2c/busses/i2c-mv64xxx.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/i2c/busses/i2c-mv64xxx.c 2019-02-15 14:29:38.738643358 +0100 @@ -22,6 +22,8 @@ #include #include #include +#include +#include #include #include #include @@ -146,6 +148,10 @@ bool irq_clear_inverted; /* Clk div is 2 to the power n, not 2 to the power n + 1 */ bool clk_n_base_0; + struct i2c_bus_recovery_info rinfo; + struct pinctrl *pinctrl; + struct pinctrl_state *pinctrl_pins_default; + struct pinctrl_state *pinctrl_pins_gpio; }; static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_mv64xxx = { @@ -311,6 +317,11 @@ case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */ case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */ /* Doesn't seem to be a device at other end */ + dev_dbg(&drv_data->adapter.dev, + "mv64xxx_i2c_fsm: got no ack -- state: 0x%x, " + "status: 0x%x, addr: 0x%x, flags: 0x%x\n", + drv_data->state, status, drv_data->msg->addr, + drv_data->msg->flags); drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; drv_data->state = MV64XXX_I2C_STATE_IDLE; drv_data->rc = -ENXIO; @@ -561,6 +572,8 @@ "mv64xxx: I2C bus locked, block: %d, " "time_left: %d\n", drv_data->block, (int)time_left); + if (drv_data->adapter.bus_recovery_info) + i2c_recover_bus(&drv_data->adapter); mv64xxx_i2c_hw_init(drv_data); } } else @@ -572,6 +585,34 @@ int is_last) { unsigned long flags; + int limit; + + /* + * wait for (re)start/stop condition to clear from last + * transfer if any + */ + limit = 1000; + do { + u32 val; + + val = readl(drv_data->reg_base + drv_data->reg_offsets.control); + if (!(val & (MV64XXX_I2C_REG_CONTROL_STOP | + MV64XXX_I2C_REG_CONTROL_STOP))) + break; + + udelay(1); + } while (limit-- > 0); + + if (limit < 0) { + dev_err(&drv_data->adapter.dev, + "mv64xxx: start/stop bit won't clear\n"); + } + + /* according to datasheet, controller is buggy when you do + * register polling and it says to always wait for an IRQ + * (clock domain related), since we busywait for START/STOP + * clear, add a small delay */ + udelay(5); spin_lock_irqsave(&drv_data->lock, flags); @@ -579,6 +620,7 @@ drv_data->send_stop = is_last; drv_data->block = 1; + mv64xxx_i2c_send_start(drv_data); spin_unlock_irqrestore(&drv_data->lock, flags); @@ -862,6 +904,62 @@ out: return rc; } + +static void mv64xxx_prepare_recovery(struct i2c_adapter *adap) +{ + struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap); + pinctrl_select_state(drv_data->pinctrl, drv_data->pinctrl_pins_gpio); +} + +static void mv64xxx_unprepare_recovery(struct i2c_adapter *adap) +{ + struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap); + pinctrl_select_state(drv_data->pinctrl, drv_data->pinctrl_pins_default); +} + +static int mv64xxx_init_recovery_info(struct mv64xxx_i2c_data *drv_data, + struct platform_device *pdev) +{ + struct i2c_bus_recovery_info *rinfo = &drv_data->rinfo; + + drv_data->pinctrl = devm_pinctrl_get(&pdev->dev); + if (!drv_data->pinctrl || IS_ERR(drv_data->pinctrl)) { + if (PTR_ERR(drv_data->pinctrl) == -EPROBE_DEFER) + return -EPROBE_DEFER; + dev_info(&pdev->dev, "can't get pinctrl, bus recovery not supported\n"); + return 0; + } + + drv_data->pinctrl_pins_default = pinctrl_lookup_state(drv_data->pinctrl, + PINCTRL_STATE_DEFAULT); + drv_data->pinctrl_pins_gpio = pinctrl_lookup_state(drv_data->pinctrl, + "gpio"); + + rinfo->sda_gpio = of_get_named_gpio(pdev->dev.of_node, "sda-gpios", 0); + rinfo->scl_gpio = of_get_named_gpio(pdev->dev.of_node, "scl-gpios", 0); + + if (rinfo->sda_gpio == -EPROBE_DEFER || + rinfo->scl_gpio == -EPROBE_DEFER) { + return -EPROBE_DEFER; + } else if (!gpio_is_valid(rinfo->sda_gpio) || + !gpio_is_valid(rinfo->scl_gpio) || + IS_ERR(drv_data->pinctrl_pins_default) || + IS_ERR(drv_data->pinctrl_pins_gpio)) { + dev_info(&pdev->dev, "recovery information incomplete\n"); + return 0; + } + + dev_dbg(&pdev->dev, "using scl-gpio %d and sda-gpio %d for recovery\n", + rinfo->sda_gpio, rinfo->scl_gpio); + + rinfo->prepare_recovery = mv64xxx_prepare_recovery; + rinfo->unprepare_recovery = mv64xxx_unprepare_recovery; + rinfo->recover_bus = i2c_generic_gpio_recovery; + drv_data->adapter.bus_recovery_info = rinfo; + + return 0; +} + #else /* CONFIG_OF */ static int mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data, @@ -869,8 +967,15 @@ { return -ENODEV; } + +static int mv64xxx_init_recovery_info(struct mv64xxx_i2c_data *drv_data, + struct platform_device *pdev) +{ + return 0; +} #endif /* CONFIG_OF */ + static int mv64xxx_i2c_probe(struct platform_device *pd) { @@ -898,6 +1003,10 @@ init_waitqueue_head(&drv_data->waitq); spin_lock_init(&drv_data->lock); + rc = mv64xxx_init_recovery_info(drv_data, pd); + if (rc) + return rc; + /* Not all platforms have a clk */ drv_data->clk = devm_clk_get(&pd->dev, NULL); if (IS_ERR(drv_data->clk) && PTR_ERR(drv_data->clk) == -EPROBE_DEFER) @@ -926,7 +1035,7 @@ drv_data->adapter.dev.parent = &pd->dev; drv_data->adapter.algo = &mv64xxx_i2c_algo; drv_data->adapter.owner = THIS_MODULE; - drv_data->adapter.class = I2C_CLASS_DEPRECATED; + drv_data->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD; drv_data->adapter.nr = pd->id; drv_data->adapter.dev.of_node = pd->dev.of_node; platform_set_drvdata(pd, drv_data); diff -ruw linux-4.14.127/drivers/i2c/i2c-core-base.c linux-4.14.127-fbx/drivers/i2c/i2c-core-base.c --- linux-4.14.127/drivers/i2c/i2c-core-base.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/i2c/i2c-core-base.c 2019-02-15 14:29:38.750643406 +0100 @@ -205,9 +205,6 @@ */ while (i++ < RECOVERY_CLK_CNT * 2) { if (val) { - /* Break if SDA is high */ - if (bri->get_sda && bri->get_sda(adap)) - break; /* SCL shouldn't be low here */ if (!bri->get_scl(adap)) { dev_err(&adap->dev, diff -ruw linux-4.14.127/drivers/input/misc/Kconfig linux-4.14.127-fbx/drivers/input/misc/Kconfig --- linux-4.14.127/drivers/input/misc/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/input/misc/Kconfig 2019-02-15 14:29:38.958644230 +0100 @@ -855,4 +855,9 @@ To compile this driver as a module, choose M here: the module will be called hisi_powerkey. +config INPUT_SMSC_CAP1066 + tristate "SMSC CAP1066 capacitive sensor driver" + select I2C + select INPUT_POLLDEV + endif diff -ruw linux-4.14.127/drivers/input/misc/Makefile linux-4.14.127-fbx/drivers/input/misc/Makefile --- linux-4.14.127/drivers/input/misc/Makefile 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/input/misc/Makefile 2019-02-15 14:29:38.958644230 +0100 @@ -81,3 +81,4 @@ obj-$(CONFIG_INPUT_XEN_KBDDEV_FRONTEND) += xen-kbdfront.o obj-$(CONFIG_INPUT_YEALINK) += yealink.o obj-$(CONFIG_INPUT_IDEAPAD_SLIDEBAR) += ideapad_slidebar.o +obj-$(CONFIG_INPUT_SMSC_CAP1066) += smsc_cap1066.o diff -ruw linux-4.14.127/drivers/irqchip/irq-mvebu-gicp.c linux-4.14.127-fbx/drivers/irqchip/irq-mvebu-gicp.c --- linux-4.14.127/drivers/irqchip/irq-mvebu-gicp.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/irqchip/irq-mvebu-gicp.c 2019-02-15 14:29:39.026644500 +0100 @@ -193,6 +193,7 @@ if (!gicp) return -ENOMEM; + spin_lock_init(&gicp->spi_lock); gicp->dev = &pdev->dev; spin_lock_init(&gicp->spi_lock); diff -ruw linux-4.14.127/drivers/media/dvb-core/dvb-usb-ids.h linux-4.14.127-fbx/drivers/media/dvb-core/dvb-usb-ids.h --- linux-4.14.127/drivers/media/dvb-core/dvb-usb-ids.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/media/dvb-core/dvb-usb-ids.h 2019-02-15 14:29:39.154645007 +0100 @@ -116,6 +116,7 @@ #define USB_PID_DELOCK_USB2_DVBT 0xb803 #define USB_PID_DIBCOM_HOOK_DEFAULT 0x0064 #define USB_PID_DIBCOM_HOOK_DEFAULT_REENUM 0x0065 +#define USB_PID_DIBCOM_HOOK_DEFAULT_STK7770P 0x0066 #define USB_PID_DIBCOM_MOD3000_COLD 0x0bb8 #define USB_PID_DIBCOM_MOD3000_WARM 0x0bb9 #define USB_PID_DIBCOM_MOD3001_COLD 0x0bc6 diff -ruw linux-4.14.127/drivers/media/dvb-core/dvb_frontend.c linux-4.14.127-fbx/drivers/media/dvb-core/dvb_frontend.c --- linux-4.14.127/drivers/media/dvb-core/dvb_frontend.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/media/dvb-core/dvb_frontend.c 2019-02-15 14:29:39.158645023 +0100 @@ -812,6 +812,7 @@ if (fe->exit != DVB_FE_DEVICE_REMOVED) fe->exit = DVB_FE_NORMAL_EXIT; mb(); + wake_up_all(&fepriv->events.wait_queue); if (!fepriv->thread) return; @@ -2486,6 +2487,9 @@ poll_wait (file, &fepriv->events.wait_queue, wait); + if (fe->exit) + return POLLERR | POLLHUP; + if (fepriv->events.eventw != fepriv->events.eventr) return (POLLIN | POLLRDNORM | POLLPRI); diff -ruw linux-4.14.127/drivers/media/rc/keymaps/Makefile linux-4.14.127-fbx/drivers/media/rc/keymaps/Makefile --- linux-4.14.127/drivers/media/rc/keymaps/Makefile 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/media/rc/keymaps/Makefile 2019-02-15 14:29:39.414646038 +0100 @@ -85,6 +85,7 @@ rc-pv951.o \ rc-hauppauge.o \ rc-rc6-mce.o \ + rc-rc6-freebox.o \ rc-real-audio-220-32-keys.o \ rc-reddo.o \ rc-snapstream-firefly.o \ diff -ruw linux-4.14.127/drivers/media/usb/dvb-usb/dib0700_devices.c linux-4.14.127-fbx/drivers/media/usb/dvb-usb/dib0700_devices.c --- linux-4.14.127/drivers/media/usb/dvb-usb/dib0700_devices.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/media/usb/dvb-usb/dib0700_devices.c 2019-02-15 14:29:39.466646243 +0100 @@ -3817,7 +3817,8 @@ { USB_DEVICE(USB_VID_PCTV, USB_PID_PCTV_2002E_SE) }, { USB_DEVICE(USB_VID_PCTV, USB_PID_DIBCOM_STK8096PVR) }, { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_STK8096PVR) }, - { USB_DEVICE(USB_VID_HAMA, USB_PID_HAMA_DVBT_HYBRID) }, +/* 85 */{ USB_DEVICE(USB_VID_HAMA, USB_PID_HAMA_DVBT_HYBRID) }, + { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_HOOK_DEFAULT_STK7770P) }, { 0 } /* Terminating entry */ }; MODULE_DEVICE_TABLE(usb, dib0700_usb_id_table); @@ -4549,6 +4550,35 @@ .change_protocol = dib0700_change_protocol, }, }, { DIB0700_DEFAULT_DEVICE_PROPERTIES, + + .num_adapters = 1, + .adapter = { + { + .num_frontends = 1, + .fe = {{ + .caps = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF, + .pid_filter_count = 32, + .pid_filter = stk70x0p_pid_filter, + .pid_filter_ctrl = stk70x0p_pid_filter_ctrl, + .frontend_attach = stk7770p_frontend_attach, + .tuner_attach = dib7770p_tuner_attach, + + DIB0700_DEFAULT_STREAMING_CONFIG(0x02), + }}, + .size_of_priv = + sizeof(struct dib0700_adapter_state), + }, + }, + + .num_device_descs = 1, + .devices = { + { "DiBcom STK7770P reference design no IR", + { &dib0700_usb_id_table[86], NULL }, + { NULL }, + }, + }, + + }, { DIB0700_DEFAULT_DEVICE_PROPERTIES, .num_adapters = 1, .adapter = { { diff -ruw linux-4.14.127/drivers/mfd/Kconfig linux-4.14.127-fbx/drivers/mfd/Kconfig --- linux-4.14.127/drivers/mfd/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/mfd/Kconfig 2019-02-15 14:29:39.558646609 +0100 @@ -1781,6 +1781,17 @@ for PWM and IIO Timer. This driver allow to share the registers between the others drivers. +config MFD_FBXGW7R_PANEL + tristate "Freebox fbxgw7r panel support" + depends on FB + depends on SPI_MASTER + depends on OF + select FB_SYS_FOPS + select FB_SYS_FILLRECT + select FB_SYS_COPYAREA + select FB_SYS_IMAGEBLIT + select FB_DEFERRED_IO + menu "Multimedia Capabilities Port drivers" depends on ARCH_SA1100 diff -ruw linux-4.14.127/drivers/mfd/Makefile linux-4.14.127-fbx/drivers/mfd/Makefile --- linux-4.14.127/drivers/mfd/Makefile 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/mfd/Makefile 2019-02-15 14:29:39.558646609 +0100 @@ -227,3 +227,4 @@ obj-$(CONFIG_MFD_STM32_LPTIMER) += stm32-lptimer.o obj-$(CONFIG_MFD_STM32_TIMERS) += stm32-timers.o obj-$(CONFIG_MFD_MXS_LRADC) += mxs-lradc.o +obj-$(CONFIG_MFD_FBXGW7R_PANEL) += fbxgw7r-panel.o diff -ruw linux-4.14.127/drivers/misc/Kconfig linux-4.14.127-fbx/drivers/misc/Kconfig --- linux-4.14.127/drivers/misc/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/misc/Kconfig 2019-02-15 14:29:39.590646735 +0100 @@ -4,6 +4,9 @@ menu "Misc devices" +config WINTEGRA_MMAP + bool "wintegra mmap driver" + config SENSORS_LIS3LV02D tristate depends on INPUT @@ -419,6 +422,18 @@ To compile this driver as a module, choose M here: the module will be called vmw_balloon. +config INTELCE_PIC16PMU + tristate "PIC16 PMU, LED, hwmon support" + select INPUT_POLLDEV + select NEW_LEDS + select I2C + select HWMON + select ARCH_REQUIRE_GPIOLIB + ---help--- + Freebox v6 HD PIC16 PMU interface support, enables + control of the on-board LEDs and reports the power status, + reset status and button status. + config PCH_PHUB tristate "Intel EG20T PCH/LAPIS Semicon IOH(ML7213/ML7223/ML7831) PHUB" select GENERIC_NET_UTILS @@ -440,6 +455,11 @@ To compile this driver as a module, choose M here: the module will be called pch_phub. +config FBXSERIAL_OF + bool "read fbxserial through DT chosen node" + depends on OF + select ARCH_HAS_FBXSERIAL + config USB_SWITCH_FSA9480 tristate "FSA9480 USB Switch" depends on I2C @@ -518,4 +538,6 @@ source "drivers/misc/genwqe/Kconfig" source "drivers/misc/echo/Kconfig" source "drivers/misc/cxl/Kconfig" +source "drivers/misc/remoti/Kconfig" +source "drivers/misc/hdmi-cec/Kconfig" endmenu diff -ruw linux-4.14.127/drivers/misc/Makefile linux-4.14.127-fbx/drivers/misc/Makefile --- linux-4.14.127/drivers/misc/Makefile 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/misc/Makefile 2019-02-15 14:29:39.590646735 +0100 @@ -3,6 +3,7 @@ # Makefile for misc devices that really don't fit anywhere else. # +obj-$(CONFIG_WINTEGRA_MMAP) += wintegra_mmap.o obj-$(CONFIG_IBM_ASM) += ibmasm/ obj-$(CONFIG_AD525X_DPOT) += ad525x_dpot.o obj-$(CONFIG_AD525X_DPOT_I2C) += ad525x_dpot-i2c.o @@ -22,7 +23,9 @@ obj-$(CONFIG_SGI_IOC4) += ioc4.o obj-$(CONFIG_ENCLOSURE_SERVICES) += enclosure.o obj-$(CONFIG_KGDB_TESTS) += kgdbts.o +obj-$(CONFIG_FBXSERIAL_OF) += fbxserial_of.o obj-$(CONFIG_SGI_XP) += sgi-xp/ +obj-$(CONFIG_INTELCE_PIC16PMU) += pic16-pmu.o obj-$(CONFIG_SGI_GRU) += sgi-gru/ obj-$(CONFIG_CS5535_MFGPT) += cs5535-mfgpt.o obj-$(CONFIG_HP_ILO) += hpilo.o @@ -39,6 +42,7 @@ obj-$(CONFIG_SPEAR13XX_PCIE_GADGET) += spear13xx_pcie_gadget.o obj-$(CONFIG_VMWARE_BALLOON) += vmw_balloon.o obj-$(CONFIG_PCH_PHUB) += pch_phub.o +obj-y += hdmi-cec/ obj-y += ti-st/ obj-y += lis3lv02d/ obj-$(CONFIG_USB_SWITCH_FSA9480) += fsa9480.o @@ -56,6 +60,7 @@ obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o obj-$(CONFIG_PCI_ENDPOINT_TEST) += pci_endpoint_test.o +obj-y += remoti/ lkdtm-$(CONFIG_LKDTM) += lkdtm_core.o lkdtm-$(CONFIG_LKDTM) += lkdtm_bugs.o diff -ruw linux-4.14.127/drivers/misc/eeprom/Kconfig linux-4.14.127-fbx/drivers/misc/eeprom/Kconfig --- linux-4.14.127/drivers/misc/eeprom/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/misc/eeprom/Kconfig 2019-05-10 11:02:37.140382353 +0200 @@ -110,4 +110,8 @@ This driver can also be built as a module. If so, the module will be called idt_89hpesx. +config EEPROM_EE1004_RAW + tristate "SPD EEPROMs on DDR4 memory modules (non smbus)" + depends on I2C && SYSFS + endmenu diff -ruw linux-4.14.127/drivers/misc/eeprom/Makefile linux-4.14.127-fbx/drivers/misc/eeprom/Makefile --- linux-4.14.127/drivers/misc/eeprom/Makefile 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/misc/eeprom/Makefile 2019-02-15 14:29:39.594646751 +0100 @@ -7,3 +7,4 @@ obj-$(CONFIG_EEPROM_93XX46) += eeprom_93xx46.o obj-$(CONFIG_EEPROM_DIGSY_MTC_CFG) += digsy_mtc_eeprom.o obj-$(CONFIG_EEPROM_IDT_89HPESX) += idt_89hpesx.o +obj-$(CONFIG_EEPROM_EE1004_RAW) += ee1004_raw.o diff -ruw linux-4.14.127/drivers/misc/eeprom/at24.c linux-4.14.127-fbx/drivers/misc/eeprom/at24.c --- linux-4.14.127/drivers/misc/eeprom/at24.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/misc/eeprom/at24.c 2019-05-10 11:02:37.140382353 +0200 @@ -575,8 +575,10 @@ int err; u32 val; +#ifndef CONFIG_NVMEM_IGNORE_RO if (device_property_present(dev, "read-only")) chip->flags |= AT24_FLAG_READONLY; +#endif err = device_property_read_u32(dev, "address-width", &val); if (!err) { @@ -618,7 +620,6 @@ struct at24_data *at24; int err; unsigned i, num_addresses; - u8 test_byte; if (client->dev.platform_data) { chip = *(struct at24_platform_data *)client->dev.platform_data; @@ -772,18 +773,6 @@ } } - i2c_set_clientdata(client, at24); - - /* - * Perform a one-byte test read to verify that the - * chip is functional. - */ - err = at24_read(at24, 0, &test_byte, 1); - if (err) { - err = -ENODEV; - goto err_clients; - } - at24->nvmem_config.name = dev_name(&client->dev); at24->nvmem_config.dev = &client->dev; at24->nvmem_config.read_only = !writable; @@ -805,6 +794,8 @@ goto err_clients; } + i2c_set_clientdata(client, at24); + dev_info(&client->dev, "%u byte %s EEPROM, %s, %u bytes/write\n", chip.byte_len, client->name, writable ? "writable" : "read-only", at24->write_max); diff -ruw linux-4.14.127/drivers/mmc/core/block.c linux-4.14.127-fbx/drivers/mmc/core/block.c --- linux-4.14.127/drivers/mmc/core/block.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/mmc/core/block.c 2019-02-15 14:29:39.622646862 +0100 @@ -2130,7 +2130,7 @@ md->parent = parent; set_disk_ro(md->disk, md->read_only || default_ro); md->disk->flags = GENHD_FL_EXT_DEVT; - if (area_type & (MMC_BLK_DATA_AREA_RPMB | MMC_BLK_DATA_AREA_BOOT)) + if (area_type & (MMC_BLK_DATA_AREA_RPMB)) md->disk->flags |= GENHD_FL_NO_PART_SCAN; /* diff -ruw linux-4.14.127/drivers/mtd/Kconfig linux-4.14.127-fbx/drivers/mtd/Kconfig --- linux-4.14.127/drivers/mtd/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/mtd/Kconfig 2019-02-15 14:29:39.654646989 +0100 @@ -23,6 +23,9 @@ WARNING: some of the tests will ERASE entire MTD device which they test. Do not use these tests unless you really know what you do. +config MTD_ERASE_PRINTK + bool "write to kernel log when a block is erased" + config MTD_REDBOOT_PARTS tristate "RedBoot partition table parsing" ---help--- @@ -135,6 +138,10 @@ the partition map from the children of the flash node, as described in Documentation/devicetree/bindings/mtd/partition.txt. +config MTD_OF_PARTS_IGNORE_RO + bool "ignore read-only flag" + depends on MTD_OF_PARTS + config MTD_AR7_PARTS tristate "TI AR7 partitioning support" ---help--- diff -ruw linux-4.14.127/drivers/mtd/devices/m25p80.c linux-4.14.127-fbx/drivers/mtd/devices/m25p80.c --- linux-4.14.127/drivers/mtd/devices/m25p80.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/mtd/devices/m25p80.c 2019-02-15 14:29:39.662647020 +0100 @@ -47,12 +47,49 @@ return ret; } +static int m25p80_read_alt_id(struct spi_nor *nor, u8 cmd, u8 *val, int len) +{ + struct m25p *flash = nor->priv; + struct spi_device *spi = flash->spi; + u8 cmdbuf[4] = { cmd, 0, 0, 0 }; + int ret; + + ret = spi_write_then_read(spi, cmdbuf, sizeof (cmdbuf), val, len); + if (ret < 0) + dev_err(&spi->dev, "error %d reading alt id %x\n", ret, cmd); + + return ret; +} + +static int m25p80_read_atmel_id(struct spi_nor *nor, u8 cmd, u8 *val, int len) +{ + struct m25p *flash = nor->priv; + struct spi_device *spi = flash->spi; + int ret; + + printk("m25p80_read_atmel_id: 0x%x\n", cmd); + ret = spi_write_then_read(spi, &cmd, 1, val, len); + if (ret < 0) + dev_err(&spi->dev, "error %d reading ATMEL id %x\n", ret, cmd); + + return ret; +} + static void m25p_addr2cmd(struct spi_nor *nor, unsigned int addr, u8 *cmd) { /* opcode is in cmd[0] */ cmd[1] = addr >> (nor->addr_width * 8 - 8); + + if (nor->addr_width < 2) + return; cmd[2] = addr >> (nor->addr_width * 8 - 16); + + if (nor->addr_width < 3) + return; cmd[3] = addr >> (nor->addr_width * 8 - 24); + + if (nor->addr_width < 4) + return; cmd[4] = addr >> (nor->addr_width * 8 - 32); } @@ -257,6 +294,8 @@ nor->write = m25p80_write; nor->write_reg = m25p80_write_reg; nor->read_reg = m25p80_read_reg; + nor->read_alt_id = m25p80_read_alt_id; + nor->read_atmel_id = m25p80_read_atmel_id; nor->dev = &spi->dev; spi_nor_set_flash_node(nor, spi->dev.of_node); @@ -306,6 +345,10 @@ static int m25p_remove(struct spi_device *spi) { struct m25p *flash = spi_get_drvdata(spi); + struct spi_nor *nor; + + nor = &flash->spi_nor; + spi_nor_reset(nor); /* Clean up MTD stuff. */ return mtd_device_unregister(&flash->spi_nor.mtd); diff -ruw linux-4.14.127/drivers/mtd/mtdchar.c linux-4.14.127-fbx/drivers/mtd/mtdchar.c --- linux-4.14.127/drivers/mtd/mtdchar.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/mtd/mtdchar.c 2019-02-15 14:29:39.670647052 +0100 @@ -190,6 +190,7 @@ { struct mtd_oob_ops ops; + memset(&ops, 0, sizeof (ops)); ops.mode = MTD_OPS_RAW; ops.datbuf = kbuf; ops.oobbuf = NULL; @@ -284,6 +285,7 @@ { struct mtd_oob_ops ops; + memset(&ops, 0, sizeof (ops)); ops.mode = MTD_OPS_RAW; ops.datbuf = kbuf; ops.oobbuf = NULL; @@ -765,6 +767,10 @@ erase->callback = mtdchar_erase_callback; erase->priv = (unsigned long)&waitq; +#ifdef CONFIG_MTD_ERASE_PRINTK + printk(KERN_DEBUG "mtd: %s: ERASE offset=@%08llx\n", + mtd->name, erase->addr); +#endif /* FIXME: Allow INTERRUPTIBLE. Which means not having the wait_queue head on the stack. diff -ruw linux-4.14.127/drivers/mtd/mtdcore.c linux-4.14.127-fbx/drivers/mtd/mtdcore.c --- linux-4.14.127/drivers/mtd/mtdcore.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/mtd/mtdcore.c 2019-02-15 14:29:39.670647052 +0100 @@ -319,6 +319,43 @@ } static DEVICE_ATTR(bbt_blocks, S_IRUGO, mtd_bbtblocks_show, NULL); +static ssize_t mtd_nand_type_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mtd_info *mtd = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "%s\n", mtd->nand_type); +} +static DEVICE_ATTR(nand_type, S_IRUGO, mtd_nand_type_show, NULL); + +static ssize_t mtd_nand_manufacturer_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mtd_info *mtd = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "%s\n", mtd->nand_manufacturer); +} +static DEVICE_ATTR(nand_manufacturer, S_IRUGO, mtd_nand_manufacturer_show, NULL); + +static ssize_t mtd_nand_onfi_ecc_bits_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mtd_info *mtd = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "%d\n", mtd->onfi_ecc_bits); +} +static DEVICE_ATTR(onfi_ecc_bits, S_IRUGO, mtd_nand_onfi_ecc_bits_show, NULL); + +static ssize_t mtd_nand_onfi_model_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mtd_info *mtd = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "%s\n", + mtd->onfi_model ? mtd->onfi_model : "unknown"); +} +static DEVICE_ATTR(onfi_model, S_IRUGO, mtd_nand_onfi_model_show, NULL); + static struct attribute *mtd_attrs[] = { &dev_attr_type.attr, &dev_attr_flags.attr, @@ -336,6 +373,10 @@ &dev_attr_bad_blocks.attr, &dev_attr_bbt_blocks.attr, &dev_attr_bitflip_threshold.attr, + &dev_attr_nand_type.attr, + &dev_attr_nand_manufacturer.attr, + &dev_attr_onfi_ecc_bits.attr, + &dev_attr_onfi_model.attr, NULL, }; ATTRIBUTE_GROUPS(mtd); diff -ruw linux-4.14.127/drivers/mtd/mtdpart.c linux-4.14.127-fbx/drivers/mtd/mtdpart.c --- linux-4.14.127/drivers/mtd/mtdpart.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/mtd/mtdpart.c 2019-02-15 14:29:39.670647052 +0100 @@ -430,6 +430,10 @@ slave->mtd.oobavail = parent->oobavail; slave->mtd.subpage_sft = parent->subpage_sft; slave->mtd.pairing = parent->pairing; + slave->mtd.nand_type = parent->nand_type; + slave->mtd.nand_manufacturer = parent->nand_manufacturer; + slave->mtd.onfi_ecc_bits = parent->onfi_ecc_bits; + slave->mtd.onfi_model = parent->onfi_model; slave->mtd.name = name; slave->mtd.owner = parent->owner; diff -ruw linux-4.14.127/drivers/mtd/nand/Kconfig linux-4.14.127-fbx/drivers/mtd/nand/Kconfig --- linux-4.14.127/drivers/mtd/nand/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/mtd/nand/Kconfig 2019-02-15 14:29:39.670647052 +0100 @@ -40,6 +40,15 @@ tristate default n +config MTD_FORCE_BAD_BLOCK_ERASE + bool "Force erase on bad blocks (useful for bootloader parts)" + depends on MTD_NAND + default n + help + Enable this option only when you need to force an erase on + blocks being marked as "bad" by Linux (i.e: other ECC/bad block + marker layout). + config MTD_NAND_DENALI tristate @@ -563,4 +572,8 @@ Enables support for NAND controller on MTK SoCs. This controller is found on mt27xx, mt81xx, mt65xx SoCs. +config MTD_NAND_DENALI_FBX + tristate "NAND Denali controller support" + depends on MTD_NAND && PCI + endif # MTD_NAND diff -ruw linux-4.14.127/drivers/mtd/nand/Makefile linux-4.14.127-fbx/drivers/mtd/nand/Makefile --- linux-4.14.127/drivers/mtd/nand/Makefile 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/mtd/nand/Makefile 2019-02-15 14:29:39.670647052 +0100 @@ -60,6 +60,7 @@ obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/ obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o obj-$(CONFIG_MTD_NAND_MTK) += mtk_nand.o mtk_ecc.o +obj-$(CONFIG_MTD_NAND_DENALI_FBX) += denali_nand.o nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o nand-objs += nand_amd.o diff -ruw linux-4.14.127/drivers/mtd/ofpart.c linux-4.14.127-fbx/drivers/mtd/ofpart.c --- linux-4.14.127/drivers/mtd/ofpart.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/mtd/ofpart.c 2019-02-15 14:29:39.694647147 +0100 @@ -115,8 +115,10 @@ partname = of_get_property(pp, "name", &len); parts[i].name = partname; +#ifndef CONFIG_MTD_OF_PARTS_IGNORE_RO if (of_get_property(pp, "read-only", &len)) parts[i].mask_flags |= MTD_WRITEABLE; +#endif if (of_get_property(pp, "lock", &len)) parts[i].mask_flags |= MTD_POWERUP_LOCK; diff -ruw linux-4.14.127/drivers/mtd/parsers/Kconfig linux-4.14.127-fbx/drivers/mtd/parsers/Kconfig --- linux-4.14.127/drivers/mtd/parsers/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/mtd/parsers/Kconfig 2019-02-15 14:29:39.694647147 +0100 @@ -6,3 +6,14 @@ may contain up to 3/4 partitions (depending on the version). This driver will parse TRX header and report at least two partitions: kernel and rootfs. + +config MTD_FBX6HD_PARTS + tristate "Freebox V6 HD partitioning support" + help + Freebox V6 HD partitioning support + +config MTD_FBX6HD_PARTS_WRITE_ALL + bool "make all partitions writeable" + depends on MTD_FBX6HD_PARTS + help + Freebox V6 HD partitions support diff -ruw linux-4.14.127/drivers/mtd/parsers/Makefile linux-4.14.127-fbx/drivers/mtd/parsers/Makefile --- linux-4.14.127/drivers/mtd/parsers/Makefile 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/mtd/parsers/Makefile 2019-02-15 14:29:39.694647147 +0100 @@ -1 +1,2 @@ obj-$(CONFIG_MTD_PARSER_TRX) += parser_trx.o +obj-$(CONFIG_MTD_FBX6HD_PARTS) += fbx6hd-mtdparts.o diff -ruw linux-4.14.127/drivers/mtd/spi-nor/spi-nor.c linux-4.14.127-fbx/drivers/mtd/spi-nor/spi-nor.c --- linux-4.14.127/drivers/mtd/spi-nor/spi-nor.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/mtd/spi-nor/spi-nor.c 2019-02-15 14:29:39.698647163 +0100 @@ -43,6 +43,7 @@ struct flash_info { char *name; + uint32_t ext_id; /* * This array stores the ID bytes. @@ -61,7 +62,8 @@ u16 page_size; u16 addr_width; - u16 flags; + u32 flags; + #define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */ #define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */ #define SST_WRITE BIT(2) /* use SST byte programming */ @@ -89,6 +91,9 @@ #define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */ #define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */ #define USE_CLSR BIT(14) /* use CLSR command */ + +#define ALT_PROBE BIT(15) /* only match during alt_probe */ +#define ALT_PROBE_ATMEL BIT(16) /* only match during alt_probe_atmel */ }; #define JEDEC_MFR(info) ((info)->id[0]) @@ -268,6 +273,7 @@ bool need_wren = false; u8 cmd; + nor->four_bytes_enabled = enable; switch (JEDEC_MFR(info)) { case SNOR_MFR_MICRON: /* Some Micron need WREN command; all will accept it */ @@ -872,6 +878,7 @@ /* Used when the "_ext_id" is two bytes at most */ #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ + .ext_id = (_ext_id), \ .id = { \ ((_jedec_id) >> 16) & 0xff, \ ((_jedec_id) >> 8) & 0xff, \ @@ -886,6 +893,7 @@ .flags = (_flags), #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ + .ext_id = (_ext_id), \ .id = { \ ((_jedec_id) >> 16) & 0xff, \ ((_jedec_id) >> 8) & 0xff, \ @@ -1185,6 +1193,22 @@ { "3S400AN", S3AN_INFO(0x1f2400, 256, 264) }, { "3S700AN", S3AN_INFO(0x1f2500, 512, 264) }, { "3S1400AN", S3AN_INFO(0x1f2600, 512, 528) }, + + /* Used on Freebox Gateways ... */ + + /* Atmel */ + { "at25f512b", INFO(0x1f6500, 0x1f65, 32 * 1024, 2, + ALT_PROBE_ATMEL) }, + /* Macronix */ + { "mx25l512", INFO(0xc20500, 0xc205, 64 * 1024, 1, + ALT_PROBE | SECT_4K) }, + /* SST */ + { "sst25vf512a", INFO(0xbf4800, 0xbf48, 32 * 1024, 2, ALT_PROBE) }, + + /* EON */ + { "en25f05", INFO(0x1c0500, 0x1c05, 64 * 1024, 1, + ALT_PROBE | SECT_4K) }, + { }, }; @@ -1212,6 +1236,56 @@ return ERR_PTR(-ENODEV); } +static const struct flash_info *spi_nor_alt_read_id(struct spi_nor *nor) +{ + u8 data[2]; + u16 id; + int err, tmp; + const struct flash_info *info; + + err = nor->read_alt_id(nor, SPINOR_OP_RDID_ALT, data, sizeof (data)); + if (err) { + dev_dbg(nor->dev, "error %d reading ALT ID.\n", err); + return ERR_PTR(err); + } + id = (data[1] << 8) | data[0]; + + for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) { + info = &spi_nor_ids[tmp]; + if ((info->flags & ALT_PROBE) && (info->ext_id == id)) + return info; + } + + dev_err(nor->dev, "unrecognized ALT id %04x\n", id); + return ERR_PTR(-ENODEV); +} + +static const struct flash_info *spi_nor_atmel_id(struct spi_nor *nor) +{ + u8 data[2]; + u16 id; + int err, tmp; + const struct flash_info *info; + + err = nor->read_atmel_id(nor, 0x15, data, sizeof (data)); + if (err) { + dev_dbg(nor->dev, "error %d reading ATMEL ID.\n", err); + return ERR_PTR(err); + } + id = (data[1] << 8) | data[0]; + + for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) { + info = &spi_nor_ids[tmp]; + if ((info->flags & ALT_PROBE_ATMEL) && (info->ext_id == id)) + return info; + } + + dev_err(nor->dev, "unrecognized ATMEL id %04x\n", id); + return ERR_PTR(-ENODEV); +} + + + static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) { @@ -2647,6 +2721,13 @@ return 0; } +static void sst_write_enable(struct spi_nor *nor) +{ + write_enable(nor); + nor->write_reg(nor, SPINOR_OP_EWRSR, NULL, 0); + write_sr(nor, 0); +} + int spi_nor_scan(struct spi_nor *nor, const char *name, const struct spi_nor_hwcaps *hwcaps) { @@ -2682,6 +2763,12 @@ if (name && info->id_len) { const struct flash_info *jinfo; + jinfo = spi_nor_alt_read_id(nor); + if (IS_ERR(jinfo)) + /* try ATMEL */ + jinfo = spi_nor_atmel_id(nor); + if (IS_ERR(jinfo)) + /* try JEDEC */ jinfo = spi_nor_read_id(nor); if (IS_ERR(jinfo)) { return PTR_ERR(jinfo); @@ -2728,6 +2815,9 @@ spi_nor_wait_till_ready(nor); } + if (info->ext_id == 0xbf48) + sst_write_enable(nor); + if (!mtd->name) mtd->name = dev_name(dev); mtd->priv = nor; @@ -2847,10 +2937,23 @@ mtd->eraseregions[i].erasesize, mtd->eraseregions[i].erasesize / 1024, mtd->eraseregions[i].numblocks); + + nor->flash_info = info; return 0; } EXPORT_SYMBOL_GPL(spi_nor_scan); +void spi_nor_reset(struct spi_nor *nor) +{ + const struct flash_info *info = nor->flash_info; + + if (nor->four_bytes_enabled) { + dev_info(nor->dev, "disabling 4 bytes address mode"); + set_4byte(nor, info, 0); + } +} +EXPORT_SYMBOL_GPL(spi_nor_reset); + static const struct flash_info *spi_nor_match_id(const char *name) { const struct flash_info *id = spi_nor_ids; diff -ruw linux-4.14.127/drivers/net/ethernet/Kconfig linux-4.14.127-fbx/drivers/net/ethernet/Kconfig --- linux-4.14.127/drivers/net/ethernet/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/net/ethernet/Kconfig 2019-02-15 14:29:39.762647417 +0100 @@ -179,6 +179,7 @@ source "drivers/net/ethernet/tundra/Kconfig" source "drivers/net/ethernet/via/Kconfig" source "drivers/net/ethernet/wiznet/Kconfig" +source "drivers/net/ethernet/wintegra/Kconfig" source "drivers/net/ethernet/xilinx/Kconfig" source "drivers/net/ethernet/xircom/Kconfig" source "drivers/net/ethernet/synopsys/Kconfig" diff -ruw linux-4.14.127/drivers/net/ethernet/Makefile linux-4.14.127-fbx/drivers/net/ethernet/Makefile --- linux-4.14.127/drivers/net/ethernet/Makefile 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/net/ethernet/Makefile 2019-02-15 14:29:39.762647417 +0100 @@ -91,6 +91,7 @@ obj-$(CONFIG_NET_VENDOR_TUNDRA) += tundra/ obj-$(CONFIG_NET_VENDOR_VIA) += via/ obj-$(CONFIG_NET_VENDOR_WIZNET) += wiznet/ +obj-$(CONFIG_NET_VENDOR_WINTEGRA) += wintegra/ obj-$(CONFIG_NET_VENDOR_XILINX) += xilinx/ obj-$(CONFIG_NET_VENDOR_XIRCOM) += xircom/ obj-$(CONFIG_NET_VENDOR_SYNOPSYS) += synopsys/ diff -ruw linux-4.14.127/drivers/net/ethernet/broadcom/Kconfig linux-4.14.127-fbx/drivers/net/ethernet/broadcom/Kconfig --- linux-4.14.127/drivers/net/ethernet/broadcom/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/net/ethernet/broadcom/Kconfig 2019-02-15 14:29:39.806647592 +0100 @@ -59,6 +59,15 @@ This driver supports the ethernet MACs in the Broadcom 63xx MIPS chipset family (BCM63XX). +config BCM63XX_ENET_RUNNER + tristate "Broadcom 63xx runner ethernet support" + select MII + select FIXED_PHY + select PHYLIB + select BCM7XXX_PHY + select BROADCOM_PHY + select SOC_BCM63XX_RDP_NEED_ENET + config BCMGENET tristate "Broadcom GENET internal MAC support" depends on OF && HAS_IOMEM diff -ruw linux-4.14.127/drivers/net/ethernet/broadcom/Makefile linux-4.14.127-fbx/drivers/net/ethernet/broadcom/Makefile --- linux-4.14.127/drivers/net/ethernet/broadcom/Makefile 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/net/ethernet/broadcom/Makefile 2019-02-15 14:29:39.806647592 +0100 @@ -16,3 +16,4 @@ obj-$(CONFIG_BGMAC_PLATFORM) += bgmac-platform.o obj-$(CONFIG_SYSTEMPORT) += bcmsysport.o obj-$(CONFIG_BNXT) += bnxt/ +obj-$(CONFIG_BCM63XX_ENET_RUNNER) += bcm63xx_enet_runner/ diff -ruw linux-4.14.127/drivers/net/ethernet/marvell/Kconfig linux-4.14.127-fbx/drivers/net/ethernet/marvell/Kconfig --- linux-4.14.127/drivers/net/ethernet/marvell/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/net/ethernet/marvell/Kconfig 2019-02-15 14:29:40.030648479 +0100 @@ -22,6 +22,7 @@ depends on HAS_DMA select PHYLIB select MVMDIO + select MII ---help--- This driver supports the gigabit ethernet MACs in the Marvell Discovery PPC/MIPS chipset family (MV643XX) and @@ -30,6 +31,15 @@ Some boards that use the Discovery chipset are the Momenco Ocelot C and Jaguar ATX and Pegasos II. +config MV643XX_ETH_FBX_FF + bool "fastpath support for freebox boards" + depends on MV643XX_ETH + select IP_FFN + select IPV6_FFN + select IPV6_SIT_6RD + select BRIDGE + select FBXBRIDGE + config MVMDIO tristate "Marvell MDIO interface support" depends on HAS_IOMEM @@ -86,10 +96,21 @@ depends on ARCH_MVEBU || COMPILE_TEST depends on HAS_DMA select MVMDIO + select PHYLINK + select MII ---help--- This driver supports the network interface units in the Marvell ARMADA 375, 7K and 8K SoCs. +config MVPP2_FBX_FF + bool "fastpath support for freebox boards" + depends on MVPP2 + select IP_FFN + select IPV6_FFN + select IPV6_SIT_6RD + select BRIDGE + select FBXBRIDGE + config PXA168_ETH tristate "Marvell pxa168 ethernet support" depends on HAS_IOMEM && HAS_DMA diff -ruw linux-4.14.127/drivers/net/ethernet/marvell/mvpp2.c linux-4.14.127-fbx/drivers/net/ethernet/marvell/mvpp2.c --- linux-4.14.127/drivers/net/ethernet/marvell/mvpp2.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/net/ethernet/marvell/mvpp2.c 2019-07-22 10:44:47.958827409 +0200 @@ -27,7 +27,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -39,11 +41,25 @@ #include #include -/* RX Fifo Registers */ +#ifdef CONFIG_MVPP2_FBX_FF +#include +#include +#include +#include +#include +#include + +#include "../../../net/bridge/br_private.h" +#include "../../../net/fbxbridge/fbxbr_private.h" +#endif + +/* Fifo Registers */ #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port)) #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port)) #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60 #define MVPP2_RX_FIFO_INIT_REG 0x64 +#define MVPP22_TX_FIFO_THRESH_REG(port) (0x8840 + 4 * (port)) +#define MVPP22_TX_FIFO_SIZE_REG(port) (0x8860 + 4 * (port)) /* RX DMA Top Registers */ #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port)) @@ -83,6 +99,16 @@ #define MVPP2_PRS_TCAM_CTRL_REG 0x1230 #define MVPP2_PRS_TCAM_EN_MASK BIT(0) +/* RSS Registers */ +#define MVPP22_RSS_INDEX 0x1500 +#define MVPP22_RSS_INDEX_TABLE_ENTRY(idx) (idx) +#define MVPP22_RSS_INDEX_TABLE(idx) ((idx) << 8) +#define MVPP22_RSS_INDEX_QUEUE(idx) ((idx) << 16) +#define MVPP22_RSS_TABLE_ENTRY 0x1508 +#define MVPP22_RSS_TABLE 0x1510 +#define MVPP22_RSS_TABLE_POINTER(p) (p) +#define MVPP22_RSS_WIDTH 0x150c + /* Classifier Registers */ #define MVPP2_CLS_MODE_REG 0x1800 #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0) @@ -216,7 +242,13 @@ #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000) #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port)) #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff + +#ifdef CONFIG_MVPP2_FBX_FF +#define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0x7f0000 +#else #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000 +#endif + #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET 16 #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24) #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25) @@ -243,6 +275,7 @@ #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4)) #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4)) #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff +#define MVPP22_BM_POOL_PTRS_NUM_MASK 0xfff8 #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16) #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4)) #define MVPP2_BM_START_MASK BIT(0) @@ -280,12 +313,31 @@ #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8 +/* packet counters. PPv2.2 only */ +#define MVPP22_PCTR_OVERRUN_REG(port) (0x7000 + 4 * (port)) +#define MVPP22_PCTR_CLS_DROPPED_REG(port) (0x7028 + 4 * (port)) +#define MVPP22_PCTR_CTR_IDX_REG (0x7040) +#define MVPP22_PCTR_TX_ENQUEUE_REG (0x7100) +#define MVPP22_PCTR_TX_ENQUEUE_DESC_DDR_REG (0x7104) +#define MVPP22_PCTR_TX_ENQUEUE_BUF_DDR_REG (0x7108) +#define MVPP22_PCTR_TX_ENQUEUE_HWFWD_REG (0x710c) +#define MVPP22_PCTR_RX_ENQUEUE_REG (0x7120) +#define MVPP22_PCTR_TX_DEQUEUE_REG (0x7130) +#define MVPP22_PCTR_TX_FULL_DROP_REG (0x7200) +#define MVPP22_PCTR_TX_EARLY_DROP_REG (0x7204) +#define MVPP22_PCTR_TX_BM_DROP_REG (0x7208) +#define MVPP22_PCTR_TX_BM_MC_DROP_REG (0x720c) +#define MVPP22_PCTR_RX_FULL_DROP_REG (0x7220) +#define MVPP22_PCTR_RX_EARLY_DROP_REG (0x7224) +#define MVPP22_PCTR_RX_BM_DROP_REG (0x7228) + /* TX Scheduler registers */ #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000 #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff #define MVPP2_TXP_SCHED_DISQ_OFFSET 8 #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010 +#define MVPP2_TXP_SCHED_FIXED_PRIO_REG 0x8014 #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018 #define MVPP2_TXP_SCHED_MTU_REG 0x801c #define MVPP2_TXP_MTU_MAX 0x7FFFF @@ -303,6 +355,7 @@ #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2)) #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff +#define MVPP2_TXQ_SCHED_BCOUNT_CFG_REG(q) (0x80A0 + ((q) << 2)) /* TX general registers */ #define MVPP2_TX_SNOOP_REG 0x8800 @@ -331,7 +384,7 @@ #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6) #define MVPP2_GMAC_SA_LOW_OFFS 7 #define MVPP2_GMAC_CTRL_2_REG 0x8 -#define MVPP2_GMAC_INBAND_AN_MASK BIT(0) +#define MVPP2_GMAC_INBAND_AN_SGMII_MASK BIT(0) #define MVPP2_GMAC_FLOW_CTRL_MASK GENMASK(2, 1) #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3) #define MVPP2_GMAC_INTERNAL_CLK_MASK BIT(4) @@ -342,6 +395,7 @@ #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1) #define MVPP2_GMAC_IN_BAND_AUTONEG BIT(2) #define MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS BIT(3) +#define MVPP2_GMAC_IN_BAND_RESTART_AN BIT(4) #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5) #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6) #define MVPP2_GMAC_AN_SPEED_EN BIT(7) @@ -351,6 +405,13 @@ #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13) #define MVPP2_GMAC_STATUS0 0x10 #define MVPP2_GMAC_STATUS0_LINK_UP BIT(0) +#define MVPP2_GMAC_STATUS0_GMII_SPEED BIT(1) +#define MVPP2_GMAC_STATUS0_MII_SPEED BIT(2) +#define MVPP2_GMAC_STATUS0_FULL_DUPLEX BIT(3) +#define MVPP2_GMAC_STATUS0_RX_PAUSE BIT(6) +#define MVPP2_GMAC_STATUS0_TX_PAUSE BIT(7) +#define MVPP2_GMAC_STATUS0_AN_COMPLETE BIT(11) +#define MVPP2_GMAC_STATUS0_SYNC_OK BIT(14) #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6 #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0 @@ -419,6 +480,8 @@ #define MAC_CLK_RESET_MAC BIT(2) #define MVPP22_MPCS_CLK_RESET_DIV_RATIO(n) ((n) << 4) #define MVPP22_MPCS_CLK_RESET_DIV_SET BIT(11) +#define MVPP22_MPCS_GEARBOX_STATUS 0xd0 +#define MVPP22_MPCS_GEARBOX_STATUS_LANELOCK BIT(0) /* XPCS registers. PPv2.2 only */ #define MVPP22_XPCS_BASE(port) (0x7400 + (port) * 0x1000) @@ -444,11 +507,11 @@ /* Various constants */ /* Coalescing */ -#define MVPP2_TXDONE_COAL_PKTS_THRESH 15 +#define MVPP2_TXDONE_COAL_PKTS_THRESH 64 #define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL #define MVPP2_TXDONE_COAL_USEC 1000 #define MVPP2_RX_COAL_PKTS 32 -#define MVPP2_RX_COAL_USEC 100 +#define MVPP2_RX_COAL_USEC 64 /* The two bytes Marvell header. Either contains a special value used * by Marvell switches when a specific hardware mode is enabled (not @@ -483,14 +546,23 @@ /* Maximum number of TXQs used by single port */ #define MVPP2_MAX_TXQ 8 +/* MVPP2_MAX_TSO_SEGS is the maximum number of fragments to allow in the GSO + * skb. As we need a maxium of two descriptors per fragments (1 header, 1 data), + * multiply this value by two to count the maximum number of skb descs needed. + */ +#define MVPP2_MAX_TSO_SEGS 100 +#define MVPP2_MAX_SKB_DESCS (MVPP2_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) + /* Dfault number of RXQs in use */ #define MVPP2_DEFAULT_RXQ 4 /* Max number of Rx descriptors */ -#define MVPP2_MAX_RXD 128 +#define MVPP2_MAX_RXD_MAX 1024 +#define MVPP2_MAX_RXD_DFLT 1024 /* Max number of Tx descriptors */ -#define MVPP2_MAX_TXD 1024 +#define MVPP2_MAX_TXD_MAX 2048 +#define MVPP2_MAX_TXD_DFLT 2048 /* Amount of Tx descriptors that can be reserved at once by CPU */ #define MVPP2_CPU_DESC_CHUNK 64 @@ -505,10 +577,23 @@ #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1) /* RX FIFO constants */ -#define MVPP2_RX_FIFO_PORT_DATA_SIZE 0x2000 -#define MVPP2_RX_FIFO_PORT_ATTR_SIZE 0x80 +#define MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB 0x8000 +#define MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB 0x2000 +#define MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB 0x1000 +#define MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB 0x200 +#define MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB 0x80 +#define MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB 0x40 #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80 +/* TX FIFO constants */ +#define MVPP22_TX_FIFO_DATA_SIZE_10KB 0xa +#define MVPP22_TX_FIFO_DATA_SIZE_3KB 0x3 +#define MVPP2_TX_FIFO_THRESHOLD_MIN 256 +#define MVPP2_TX_FIFO_THRESHOLD_10KB \ + (MVPP22_TX_FIFO_DATA_SIZE_10KB * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN) +#define MVPP2_TX_FIFO_THRESHOLD_3KB \ + (MVPP22_TX_FIFO_DATA_SIZE_3KB * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN) + /* RX buffer constants */ #define MVPP2_SKB_SHINFO_SIZE \ SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) @@ -738,25 +823,32 @@ #define MVPP2_CLS_FLOWS_TBL_SIZE 512 #define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3 #define MVPP2_CLS_LKP_TBL_SIZE 64 +#define MVPP2_CLS_RX_QUEUES 256 + +/* RSS constants */ +#define MVPP22_RSS_TABLE_ENTRIES 32 /* BM constants */ -#define MVPP2_BM_POOLS_NUM 8 +#define MVPP2_BM_JUMBO_BUF_NUM 512 #define MVPP2_BM_LONG_BUF_NUM 1024 #define MVPP2_BM_SHORT_BUF_NUM 2048 #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4) #define MVPP2_BM_POOL_PTR_ALIGN 128 -#define MVPP2_BM_SWF_LONG_POOL(port) ((port > 2) ? 2 : port) -#define MVPP2_BM_SWF_SHORT_POOL 3 /* BM cookie (32 bits) definition */ #define MVPP2_BM_COOKIE_POOL_OFFS 8 #define MVPP2_BM_COOKIE_CPU_OFFS 24 +#define MVPP2_BM_SHORT_FRAME_SIZE 512 +#define MVPP2_BM_LONG_FRAME_SIZE 2048 +#define MVPP2_BM_JUMBO_FRAME_SIZE 10240 /* BM short pool packet size * These value assure that for SWF the total number * of bytes allocated for each buffer will be 512 */ -#define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(512) +#define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_SHORT_FRAME_SIZE) +#define MVPP2_BM_LONG_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_LONG_FRAME_SIZE) +#define MVPP2_BM_JUMBO_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_JUMBO_FRAME_SIZE) #define MVPP21_ADDR_SPACE_SZ 0 #define MVPP22_ADDR_SPACE_SZ SZ_64K @@ -764,16 +856,64 @@ #define MVPP2_MAX_THREADS 8 #define MVPP2_MAX_QVECS MVPP2_MAX_THREADS -enum mvpp2_bm_type { - MVPP2_BM_FREE, - MVPP2_BM_SWF_LONG, - MVPP2_BM_SWF_SHORT +enum mvpp2_bm_pool_log_num { + MVPP2_BM_SHORT, + MVPP2_BM_LONG, + MVPP2_BM_JUMBO, + MVPP2_BM_POOLS_NUM }; +static struct { + int pkt_size; + int buf_num; +} mvpp2_pools[MVPP2_BM_POOLS_NUM]; + +/* GMAC MIB Counters register definitions */ +#define MVPP21_MIB_COUNTERS_OFFSET 0x1000 +#define MVPP21_MIB_COUNTERS_PORT_SZ 0x400 +#define MVPP22_MIB_COUNTERS_OFFSET 0x0 +#define MVPP22_MIB_COUNTERS_PORT_SZ 0x100 + +#define MVPP2_MIB_GOOD_OCTETS_RCVD 0x0 +#define MVPP2_MIB_BAD_OCTETS_RCVD 0x8 +#define MVPP2_MIB_CRC_ERRORS_SENT 0xc +#define MVPP2_MIB_UNICAST_FRAMES_RCVD 0x10 +#define MVPP2_MIB_BROADCAST_FRAMES_RCVD 0x18 +#define MVPP2_MIB_MULTICAST_FRAMES_RCVD 0x1c +#define MVPP2_MIB_FRAMES_64_OCTETS 0x20 +#define MVPP2_MIB_FRAMES_65_TO_127_OCTETS 0x24 +#define MVPP2_MIB_FRAMES_128_TO_255_OCTETS 0x28 +#define MVPP2_MIB_FRAMES_256_TO_511_OCTETS 0x2c +#define MVPP2_MIB_FRAMES_512_TO_1023_OCTETS 0x30 +#define MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34 +#define MVPP2_MIB_GOOD_OCTETS_SENT 0x38 +#define MVPP2_MIB_UNICAST_FRAMES_SENT 0x40 +#define MVPP2_MIB_MULTICAST_FRAMES_SENT 0x48 +#define MVPP2_MIB_BROADCAST_FRAMES_SENT 0x4c +#define MVPP2_MIB_FC_SENT 0x54 +#define MVPP2_MIB_FC_RCVD 0x58 +#define MVPP2_MIB_RX_FIFO_OVERRUN 0x5c +#define MVPP2_MIB_UNDERSIZE_RCVD 0x60 +#define MVPP2_MIB_FRAGMENTS_RCVD 0x64 +#define MVPP2_MIB_OVERSIZE_RCVD 0x68 +#define MVPP2_MIB_JABBER_RCVD 0x6c +#define MVPP2_MIB_MAC_RCV_ERROR 0x70 +#define MVPP2_MIB_BAD_CRC_EVENT 0x74 +#define MVPP2_MIB_COLLISION 0x78 +#define MVPP2_MIB_LATE_COLLISION 0x7c + +#define MVPP2_MIB_COUNTERS_STATS_DELAY (1 * HZ) + +#define MVPP2_DESC_DMA_MASK DMA_BIT_MASK(40) + /* Definitions */ /* Shared Packet Processor resources */ struct mvpp2 { +#ifdef CONFIG_MVPP2_FBX_FF + int id; +#endif + /* Shared registers' base addresses */ void __iomem *lms_base; void __iomem *iface_base; @@ -797,6 +937,7 @@ struct clk *axi_clk; /* List of pointers to port structures */ + int port_count; struct mvpp2_port **port_list; /* Aggregated TXQs */ @@ -818,6 +959,10 @@ /* Maximum number of RXQs per port */ unsigned int max_port_rxqs; + + /* Workqueue to gather hardware statistics */ + char queue_name[30]; + struct workqueue_struct *stats_queue; }; struct mvpp2_pcpu_stats { @@ -848,13 +993,44 @@ struct mvpp2_port *port; }; +/* + * ethtool private flags layout (stopgap measure until phylink is + * operational on mvpp2). + */ + +/* + * set to 1 only, cannot be cleared, enable 10G/1G media change logic. + */ +#define FBX_101G_SWITCH_EN_BIT 0 + +/* + * *_EN_BITS are write only, and must be only set one at a + * time. writing one to either of those effectively changes the mode + * of the interface to 1G (1000Base-X) or 10G (10000Base-KR). + * + * they are always 0 on read. + */ +#define FBX_10G_EN_BIT 1 +#define FBX_1G_EN_BIT 2 +#define FBX_ALL_EN_MASK ((1 << FBX_10G_EN_BIT) | (1 << FBX_1G_EN_BIT)) + +/* + * *_ST_BITS reflect the current state of 10G/1G media selection. + */ +#define FBX_10G_ST_BIT 3 +#define FBX_1G_ST_BIT 4 +#define FBX_SYNC_OK_BIT 5 +#define FBX_CLEAR_MIB_BIT 6 + struct mvpp2_port { u8 id; + unsigned int index; /* Index of the port from the "group of ports" complex point * of view */ int gop_id; + bool pending_10g_reset; int link_irq; @@ -862,6 +1038,7 @@ /* Per-port registers' base address */ void __iomem *base; + void __iomem *stats_base; struct mvpp2_rx_queue **rxqs; unsigned int nrxqs; @@ -880,13 +1057,17 @@ u16 tx_ring_size; u16 rx_ring_size; struct mvpp2_pcpu_stats __percpu *stats; + u64 *ethtool_stats; + + struct device_node *of_node; + + /* Per-port work and its lock to gather hardware statistics */ + struct mutex gather_stats_lock; + struct delayed_work stats_work; phy_interface_t phy_interface; - struct device_node *phy_node; + struct phylink *phylink; struct phy *comphy; - unsigned int link; - unsigned int duplex; - unsigned int speed; struct mvpp2_bm_pool *pool_long; struct mvpp2_bm_pool *pool_short; @@ -899,8 +1080,27 @@ bool has_tx_irqs; u32 tx_time_coal; + + /* RSS indirection table */ + u32 indir[MVPP22_RSS_TABLE_ENTRIES]; + + /* MII bus for MII bus access ioctls from userspace */ + struct mii_bus *mii_bus; + + /* FBX ratures */ + bool en_fbx_10g1g_switch; + +#ifdef CONFIG_MVPP2_FBX_FF + struct mvpp2_tx_queue *ff_txq; + struct notifier_block ff_notifier; +#endif }; +#ifdef CONFIG_MVPP2_FBX_FF +static struct mvpp2_port *ports_by_idx[4]; +#endif + + /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the * layout of the transmit and reception DMA descriptors, and their * layout is therefore defined by the hardware design @@ -975,7 +1175,7 @@ /* HW RX descriptor for PPv2.2 */ struct mvpp22_rx_desc { u32 status; - u16 reserved1; + u16 parser_info; u16 data_size; u32 reserved2; u32 reserved3; @@ -1004,6 +1204,13 @@ /* Transmitted SKB */ struct sk_buff *skb; +#ifdef CONFIG_MVPP2_FBX_FF + bool is_rx_buf; + int pool; + phys_addr_t bm_dma; + phys_addr_t bm_phys; +#endif + /* Physical address of transmitted buffer */ dma_addr_t dma; @@ -1023,6 +1230,13 @@ */ int count; +#ifdef CONFIG_MVPP2_FBX_FF + int release_pending; +#endif + + int wake_threshold; + int stop_threshold; + /* Number of Tx DMA descriptors reserved for each CPU */ int reserved_num; @@ -1145,7 +1359,6 @@ struct mvpp2_bm_pool { /* Pool number in the range 0-7 */ int id; - enum mvpp2_bm_type type; /* Buffer Pointers Pool External (BPPE) size */ int size; @@ -1185,6 +1398,15 @@ #define MVPP2_DRIVER_NAME "mvpp2" #define MVPP2_DRIVER_VERSION "1.0" +#ifdef CONFIG_MVPP2_FBX_FF +#define MVPP2_FF_TXQ_ID 7 +#define MVPP2_USABLE_TX_QUEUES 7 +#else +#define MVPP2_USABLE_TX_QUEUES 8 +#endif + +#define MVPP2_TX_FIXED_PRIO_QUEUES (1 << (MVPP2_USABLE_TX_QUEUES - 1)) + /* Utility/helper methods */ static void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data) @@ -1197,6 +1419,10 @@ return readl(priv->swth_base[0] + offset); } +static u32 mvpp2_read_relaxed(struct mvpp2 *priv, u32 offset) +{ + return readl_relaxed(priv->swth_base[0] + offset); +} /* These accessors should be used to access: * * - per-CPU registers, where each CPU has its own copy of the @@ -1245,26 +1471,45 @@ return readl(priv->swth_base[cpu] + offset); } +static void mvpp2_percpu_write_relaxed(struct mvpp2 *priv, int cpu, + u32 offset, u32 data) +{ + writel_relaxed(data, priv->swth_base[cpu] + offset); +} + +static u32 mvpp2_percpu_read_relaxed(struct mvpp2 *priv, int cpu, + u32 offset) +{ + return readl_relaxed(priv->swth_base[cpu] + offset); +} + static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port, struct mvpp2_tx_desc *tx_desc) { if (port->priv->hw_version == MVPP21) return tx_desc->pp21.buf_dma_addr; else - return tx_desc->pp22.buf_dma_addr_ptp & GENMASK_ULL(40, 0); + return tx_desc->pp22.buf_dma_addr_ptp & MVPP2_DESC_DMA_MASK; } static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port, struct mvpp2_tx_desc *tx_desc, dma_addr_t dma_addr) { + dma_addr_t addr, offset; + + addr = dma_addr & ~MVPP2_TX_DESC_ALIGN; + offset = dma_addr & MVPP2_TX_DESC_ALIGN; + if (port->priv->hw_version == MVPP21) { - tx_desc->pp21.buf_dma_addr = dma_addr; + tx_desc->pp21.buf_dma_addr = addr; + tx_desc->pp21.packet_offset = offset; } else { - u64 val = (u64)dma_addr; + u64 val = (u64)addr; - tx_desc->pp22.buf_dma_addr_ptp &= ~GENMASK_ULL(40, 0); + tx_desc->pp22.buf_dma_addr_ptp &= ~MVPP2_DESC_DMA_MASK; tx_desc->pp22.buf_dma_addr_ptp |= val; + tx_desc->pp22.packet_offset = offset; } } @@ -1307,16 +1552,6 @@ tx_desc->pp22.command = command; } -static void mvpp2_txdesc_offset_set(struct mvpp2_port *port, - struct mvpp2_tx_desc *tx_desc, - unsigned int offset) -{ - if (port->priv->hw_version == MVPP21) - tx_desc->pp21.packet_offset = offset; - else - tx_desc->pp22.packet_offset = offset; -} - static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port, struct mvpp2_tx_desc *tx_desc) { @@ -1332,7 +1567,7 @@ if (port->priv->hw_version == MVPP21) return rx_desc->pp21.buf_dma_addr; else - return rx_desc->pp22.buf_dma_addr_key_hash & GENMASK_ULL(40, 0); + return rx_desc->pp22.buf_dma_addr_key_hash & MVPP2_DESC_DMA_MASK; } static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port, @@ -1341,7 +1576,7 @@ if (port->priv->hw_version == MVPP21) return rx_desc->pp21.buf_cookie; else - return rx_desc->pp22.buf_cookie_misc & GENMASK_ULL(40, 0); + return rx_desc->pp22.buf_cookie_misc & MVPP2_DESC_DMA_MASK; } static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port, @@ -1362,6 +1597,15 @@ return rx_desc->pp22.status; } +static u16 mvpp2_rxdesc_parser_info_get(struct mvpp2_port *port, + struct mvpp2_rx_desc *rx_desc) +{ + if (port->priv->hw_version == MVPP21) + return 0; + else + return rx_desc->pp22.parser_info; +} + static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu) { txq_pcpu->txq_get_index++; @@ -1376,6 +1620,9 @@ { struct mvpp2_txq_pcpu_buf *tx_buf = txq_pcpu->buffs + txq_pcpu->txq_put_index; +#ifdef CONFIG_MVPP2_FBX_FF + tx_buf->is_rx_buf = false; +#endif tx_buf->skb = skb; tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc); tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) + @@ -1397,6 +1644,2042 @@ return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq; } +#ifdef CONFIG_MVPP2_FBX_FF + +static int mvpp2_aggr_desc_num_check(struct mvpp2 *priv, + struct mvpp2_tx_queue *aggr_txq, int num); + +static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending); + +static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool, + dma_addr_t buf_dma_addr, + phys_addr_t buf_phys_addr); + +static int mvpp2_rx_refill(struct mvpp2_port *port, + struct mvpp2_bm_pool *bm_pool, int pool); + +static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2 *priv, + struct mvpp2_tx_queue *txq, + struct mvpp2_txq_pcpu *txq_pcpu, + int num); + +static struct mvpp2_tx_desc * +mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq); + +static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port, + struct mvpp2_tx_queue *txq); + +static void mvpp2_txq_inc_put_ff(struct mvpp2_port *port, + dma_addr_t buf_dma, + phys_addr_t buf_phys, + int pool, + struct mvpp2_txq_pcpu *txq_pcpu, + struct mvpp2_tx_desc *tx_desc) +{ + struct mvpp2_txq_pcpu_buf *tx_buf = + txq_pcpu->buffs + txq_pcpu->txq_put_index; + + tx_buf->is_rx_buf = true; + tx_buf->pool = pool; + tx_buf->bm_dma = buf_dma; + tx_buf->bm_phys = buf_phys; + + txq_pcpu->txq_put_index++; + if (txq_pcpu->txq_put_index == txq_pcpu->size) + txq_pcpu->txq_put_index = 0; +} + +static bool ff_enabled; + +static DEFINE_SPINLOCK(ff_lock); + +static inline bool pkt_is_ipv4(u32 rx_status) +{ + u32 val; + + val = (rx_status >> 28) & 0x7; + if (val == 1 || val == 2 || val == 3) + return true; + + return false; +} + +static inline bool pkt_is_ipv6(u32 rx_status) +{ + u32 val; + + val = (rx_status >> 28) & 0x7; + if (val == 4 || val == 5) + return true; + + return false; +} + +static inline bool pkt_is_ipvx(u32 rx_status) +{ + return pkt_is_ipv4(rx_status) || pkt_is_ipv6(rx_status); +} + +static inline bool pkt_is_vlan(u16 parser_info) +{ + if (parser_info & (0x3 << 14)) + return true; + return false; +} + + +#define FF_DEV_SWLAN_ID 0 +#define FF_DEV_SWLAN_PORT_INDEX 1 + +#define FF_DEV_WAN_ID 0 +#define FF_DEV_WAN_PORT_INDEX 0 + +#define FF_DEV_SFPLAN_ID 1 +#define FF_DEV_SFPLAN_PORT_INDEX 0 + +static struct { + struct net_device *wan_dev; + struct net_device *lan_dev_sfp; + struct net_device *lan_dev_sw; + + unsigned long jiffies; + + struct net_device *tun_dev; + u8 tun_ready:1; + u16 tun_mtu; + + /* sit parameters */ + union ff_tun_params { + struct { + u32 src; + u32 s6rd_prefix; + u32 s6rd_pmask; + u8 s6rd_plen; + } sit; + + struct { + /* map parameters */ + u32 ipv4_prefix; + u32 ipv4_pmask; + u8 ipv4_plen; + u8 ipv6_plen; + struct in6_addr src; + struct in6_addr br; + + u64 ipv6_prefix; + u32 ea_addr_mask; + u16 ea_port_mask; + u8 psid_len; + u8 ea_lshift; + } map; + } u; + + char tun_dev_name[IFNAMSIZ]; +} ff; + +static LIST_HEAD(ff_devs); + +struct ff_dev { + const char *desc; + int id; + int port_index; + bool bridge_member; + unsigned int vlan; + struct net_device **pvirt_dev; + + char bridge_hwaddr[6]; + + bool active; + struct net_bridge_port *br_port; + struct fbxbr_port *fbxbr_port; + bool dev_up; + struct list_head next; +}; + +static struct ff_dev swlan; +static struct ff_dev sfplan; +static struct ff_dev wan; + +static inline bool is_bridge_dev(struct net_device *dev) +{ + return dev->priv_flags & IFF_EBRIDGE; +} + +static inline bool is_fbxbridge_port(struct net_device *dev) +{ + return dev->priv_flags & IFF_FBXBRIDGE_PORT; +} + +static u32 gen_netmask(u8 len) +{ + return htonl(~((1 << (32 - len)) - 1)); +} + +static void __ff_tun_set_params(bool ready, + unsigned int mtu, + const union ff_tun_params *tp) +{ + if (!ready) { + if (!ff.tun_ready) + return; + + printk(KERN_DEBUG "ff: tunnel now NOT ready\n"); + ff.tun_ready = 0; + return; + } + + if (ff.tun_ready) { + if (ff.tun_mtu == mtu && !memcmp(tp, &ff.u, sizeof (*tp))) + return; + } + + ff.tun_mtu = mtu; + memcpy(&ff.u, tp, sizeof (*tp)); + + if (!ff.tun_ready) + printk(KERN_DEBUG "ff: tunnel now ready\n"); + else + printk(KERN_DEBUG "ff: tunnel params updated\n"); + + ff.tun_ready = true; +} + +static void __ff_tun_read_params(void) +{ + union ff_tun_params tp; + + if (!ff.tun_dev) + return; + + if (!ff.wan_dev) { + __ff_tun_set_params(false, 0, NULL); + return; + } + + memset(&tp, 0, sizeof (tp)); + + if (ff.tun_dev->type == ARPHRD_SIT) { + const struct ip_tunnel *tun = netdev_priv(ff.tun_dev); + const struct ip_tunnel_6rd_parm *ip6rd = &tun->ip6rd; + + if (!ip6rd->prefixlen || ip6rd->prefixlen > 32) { + printk(KERN_DEBUG "ff: unsupported 6rd plen\n"); + __ff_tun_set_params(false, 0, NULL); + return; + } + + if (ff.tun_dev->mtu + sizeof (struct iphdr) > + ff.wan_dev->mtu) { + printk(KERN_DEBUG "ff: WAN mtu too " + "small for tunnel (%u => %u)\n", + ff.tun_dev->mtu, ff.wan_dev->mtu); + __ff_tun_set_params(false, 0, NULL); + return; + } + + tp.sit.src = tun->parms.iph.saddr; + tp.sit.s6rd_prefix = ip6rd->prefix.s6_addr32[0]; + tp.sit.s6rd_pmask = gen_netmask(ip6rd->prefixlen); + tp.sit.s6rd_plen = ip6rd->prefixlen; + __ff_tun_set_params(true, ff.tun_dev->mtu, &tp); + return; + } + + if (ff.tun_dev->type == ARPHRD_TUNNEL6) { + const struct ip6_tnl *t = netdev_priv(ff.tun_dev); + const struct __ip6_tnl_parm *prm = &t->parms; + const struct __ip6_tnl_fmr *fmr; + + if (ff.tun_dev->mtu + sizeof (struct ipv6hdr) > + ff.wan_dev->mtu) { + printk(KERN_DEBUG "ff: WAN mtu too " + "small for tunnel (%u => %u)\n", + ff.tun_dev->mtu, ff.wan_dev->mtu); + __ff_tun_set_params(false, 0, NULL); + return; + } + + tp.map.src = prm->laddr; + tp.map.br = prm->raddr; + + fmr = prm->fmrs; + if (!fmr) { + tp.map.ipv4_prefix = 0; + __ff_tun_set_params(true, ff.tun_dev->mtu, &tp); + return; + } + + if (fmr->ip6_prefix_len < 32 || + (fmr->ip6_prefix_len + 32 - fmr->ip4_prefix_len > 64)) { + printk(KERN_DEBUG "ff: unsupp MAP-E: eabits " + "span 32 bits\n"); + __ff_tun_set_params(false, 0, NULL); + return; + } + + if (fmr->offset) { + printk(KERN_DEBUG "ff: unsupp MAP-E: non zero " + "PSID offset\n"); + __ff_tun_set_params(false, 0, NULL); + return; + } + + tp.map.ipv4_prefix = fmr->ip4_prefix.s_addr; + tp.map.ipv4_pmask = gen_netmask(fmr->ip4_prefix_len); + tp.map.ipv4_plen = fmr->ip4_prefix_len; + tp.map.ipv6_plen = fmr->ip6_prefix_len; + memcpy(&tp.map.ipv6_prefix, &fmr->ip6_prefix, 8); + + tp.map.ea_addr_mask = ~gen_netmask(fmr->ip4_prefix_len); + if (fmr->ea_len <= 32 - fmr->ip4_prefix_len) { + /* v4 prefix or full IP */ + u32 addr_bits; + + addr_bits = fmr->ip4_prefix_len + fmr->ea_len; + if (addr_bits != 32) + tp.map.ea_addr_mask &= gen_netmask(addr_bits); + tp.map.psid_len = 0; + } else { + u8 psid_len; + + psid_len = fmr->ea_len - (32 - fmr->ip4_prefix_len); + tp.map.psid_len = psid_len; + tp.map.ea_port_mask = gen_netmask(psid_len); + } + + tp.map.ea_lshift = 32 - (fmr->ip6_prefix_len - 32) - + fmr->ea_len; + + __ff_tun_set_params(true, ff.tun_dev->mtu, &tp); + return; + } +} + +static void __ff_tun_capture(void) +{ + struct net_device *dev; + + if (ff.tun_dev) { + printk(KERN_ERR "ff: error: tun already registered\n"); + return; + } + + dev = dev_get_by_name(&init_net, ff.tun_dev_name); + if (!dev) { + return; + } + + if (dev->type != ARPHRD_SIT && dev->type != ARPHRD_TUNNEL6) { + return; + } + + if (!(dev->flags & IFF_UP)) { + dev_put(ff.tun_dev); + return; + } + + ff.tun_dev = dev; + __ff_tun_read_params(); + printk(KERN_INFO "ff: tun dev grabbed\n"); +} + +static void __ff_tun_release(void) +{ + int was_on = 0; + + if (ff.tun_dev) { + dev_put(ff.tun_dev); + ff.tun_dev = NULL; + was_on = 1; + } + if (was_on) + printk(KERN_INFO "ff: tun dev released\n"); +} + +static int ff_device_event(struct notifier_block *this, + unsigned long event, void *ptr) +{ + struct net_device *dev = netdev_notifier_info_to_dev(ptr); + struct mvpp2_port *port; + struct ff_dev *ff_dev; + + if (!net_eq(dev_net(dev), &init_net)) + return 0; + + if (!strcmp(dev->name, ff.tun_dev_name)) { + spin_lock_bh(&ff_lock); + + switch (event) { + case NETDEV_UP: + if (!ff.tun_dev) + __ff_tun_capture(); + break; + + case NETDEV_CHANGE: + case NETDEV_CHANGEMTU: + if (ff.tun_dev == dev) + __ff_tun_read_params(); + break; + + case NETDEV_GOING_DOWN: + case NETDEV_DOWN: + case NETDEV_UNREGISTER: + if (ff.tun_dev == dev) + __ff_tun_release(); + break; + } + + spin_unlock_bh(&ff_lock); + return 0; + } + + port = container_of(this, typeof(*port), ff_notifier); + list_for_each_entry(ff_dev, &ff_devs, next) { + if (port->priv->id != ff_dev->id) + continue; + if (port->index != ff_dev->port_index) + continue; + + if (ff_dev->vlan) { + if (!is_vlan_dev(dev)) + continue; + + switch (event) { + case NETDEV_UP: + if (vlan_dev_upper_dev(dev) != port->dev || + vlan_dev_vlan_id(dev) != ff_dev->vlan) + continue; + + if (ff_dev->active) + continue; + + dev_hold(dev); + + spin_lock_bh(&ff_lock); + *(ff_dev->pvirt_dev) = dev; + + if (ff_dev->pvirt_dev == &ff.wan_dev) + __ff_tun_read_params(); + spin_unlock_bh(&ff_lock); + + ff_dev->active = true; + printk(KERN_INFO "ff: ff_dev %s: active " + "for %s\n", ff_dev->desc, + dev->name); + break; + + case NETDEV_GOING_DOWN: + case NETDEV_DOWN: + case NETDEV_UNREGISTER: + if (!ff_dev->active) + continue; + + if (vlan_dev_upper_dev(dev) != port->dev || + vlan_dev_vlan_id(dev) != ff_dev->vlan) + continue; + + spin_lock_bh(&ff_lock); + *(ff_dev->pvirt_dev) = NULL; + spin_unlock_bh(&ff_lock); + dev_put(dev); + ff_dev->active = false; + + printk(KERN_INFO "ff: ff_dev %s: now " + "inactive\n", ff_dev->desc); + break; + + default: + break; + } + } + + if (ff_dev->bridge_member) { + struct net_bridge *br; + struct fbxbr *fbxbr; + bool ok; + + switch (event) { + case NETDEV_UP: + if (dev == port->dev) + ff_dev->dev_up = true; + break; + + case NETDEV_GOING_DOWN: + case NETDEV_DOWN: + case NETDEV_UNREGISTER: + if (dev == port->dev) + ff_dev->dev_up = false; + break; + + case NETDEV_CHANGEUPPER: + if (dev == port->dev) { + rcu_read_lock(); + if ((dev->priv_flags & + IFF_BRIDGE_PORT) && + netdev_master_upper_dev_get(dev)) + ff_dev->br_port = br_port_get_rcu(dev); + else + ff_dev->br_port = NULL; + + if ((dev->priv_flags & + IFF_FBXBRIDGE_PORT) && + netdev_master_upper_dev_get(dev)) + ff_dev->fbxbr_port = fbxbr_port_get_rcu(dev); + else + ff_dev->fbxbr_port = NULL; + rcu_read_unlock(); + } + break; + + default: + break; + } + + ok = false; + br = NULL; + fbxbr = NULL; + if (ff_dev->dev_up && ff_dev->br_port) { + br = ff_dev->br_port->br; + if (br->dev->flags & IFF_UP) + ok = true; + } + + if (ff_dev->dev_up && ff_dev->fbxbr_port) { + fbxbr = ff_dev->fbxbr_port->br; + if (fbxbr->dev->flags & IFF_UP) + ok = true; + } + + if (!(ok ^ ff_dev->active)) + continue; + + if (ok) { + struct net_device *true_dev; + + if (br) { + true_dev = br->dev; + } else { + true_dev = port->dev; + } + + dev_hold(true_dev); + spin_lock_bh(&ff_lock); + *(ff_dev->pvirt_dev) = true_dev; + spin_unlock_bh(&ff_lock); + + if (br) + memcpy(ff_dev->bridge_hwaddr, + br->dev->dev_addr, 6); + ff_dev->active = true; + + printk(KERN_INFO "ff: ff_dev %s: active " + "for %s\n", ff_dev->desc, + true_dev->name); + + + } else { + dev = *(ff_dev->pvirt_dev); + spin_lock_bh(&ff_lock); + *(ff_dev->pvirt_dev) = NULL; + spin_unlock_bh(&ff_lock); + dev_put(dev); + ff_dev->active = false; + memset(ff_dev->bridge_hwaddr, 0, 6); + printk(KERN_INFO "ff: ff_dev %s: " + "now inactive\n", ff_dev->desc); + } + } + } + + return 0; +} + +enum ff_xmit_mode { + FF_XMIT_IPV4, + FF_XMIT_IPV6, + FF_XMIT_IPV6_IN_IPV4, + FF_XMIT_IPV4_IN_IPV6, +}; + +static void mvpp2_frag_free(const struct mvpp2_bm_pool *pool, void *data); +static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv, + struct mvpp2_bm_pool *bm_pool, + dma_addr_t *dma_addr, + phys_addr_t *phys_addr); + +/* + * + */ +static bool ff_force_reclaim(struct mvpp2_port *port, + struct mvpp2_bm_pool *bm_pool, + unsigned int count) +{ + struct mvpp2_tx_queue *txq; + struct mvpp2_txq_pcpu *txq_pcpu; + struct device *device; + bool done; + + txq = port->ff_txq; + txq_pcpu = this_cpu_ptr(txq->pcpu); + + txq_pcpu->release_pending += mvpp2_txq_sent_desc_proc(port, txq); + device = port->dev->dev.parent; + + done = false; + while (txq_pcpu->count > count && txq_pcpu->release_pending) { + struct mvpp2_txq_pcpu_buf *tx_buf; + void *data; + + tx_buf = txq_pcpu->buffs + txq_pcpu->txq_get_index; + if (WARN_ON(!tx_buf->is_rx_buf)) + continue; + + dma_unmap_single(device, + tx_buf->bm_dma, + MVPP2_RX_BUF_SIZE(bm_pool->pkt_size), + DMA_FROM_DEVICE); + + data = (void *)phys_to_virt(tx_buf->bm_dma); + mvpp2_frag_free(bm_pool, data); + txq_pcpu->release_pending--; + txq_pcpu->count--; + mvpp2_txq_inc_get(txq_pcpu); + done = true; + } + return done; +} + +/* + * + */ +static bool ff_can_send(struct mvpp2_port *port, + struct mvpp2_bm_pool *bm_pool) +{ + struct mvpp2_tx_queue *txq; + struct mvpp2_txq_pcpu *txq_pcpu; + + txq = port->ff_txq; + txq_pcpu = this_cpu_ptr(txq->pcpu); + + /* make sure tx queue is not full */ + if (txq_pcpu->count == txq_pcpu->size) { + txq_pcpu->release_pending += + mvpp2_txq_sent_desc_proc(port, txq); + if (!txq_pcpu->release_pending) { + /* if (net_ratelimit()) */ + /* printk("ff: %s: txq_pcpu is full (%u)\n", */ + /* port->dev->name, */ + /* txq_pcpu->count); */ + return false; + } + } + + if (txq_pcpu->count < (txq_pcpu->size / 2)) + return true; + + ff_force_reclaim(port, bm_pool, txq_pcpu->size / 2); + return true; +} + +/* + * + */ +static bool ff_ensure_tx_desc(struct mvpp2_port *port, + struct mvpp2_bm_pool *bm_pool) +{ + struct mvpp2_tx_queue *txq, *aggr_txq; + struct mvpp2_txq_pcpu *txq_pcpu; + + txq = port->ff_txq; + txq_pcpu = this_cpu_ptr(txq->pcpu); + + /* make sure there is space in the aggregated tx queue */ + aggr_txq = &port->priv->aggr_txqs[smp_processor_id()]; + if (mvpp2_aggr_desc_num_check(port->priv, aggr_txq, 1)) { + if (net_ratelimit()) + printk("ff: %s: failed to get 1 desc in aggr tx queue\n", + port->dev->name); + return false; + } + + /* make sure we have space reserved in the ff txq */ + if (!mvpp2_txq_reserved_desc_num_proc(port->priv, txq, txq_pcpu, 1)) + return true; + + ff_force_reclaim(port, bm_pool, txq_pcpu->size / 2); + + if (!mvpp2_txq_reserved_desc_num_proc(port->priv, txq, txq_pcpu, 1)) + return true; + + return false; +} + +/* + * + */ +static void ff_send(struct mvpp2_port *port, + dma_addr_t dma_buf_addr, + phys_addr_t dma_buf_phys, + unsigned int dma_buf_offset, + int dma_buf_pool, + unsigned int send_len, + bool is_ipv4, + bool is_tcp_or_udp, + bool is_tcp, + bool is_vlan) +{ + struct mvpp2_tx_queue *txq, *aggr_txq; + struct mvpp2_txq_pcpu *txq_pcpu; + struct mvpp2_tx_desc *tx_desc; + u32 tx_cmd; + + aggr_txq = &port->priv->aggr_txqs[smp_processor_id()]; + txq = port->ff_txq; + txq_pcpu = this_cpu_ptr(txq->pcpu); + + /* Get a descriptor for packet */ + tx_desc = mvpp2_txq_next_desc_get(aggr_txq); + memset(tx_desc, 0, sizeof (*tx_desc)); + mvpp2_txdesc_txq_set(port, tx_desc, txq->id); + mvpp2_txdesc_size_set(port, tx_desc, send_len); + mvpp2_txdesc_dma_addr_set(port, tx_desc, + dma_buf_addr + dma_buf_offset); + + if (is_vlan) + tx_cmd = (VLAN_ETH_HLEN << MVPP2_TXD_L3_OFF_SHIFT); + else + tx_cmd = (ETH_HLEN << MVPP2_TXD_L3_OFF_SHIFT); + + if (is_ipv4) { + /* 20 is sizeof (ipv4) */ + tx_cmd |= ((20 >> 2) << MVPP2_TXD_IP_HLEN_SHIFT); + } else { + /* 40 is sizeof (ip6hdr) */ + tx_cmd |= ((40 >> 2) << MVPP2_TXD_IP_HLEN_SHIFT); + tx_cmd |= MVPP2_TXD_IP_CSUM_DISABLE; + tx_cmd |= MVPP2_TXD_L3_IP6; + } + + if (is_tcp_or_udp) { + if (!is_tcp) + tx_cmd |= MVPP2_TXD_L4_UDP; + } else { + tx_cmd |= MVPP2_TXD_L4_CSUM_NOT; + } + + /* First and Last descriptor */ + tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC; + mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); + mvpp2_txq_inc_put_ff(port, + dma_buf_addr, + dma_buf_phys, + dma_buf_pool, + txq_pcpu, tx_desc); + + txq_pcpu->reserved_num--; + txq_pcpu->count++; + aggr_txq->count++; + + /* Enable transmit */ + wmb(); + mvpp2_aggr_txq_pend_desc_add(port, 1); +} + +/* + * ipv4 forward cache private data + */ +struct ff_priv { + struct in6_addr tun_dest_ip6; + struct dst_entry *tun_dst; +}; + +static void ff_priv_release(const struct ff_priv *priv) +{ + dst_release(priv->tun_dst); +} + +static void ff_priv_destructor_cb(void *data) +{ + const struct ff_priv *priv = (const struct ff_priv *)data; + ff_priv_release(priv); +} + +static const struct ff_priv *ffn_get_ro_priv(const struct ffn_lookup_entry *e) +{ + if (e->manip.priv_destructor != ff_priv_destructor_cb) + return NULL; + + return (const struct ff_priv *)e->manip.ffn_priv_area; +} + +static struct ff_priv *ffn_get_rw_priv(struct ffn_lookup_entry *e) +{ + BUILD_BUG_ON(sizeof (e->manip.ffn_priv_area) < + sizeof (struct ff_priv)); + + if (e->manip.priv_destructor && + e->manip.priv_destructor != ff_priv_destructor_cb) + return NULL; + + return (struct ff_priv *)e->manip.ffn_priv_area; +} + +static const struct ff_priv *fwc_get_ro_priv(const struct fbxbr_fwcache *fwc) +{ + if (fwc->priv_destructor != ff_priv_destructor_cb) + return NULL; + + return (const struct ff_priv *)fwc->priv_area; +} + +static struct ff_priv *fwc_get_rw_priv(const struct fbxbr_fwcache *fwc) +{ + BUILD_BUG_ON(sizeof (fwc->priv_area) < sizeof (struct ff_priv)); + + if (fwc->priv_destructor && + fwc->priv_destructor != ff_priv_destructor_cb) + return NULL; + + return (struct ff_priv *)fwc->priv_area; +} + +/* + * ipv6 forward cache private data + */ +struct ff6_priv { + u32 tun_dest_ip; + struct dst_entry *tun_dst; +}; + +static void ff6_priv_release(const struct ff6_priv *priv) +{ + dst_release(priv->tun_dst); +} + +static void ff6_priv_destructor_cb(void *data) +{ + const struct ff6_priv *priv = (const struct ff6_priv *)data; + ff6_priv_release(priv); +} + +static const struct ff6_priv *ffn6_get_ro_priv(const struct ffn6_lookup_entry *e6) +{ + if (e6->manip.priv_destructor != ff6_priv_destructor_cb) + return NULL; + + return (const struct ff6_priv *)e6->manip.ffn_priv_area; +} + +static struct ff6_priv *ffn6_get_rw_priv(struct ffn6_lookup_entry *e6) +{ + BUILD_BUG_ON(sizeof (e6->manip.ffn_priv_area) < + sizeof (struct ff6_priv)); + + if (e6->manip.priv_destructor && + e6->manip.priv_destructor != ff6_priv_destructor_cb) + return NULL; + + return (struct ff6_priv *)e6->manip.ffn_priv_area; +} + +/* + * + */ +static u32 ff_tun_extract_6rd_addr(const struct in6_addr *d) +{ + u32 a1, a2; + + a1 = ntohl(d->s6_addr32[0] & ~ff.u.sit.s6rd_pmask); + a1 <<= ff.u.sit.s6rd_plen; + + a2 = ntohl(d->s6_addr32[1] & ff.u.sit.s6rd_pmask); + a2 >>= (32 - ff.u.sit.s6rd_plen); + return htonl(a1 | a2); +} + +/* + * + */ +static void ff_tun_gen_mape_addr(u32 addr, u16 port, struct in6_addr *dest) +{ + u32 eabits; + u16 psid; + + eabits = ntohl(addr & ff.u.map.ea_addr_mask) << ff.u.map.psid_len; + psid = 0; + if (ff.u.map.psid_len) { + psid = ntohs(port & ff.u.map.ea_port_mask) >> + (16 - ff.u.map.psid_len); + eabits |= psid; + } + + memcpy(dest, &ff.u.map.ipv6_prefix, 8); + dest->s6_addr32[1] |= htonl(eabits << ff.u.map.ea_lshift); + + dest->s6_addr32[2] = htonl(ntohl(addr) >> 16); + dest->s6_addr32[3] = htonl((ntohl(addr) << 16) | psid); +} + +/* + * + */ +static bool ff_forward(struct mvpp2_port *rx_port, + const uint8_t *rx_alt_hwaddr, + int pool, + struct mvpp2_port *tx_port1, + struct mvpp2_port *tx_port2, + const uint8_t *tx_alt_hwaddr, + bool wan_to_lan, + struct net_device *rx_dev, + struct net_device *tx_dev, + unsigned int rx_vlan, + unsigned int tx_vlan, + struct mvpp2_rx_desc *rx_desc, + void *frag, + size_t offset, size_t eth_len) +{ + struct mvpp2_bm_pool *bm_pool; + struct net_device_stats *rx_hw_stats; + struct net_device_stats *tx_hw_stats; + struct mvpp2_port *tx_port; + struct net_device *last_rx_dev, *next_tx_dev; + struct ffn_lookup_entry *e; + struct ffn6_lookup_entry *e6; + struct nf_conn *ct = NULL; + struct ethhdr *eth; + enum ff_xmit_mode xmit_mode; + u8 dest_hw[6]; + unsigned int timeout; + void *l3_hdr, *l4_hdr; + bool l3_is_ipv4, l4_is_tcp; + unsigned int l3_plen; + u32 tun_v4_dest; + const struct in6_addr *tun_v6_pdest; + u32 rx_status; + u16 proto, parser_info; + dma_addr_t frag_dma_addr; + phys_addr_t frag_phys_addr; + const uint8_t *src_hwaddr; + + /* make sure we have headroom for the worst case scenario */ + BUILD_BUG_ON(NET_SKB_PAD < + (sizeof (struct ipv6hdr) + VLAN_HLEN)); + + if (!tx_port1 || !rx_port || !tx_dev || !rx_dev) + return false; + + eth = (struct ethhdr *)((uint8_t *)frag + offset); + rx_status = mvpp2_rxdesc_status_get(rx_port, rx_desc); + parser_info = mvpp2_rxdesc_parser_info_get(rx_port, rx_desc); + + /* + * filter only IPv4 & IPv6 packets + */ + if (rx_vlan) { + struct vlan_ethhdr *vhdr; + + if (!pkt_is_vlan(parser_info)) + return false; + + vhdr = (struct vlan_ethhdr *)eth; + if (vhdr->h_vlan_TCI != htons(rx_vlan)) + return false; + + if (!pkt_is_ipvx(rx_status)) + return false; + + l3_hdr = vhdr + 1; + l3_plen = eth_len - VLAN_ETH_HLEN; + } else { + if (pkt_is_vlan(parser_info)) + return false; + + if (!pkt_is_ipvx(rx_status)) + return false; + + l3_hdr = eth + 1; + l3_plen = eth_len - ETH_HLEN; + } + + /* make sure packet is for our mac address */ + if (memcmp(eth->h_dest, rx_port->dev->dev_addr, 6)) { + if (!rx_alt_hwaddr || memcmp(eth->h_dest, rx_alt_hwaddr, 6)) + return false; + } + + last_rx_dev = rx_dev; + l3_is_ipv4 = pkt_is_ipv4(rx_status); + + if (l3_is_ipv4) { + struct iphdr *iph; + struct fbxbr_fwcache *fwc; + struct fbxbr *fbxbr; + struct fbxbr_port *fbxbr_fwd_port; + u16 sport, dport; + u8 ip_proto; + +handle_ipv4: + iph = (struct iphdr *)l3_hdr; + + /* lookup IP ffn entry */ + if (iph->ihl > 5 || (iph->frag_off & htons(IP_MF | IP_OFFSET))) + return false; + + if (iph->ttl <= 1) + return false; + + ip_proto = iph->protocol; + if (ip_proto == IPPROTO_TCP) { + struct tcphdr *tcph; + + if (l3_plen < sizeof (*iph) + sizeof (*tcph)) + return false; + + tcph = (struct tcphdr *)((u8 *)iph + 20); + if (tcph->fin || + tcph->syn || + tcph->rst || + !tcph->ack) { + return false; + } + + sport = tcph->source; + dport = tcph->dest; + l4_hdr = tcph; + l4_is_tcp = true; + + } else if (ip_proto == IPPROTO_UDP) { + struct udphdr *udph; + + if (l3_plen < sizeof (*iph) + sizeof (*udph)) + return false; + + udph = (struct udphdr *)((u8 *)iph + 20); + sport = udph->source; + dport = udph->dest; + l4_hdr = udph; + l4_is_tcp = false; + + } else if (ip_proto == IPPROTO_IPV6) { + struct ipv6hdr *ip6hdr; + u32 ip6rd_daddr; + + if (!ff.tun_ready) + return false; + + /* must be for us */ + if (iph->daddr != ff.u.sit.src) + return false; + + /* check len */ + if (l3_plen < sizeof (struct iphdr) + + sizeof (struct ipv6hdr)) + return false; + + ip6hdr = (struct ipv6hdr *)(iph + 1); + + /* must belong to 6rd prefix */ + if ((ip6hdr->daddr.s6_addr32[0] & + ff.u.sit.s6rd_pmask) != ff.u.sit.s6rd_prefix) + return false; + + /* 6rd address */ + ip6rd_daddr = ff_tun_extract_6rd_addr(&ip6hdr->daddr); + if (ip6rd_daddr != ff.u.sit.src) + return false; + + /* TODO: should check for spoofing here */ + l3_hdr = ip6hdr; + l3_plen -= 20; + l3_is_ipv4 = false; + goto handle_ipv6; + + } else + return false; + + if (is_fbxbridge_port(last_rx_dev)) { + struct fbxbr_fwcache_key k; + struct fbxbr_port *p; + u32 hash; + + p = fbxbr_port_get_rcu(last_rx_dev); + fbxbr = p->br; + + if (wan_to_lan) { + WARN_ON(!p->is_wan); + k.wan_ip = iph->saddr; + k.lan_ip = iph->daddr; + k.wan_port = sport; + k.lan_port = dport; + fbxbr_fwd_port = fbxbr->lan_port; + } else { + WARN_ON(p->is_wan); + k.lan_ip = iph->saddr; + k.wan_ip = iph->daddr; + k.lan_port = sport; + k.wan_port = dport; + fbxbr_fwd_port = fbxbr->wan_port; + } + k.is_tcp = l4_is_tcp; + + if (!unlikely(fbxbr_fwd_port)) + return false; + + hash = fbxbr_fwcache_hash(&k); + fwc = __fbxbr_fwcache_lookup(p->br, hash, &k); + if (!fwc) + return false; + + next_tx_dev = fbxbr_fwd_port->dev; + e = NULL; + } else { + e = __ffn_get(iph->saddr, iph->daddr, + sport, dport, l4_is_tcp); + if (!e) + return false; + + if (e->manip.dst->obsolete > 0) + return false; + + ct = e->manip.ct; + + /* only fast forward TCP connections in established state */ + if (l4_is_tcp && + ct->proto.tcp.state != TCP_CONNTRACK_ESTABLISHED) + return false; + + next_tx_dev = e->manip.dst->dev; + fwc = NULL; + } + + /* find out if the packet is to be sent as-is or + * tunneled */ + if (ff.tun_dev && next_tx_dev == ff.tun_dev) { + const struct ff_priv *ff_priv; + struct ff_priv *ff_wpriv; + struct dst_entry *v6_dst; + const struct in6_addr *pdest, *nexthop; + struct in6_addr dest; + struct rt6_info *rt6; + struct neighbour *neigh; + + /* IPv4 tunneled into MAP-E device */ + if (!ff.tun_ready) { + return false; + } + + if (l3_plen > ff.tun_mtu) + return false; + + /* lookup ipv6 route cache */ + if (e) + ff_priv = ffn_get_ro_priv(e); + else + ff_priv = fwc_get_ro_priv(fwc); + + if (ff_priv) { + if (ff_priv->tun_dst->obsolete < 0) { + /* valid route found */ + v6_dst = ff_priv->tun_dst; + pdest = &ff_priv->tun_dest_ip6; + goto cached_ipv6_route; + } + + ff_priv_release(ff_priv); + if (e) + e->manip.priv_destructor = NULL; + else + fwc->priv_destructor = NULL; + } + + /* cache miss, compute IPv6 destination */ + if (ff.u.map.ipv4_prefix && + (iph->daddr & ff.u.map.ipv4_pmask) == + ff.u.map.ipv4_prefix) { + /* compute dest using FMR */ + ff_tun_gen_mape_addr(iph->daddr, dport, &dest); + pdest = &dest; + } else { + /* next hop is BR */ + pdest = &ff.u.map.br; + } + + /* v6 route lookup */ + rt6 = rt6_lookup(&init_net, pdest, NULL, 0, 0); + if (!rt6) + return false; + + if (e) + ff_wpriv = ffn_get_rw_priv(e); + else + ff_wpriv = fwc_get_rw_priv(fwc); + if (!ff_wpriv) + return false; + + /* cache this inside FFN private area */ + ff_wpriv->tun_dst = (struct dst_entry *)rt6; + memcpy(&ff_wpriv->tun_dest_ip6, pdest, 16); + if (e) + e->manip.priv_destructor = ff_priv_destructor_cb; + else + fwc->priv_destructor = ff_priv_destructor_cb; + ff_priv = ff_wpriv; + + v6_dst = (struct dst_entry *)rt6; + +cached_ipv6_route: + if (v6_dst->dev != tx_dev) { + return false; + } + + /* is the neighboor ready ? */ + rt6 = (struct rt6_info *)v6_dst; + nexthop = rt6_nexthop(rt6, (struct in6_addr *)pdest); + if (!nexthop) { + return false; + } + + neigh = __ipv6_neigh_lookup_noref(tx_dev, nexthop); + if (!neigh || !(neigh->nud_state & NUD_VALID)) + return false; + memcpy(dest_hw, neigh->ha, 6); + + xmit_mode = FF_XMIT_IPV4_IN_IPV6; + tun_v6_pdest = &ff_priv->tun_dest_ip6; + + } else if (next_tx_dev == tx_dev) { + struct neighbour *neigh; + const struct rtable *rt; + + /* is the neighboor ready ? */ + if (e) { + u32 nexthop; + + rt = (const struct rtable *)e->manip.dst; + nexthop = (__force u32)rt_nexthop(rt, + e->manip.new_dip); + neigh = __ipv4_neigh_lookup_noref(tx_dev, + nexthop); + if (!neigh || !(neigh->nud_state & NUD_VALID)) + return false; + + memcpy(dest_hw, neigh->ha, 6); + } else { + if (!fbxbr_fwd_port->is_wan) { + if (!fbxbr->have_hw_addr) + return false; + memcpy(dest_hw, fbxbr->lan_hwaddr, 6); + } else { + __be32 nh; + + nh = iph->daddr; + if ((nh & fbxbr->wan_netmask) != + (fbxbr->wan_ipaddr & + fbxbr->wan_netmask)) { + rt = fbxbr_fwd_port->rt; + if (!rt || + rt->dst.obsolete > 0) + return false; + + nh = rt_nexthop(rt, nh); + } + + neigh = __ipv4_neigh_lookup_noref( + tx_dev, nh); + if (!neigh || + !(neigh->nud_state & NUD_VALID)) + return false; + + memcpy(dest_hw, neigh->ha, 6); + } + } + + xmit_mode = FF_XMIT_IPV4; + } else + return false; + + } else { + struct ipv6hdr *ip6hdr; + u16 sport, dport; + u8 ip_proto; + +handle_ipv6: + ip6hdr = (struct ipv6hdr *)l3_hdr; + + if (ip6hdr->hop_limit <= 1 || !ip6hdr->payload_len) + return false; + + if (ntohs(ip6hdr->payload_len) > l3_plen) + return false; + + ip_proto = ip6hdr->nexthdr; + + if (ip_proto == IPPROTO_TCP) { + struct tcphdr *tcph; + + if (l3_plen < sizeof (*ip6hdr) + sizeof (*tcph)) + return false; + + tcph = (struct tcphdr *)((u8 *)ip6hdr + + sizeof (*ip6hdr)); + + if (tcph->fin || + tcph->syn || + tcph->rst || + !tcph->ack) { + return false; + } + + sport = tcph->source; + dport = tcph->dest; + l4_hdr = tcph; + l4_is_tcp = true; + + } else if (ip_proto == IPPROTO_UDP) { + struct udphdr *udph; + + if (l3_plen < sizeof (*ip6hdr) + sizeof (*udph)) + return false; + + udph = (struct udphdr *)((u8 *)ip6hdr + + sizeof (*ip6hdr)); + sport = udph->source; + dport = udph->dest; + l4_hdr = udph; + l4_is_tcp = false; + + } else if (ip_proto == IPPROTO_IPIP) { + struct iphdr *iph; + + if (!ff.tun_ready) + return false; + + /* must be for us */ + if (memcmp(&ip6hdr->daddr, &ff.u.map.src, 16)) + return false; + + /* check len */ + if (l3_plen < sizeof (struct iphdr) + + sizeof (struct ipv6hdr)) + return false; + + iph = (struct iphdr *)(ip6hdr + 1); + + /* does it come from BR ? */ + if (memcmp(&ip6hdr->saddr, &ff.u.map.br, 16)) { + struct in6_addr exp_src_addr; + + /* no, check FMR for spoofing */ + if (!ff.u.map.ipv4_prefix) + return false; + + /* check up to PSID to reduce lookup + * depth */ + ff_tun_gen_mape_addr(iph->saddr, 0, + &exp_src_addr); + if (!ipv6_prefix_equal(&ip6hdr->saddr, + &exp_src_addr, + ff.u.map.ipv6_plen + + ff.u.map.ipv4_plen)) + return false; + } + + last_rx_dev = ff.tun_dev; + if (!last_rx_dev) + return false; + + l3_hdr = iph; + l3_plen -= sizeof (*ip6hdr); + l3_is_ipv4 = true; + goto handle_ipv4; + + } else + return false; + + e6 = __ffn6_get(ip6hdr->saddr.s6_addr32, + ip6hdr->daddr.s6_addr32, + sport, dport, l4_is_tcp); + + if (!e6) { + return false; + } + + if (e6->manip.dst->obsolete > 0) { + return false; + } + + ct = e6->manip.ct; + + /* only fast forward TCP connections in established state */ + if (l4_is_tcp && + ct->proto.tcp.state != TCP_CONNTRACK_ESTABLISHED) { + return false; + } + + /* find out if the packet is to be sent as-is or + * tunneled */ + if (ff.tun_dev && e6->manip.dst->dev == ff.tun_dev) { + const struct ff6_priv *ff6_priv; + struct ff6_priv *ff6_wpriv; + struct dst_entry *v4_dst; + struct flowi4 fl4; + struct rtable *rt; + struct neighbour *neigh; + u32 dest, nexthop; + + /* IPv6 tunneled into SIT device using 6rd */ + if (!ff.tun_ready) { + return false; + } + + if (l3_plen > ff.tun_mtu) + return false; + + /* lookup ipv4 route cache */ + ff6_priv = ffn6_get_ro_priv(e6); + if (ff6_priv) { + if (!ff6_priv->tun_dst->obsolete) { + /* valid route found */ + v4_dst = ff6_priv->tun_dst; + dest = ff6_priv->tun_dest_ip; + goto cached_ipv4_route; + } + + ff6_priv_release(ff6_priv); + e6->manip.priv_destructor = NULL; + } + + /* cache miss, compute IPv4 destination */ + if ((ip6hdr->daddr.s6_addr32[0] & + ff.u.sit.s6rd_pmask) == ff.u.sit.s6rd_prefix) { + /* next hop via prefix */ + dest = ff_tun_extract_6rd_addr(&ip6hdr->daddr); + } else { + struct in6_addr *nh6; + struct rt6_info *rt6; + + /* next hop via route */ + rt6 = (struct rt6_info *)e6->manip.dst; + nh6 = rt6_nexthop(rt6, + (struct in6_addr *)e6->manip.new_dip); + if (!nh6) { + return false; + } + + /* should be a v4 mapped */ + if (nh6->s6_addr32[0] != 0 || + nh6->s6_addr32[1] != 0 || + nh6->s6_addr32[2] != 0) { + return false; + } + + dest = nh6->s6_addr32[3]; + } + + /* v4 route lookup */ + rt = ip_route_output_ports(&init_net, &fl4, NULL, + dest, ff.u.sit.src, + 0, 0, + IPPROTO_IPV6, 0, + 0); + if (IS_ERR(rt) || + rt->rt_type != RTN_UNICAST) + return false; + + ff6_wpriv = ffn6_get_rw_priv(e6); + if (!ff6_wpriv) + return false; + + /* cache this inside FFN private area */ + ff6_wpriv->tun_dst = (struct dst_entry *)rt; + ff6_wpriv->tun_dest_ip = dest; + e6->manip.priv_destructor = ff6_priv_destructor_cb; + + v4_dst = (struct dst_entry *)rt; + ff6_priv = ff6_wpriv; + +cached_ipv4_route: + if (v4_dst->dev != tx_dev) { + return false; + } + + /* is the neighboor ready ? */ + rt = (struct rtable *)v4_dst; + nexthop = (__force u32)rt_nexthop(rt, dest); + neigh = __ipv4_neigh_lookup_noref(tx_dev, nexthop); + if (!neigh || !(neigh->nud_state & NUD_VALID)) + return false; + memcpy(dest_hw, neigh->ha, 6); + + tun_v4_dest = dest; + xmit_mode = FF_XMIT_IPV6_IN_IPV4; + + } else if (e6->manip.dst->dev == tx_dev) { + struct in6_addr *nexthop; + struct rt6_info *rt6; + struct neighbour *neigh; + + /* is the neighboor ready ? */ + rt6 = (struct rt6_info *)e6->manip.dst; + + nexthop = rt6_nexthop(rt6, + (struct in6_addr *)e6->manip.new_dip); + if (!nexthop) + return false; + + neigh = __ipv6_neigh_lookup_noref(tx_dev, nexthop); + if (!neigh || !(neigh->nud_state & NUD_VALID)) + return false; + memcpy(dest_hw, neigh->ha, 6); + + xmit_mode = FF_XMIT_IPV6; + } else + return false; + } + + /* is destination on correct tx bridge port ? */ + if (!is_bridge_dev(tx_dev)) + tx_port = tx_port1; + else { + struct net_bridge_port *p1, *p2; + struct net_bridge_fdb_entry *fdb; + + p1 = br_port_get_rcu(tx_port1->dev); + p2 = NULL; + if (tx_port2) + p2 = br_port_get_rcu(tx_port2->dev); + + fdb = br_fdb_find_rcu(p1->br, dest_hw, 0); + if (!fdb) + return false; + + if (fdb->dst == p1) + tx_port = tx_port1; + else if (fdb->dst == p2) + tx_port = tx_port2; + else + return false; + } + + if (is_bridge_dev(rx_dev)) { + struct net_bridge *br = netdev_priv(rx_dev); + struct net_bridge_port *p; + struct pcpu_sw_netstats *stats; + + /* if packet comes from a bridge, make sure we are + * allowed to ingress it */ + p = br_port_get_rcu(rx_port->dev); + if (p->state != BR_STATE_FORWARDING) { + return false; + } + + /* refresh FDB entry for this source */ + if (!br_fdb_update_only(br, p, eth->h_source)) { + return false; + } + + stats = this_cpu_ptr(br->stats); + stats->rx_packets++; + stats->rx_bytes += eth_len; + + } else if (rx_vlan) { + struct vlan_dev_priv *vlan = vlan_dev_priv(rx_dev); + struct vlan_pcpu_stats *stats; + stats = this_cpu_ptr(vlan->vlan_pcpu_stats); + stats->rx_packets++; + stats->rx_bytes += eth_len; + } else { + rx_dev->stats.rx_packets++; + rx_dev->stats.rx_bytes += eth_len; + } + + rx_hw_stats = &rx_port->dev->stats; + rx_hw_stats->rx_bytes += eth_len; + rx_hw_stats->rx_packets++; + + frag_dma_addr = mvpp2_rxdesc_dma_addr_get(rx_port, rx_desc); + frag_phys_addr = mvpp2_rxdesc_cookie_get(rx_port, rx_desc); + + /* do we have room in the tx queue ? */ + bm_pool = &rx_port->priv->bm_pools[pool]; + if (!ff_can_send(tx_port, bm_pool)) { + /* just rearm descriptor and fake success */ + mvpp2_bm_pool_put(rx_port, pool, frag_dma_addr, frag_phys_addr); + return true; + } + + /* can we allocate a new fragment to replace the descriptor we + * are about to use ? */ + if (mvpp2_rx_refill(rx_port, bm_pool, pool)) { + /* just rearm descriptor and fake success */ + mvpp2_bm_pool_put(rx_port, pool, frag_dma_addr, frag_phys_addr); + return true; + } + + /* do we have a free tx desc ? */ + if (!ff_ensure_tx_desc(tx_port, bm_pool)) { + /* just rearm descriptor and fake success */ + mvpp2_bm_pool_put(rx_port, pool, frag_dma_addr, frag_phys_addr); + return true; + } + + if (ct && l4_is_tcp) { + /* don't try to track window anymore on this + * connection */ + ct->proto.tcp.no_window_track = 1; + } + + /* alter l3 & l4 content if needed (routing only) */ + if (l3_is_ipv4 && e) { + struct iphdr *iph = (struct iphdr *)l3_hdr; + + if (e->manip.alter) { + if (l4_is_tcp) { + struct tcphdr *tcph = (struct tcphdr *)l4_hdr; + tcph->source = e->manip.new_sport; + tcph->dest = e->manip.new_dport; + tcph->check = csum16_sub(tcph->check, + e->manip.l4_adjustment); + } else { + struct udphdr *udph = (struct udphdr *)l4_hdr; + udph->source = e->manip.new_sport; + udph->dest = e->manip.new_dport; + if (udph->check) { + u16 tcheck; + + tcheck = csum16_sub(udph->check, + e->manip.l4_adjustment); + udph->check = tcheck ? tcheck : 0xffff; + } + } + + iph->saddr = e->manip.new_sip; + iph->daddr = e->manip.new_dip; + } + + iph->ttl--; + iph->check = csum16_sub(iph->check, + e->manip.ip_adjustment); + + } else if (!l3_is_ipv4 && e6) { + struct ipv6hdr *ip6hdr = (struct ipv6hdr *)l3_hdr; + + if (e6->manip.alter) { + if (l4_is_tcp) { + struct tcphdr *tcph = (struct tcphdr *)l4_hdr; + tcph->source = e6->manip.new_sport; + tcph->dest = e6->manip.new_dport; + tcph->check = csum16_sub(tcph->check, + e6->manip.adjustment); + } else { + struct udphdr *udph = (struct udphdr *)l4_hdr; + udph->source = e6->manip.new_sport; + udph->dest = e6->manip.new_dport; + + if (udph->check) { + u16 tcheck; + + tcheck = csum16_sub(udph->check, + e6->manip.adjustment); + udph->check = tcheck ? tcheck : 0xffff; + } + } + + memcpy(ip6hdr->saddr.s6_addr32, e6->manip.new_sip, 16); + memcpy(ip6hdr->daddr.s6_addr32, e6->manip.new_dip, 16); + } + + ip6hdr->hop_limit--; + } + + /* packet is ready to xmit */ + switch (xmit_mode) { + case FF_XMIT_IPV4: + proto = ETH_P_IP; + break; + + case FF_XMIT_IPV6: + proto = ETH_P_IPV6; + break; + + case FF_XMIT_IPV6_IN_IPV4: + { + struct iphdr *tun_hdr; + /* prepend IPv4 */ + tun_hdr = (struct iphdr *)((u8 *)l3_hdr - sizeof (*tun_hdr)); + tun_hdr->ihl = 5; + tun_hdr->version = 4; + tun_hdr->tos = 0; + tun_hdr->tot_len = htons(l3_plen + sizeof (*tun_hdr)); + tun_hdr->id = 0; + tun_hdr->frag_off = 0; + tun_hdr->ttl = 64; + tun_hdr->protocol = IPPROTO_IPV6; + tun_hdr->saddr = ff.u.sit.src; + tun_hdr->daddr = tun_v4_dest; + + l3_hdr = (u8 *)tun_hdr; + l3_plen += sizeof (*tun_hdr); + + proto = ETH_P_IP; + break; + } + + case FF_XMIT_IPV4_IN_IPV6: + { + struct ipv6hdr *tun_6hdr; + + /* prepend IPv6 */ + tun_6hdr = (struct ipv6hdr *)((u8 *)l3_hdr - sizeof (*tun_6hdr)); + tun_6hdr->version = 6; + tun_6hdr->priority = 0; + memset(tun_6hdr->flow_lbl, 0, sizeof (tun_6hdr->flow_lbl)); + tun_6hdr->payload_len = htons(l3_plen); + tun_6hdr->nexthdr = IPPROTO_IPIP; + tun_6hdr->hop_limit = 64; + tun_6hdr->saddr = ff.u.map.src; + tun_6hdr->daddr = *tun_v6_pdest; + + l3_hdr = (u8 *)tun_6hdr; + l3_plen += sizeof (*tun_6hdr); + + proto = ETH_P_IPV6; + break; + } + } + + src_hwaddr = tx_port->dev->dev_addr; + if (tx_alt_hwaddr) + src_hwaddr = tx_alt_hwaddr; + + /* add ethernet header */ + if (tx_vlan) { + struct vlan_ethhdr *vhdr; + + vhdr = (struct vlan_ethhdr *)((u8 *)l3_hdr - VLAN_ETH_HLEN); + memcpy(vhdr->h_dest, dest_hw, 6); + memcpy(vhdr->h_source, src_hwaddr, 6); + vhdr->h_vlan_proto = htons(ETH_P_8021Q); + vhdr->h_vlan_TCI = htons(836); + vhdr->h_vlan_encapsulated_proto = htons(proto); + + eth = (struct ethhdr *)vhdr; + eth_len = l3_plen + VLAN_ETH_HLEN; + } else { + eth = (struct ethhdr *)((u8 *)l3_hdr - ETH_HLEN); + memcpy(eth->h_dest, dest_hw, 6); + memcpy(eth->h_source, src_hwaddr, 6); + eth->h_proto = htons(proto); + eth_len = l3_plen + ETH_HLEN; + } + + ff_send(tx_port, + frag_dma_addr, + frag_phys_addr, + (void *)eth - frag, + pool, + eth_len, + (proto == ETH_P_IP), + (xmit_mode == FF_XMIT_IPV4), + l4_is_tcp, + tx_vlan); + + if (is_bridge_dev(tx_dev)) { + struct net_bridge *br = netdev_priv(tx_dev); + struct pcpu_sw_netstats *stats; + stats = this_cpu_ptr(br->stats); + stats->tx_packets++; + stats->tx_bytes += eth_len; + } else if (tx_vlan) { + struct vlan_dev_priv *vlan = vlan_dev_priv(tx_dev); + struct vlan_pcpu_stats *stats; + stats = this_cpu_ptr(vlan->vlan_pcpu_stats); + stats->tx_packets++; + stats->tx_bytes += eth_len; + } else { + tx_dev->stats.tx_packets++; + tx_dev->stats.tx_bytes += eth_len; + } + + tx_hw_stats = &tx_port->dev->stats; + tx_hw_stats->tx_bytes += eth_len; + tx_hw_stats->tx_packets++; + + /* refresh conntrack */ + if (ct) { + if (l4_is_tcp) + timeout = HZ * 3600 * 24 * 5; + else + timeout = HZ * 180; + + if (ct->timeout - ff.jiffies < timeout - 10 * HZ) { + unsigned long newtime = ff.jiffies + timeout; + ct->timeout = newtime; + } + } + + return true; +} + +/* + * + */ +static bool ff_receive(struct mvpp2_port *port, + int pool, + struct mvpp2_rx_desc *rx_desc, + void *frag, + size_t offset, size_t dlen) +{ + int wan_idx = (FF_DEV_WAN_ID << 1) | FF_DEV_WAN_PORT_INDEX; + int sfplan_idx = (FF_DEV_SFPLAN_ID << 1) | FF_DEV_SFPLAN_PORT_INDEX; + int swlan_idx = (FF_DEV_SWLAN_ID << 1) | FF_DEV_SWLAN_PORT_INDEX; + unsigned int idx; + + if (!ff_enabled) + return false; + + idx = (port->priv->id << 1) | port->index; + + /* + * LAN => WAN + * [sfplan0 (untagged)] => [br0] => IPV4 => [ftth0.836] + */ + if (idx == sfplan_idx) { + return ff_forward(port, + sfplan.bridge_hwaddr, + pool, + ports_by_idx[wan_idx], + NULL, + NULL, + false, + ff.lan_dev_sfp, + ff.wan_dev, + 0, 836, + rx_desc, + frag, offset, dlen); + } + + /* + * LAN => WAN + * [swlan0 (untagged)] => [br0] => IPV4 => [ftth0.836] + */ + if (idx == swlan_idx) { + return ff_forward(port, + swlan.bridge_hwaddr, + pool, + ports_by_idx[wan_idx], + NULL, + NULL, + false, + ff.lan_dev_sw, + ff.wan_dev, + 0, 836, + rx_desc, + frag, offset, dlen); + } + + /* + * WAN => LAN + * [ffth0.836] => IPV4 => [br0] => [sfplan0/swlan0] + */ + if (idx == wan_idx) { + struct mvpp2_port *tx_ports[2]; + struct net_device *tx_dev; + const uint8_t *tx_alt_hwaddr; + + if (ff.lan_dev_sfp && sfplan.fbxbr_port) { + /* fbxbridge mode */ + tx_ports[0] = ports_by_idx[sfplan_idx]; + tx_ports[1] = NULL; + tx_dev = ff.lan_dev_sfp; + tx_alt_hwaddr = NULL; + + } else if (ff.lan_dev_sw && swlan.fbxbr_port) { + /* fbxbridge mode */ + tx_ports[0] = ports_by_idx[swlan_idx]; + tx_ports[1] = NULL; + tx_dev = ff.lan_dev_sw; + tx_alt_hwaddr = NULL; + + } else { + /* bridge mode */ + tx_ports[0] = ports_by_idx[sfplan_idx]; + if (tx_ports[0]) + tx_ports[1] = ports_by_idx[swlan_idx]; + else { + tx_ports[0] = ports_by_idx[swlan_idx]; + tx_ports[1] = NULL; + } + + tx_dev = ff.lan_dev_sfp; + tx_alt_hwaddr = sfplan.bridge_hwaddr; + if (!tx_dev) { + tx_dev = ff.lan_dev_sw; + tx_alt_hwaddr = swlan.bridge_hwaddr; + } + } + + return ff_forward(port, + NULL, + pool, + tx_ports[0], + tx_ports[1], + tx_alt_hwaddr, + true, + ff.wan_dev, + tx_dev, + 836, 0, + rx_desc, + frag, offset, dlen); + } + + return false; +} + +/* + * + */ +static unsigned int ff_get_opposite_ports(struct mvpp2_port *in_port, + struct mvpp2_port *out_ports[2]) +{ + int wan_idx = (FF_DEV_WAN_ID << 1) | FF_DEV_WAN_PORT_INDEX; + int sfplan_idx = (FF_DEV_SFPLAN_ID << 1) | FF_DEV_SFPLAN_PORT_INDEX; + int swlan_idx = (FF_DEV_SWLAN_ID << 1) | FF_DEV_SWLAN_PORT_INDEX; + unsigned int idx, count; + + idx = (in_port->priv->id << 1) | in_port->index; + count = 0; + + if (idx == sfplan_idx || idx == swlan_idx) { + if (ports_by_idx[wan_idx]) + out_ports[count++] = ports_by_idx[wan_idx]; + } else if (idx == wan_idx) { + if (ports_by_idx[sfplan_idx]) + out_ports[count++] = ports_by_idx[sfplan_idx]; + if (ports_by_idx[swlan_idx]) + out_ports[count++] = ports_by_idx[swlan_idx]; + } + + return count; +} + +/* + * + */ +static ssize_t ff_show_enabled(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%u\n", ff_enabled); +} + +static ssize_t ff_store_enabled(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + unsigned long val; + + if (kstrtoul(buf, 10, &val)) + return -EINVAL; + + if (ff_enabled == val) + return len; + + printk(KERN_NOTICE "ff: fastpath now %s\n", + val ? "enabled" : "disabled"); + ff_enabled = val; + return len; +} + +static struct device_attribute dev_attr_ff = { + .attr = { .name = "ff_enabled", .mode = (S_IRUGO | S_IWUSR) }, + .show = ff_show_enabled, + .store = ff_store_enabled, +}; + +/* + * + */ +static ssize_t ff_show_tun_dev(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%s\n", ff.tun_dev_name); +} + +static ssize_t ff_store_tun_dev(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + if (!len || buf[0] == '\n') { + ff.tun_dev_name[0] = 0; + spin_lock_bh(&ff_lock); + __ff_tun_release(); + spin_unlock_bh(&ff_lock); + printk(KERN_NOTICE "ff: tun dev unset\n"); + return len; + } + + spin_lock_bh(&ff_lock); + __ff_tun_release(); + strncpy(ff.tun_dev_name, buf, len); + strim(ff.tun_dev_name); + printk(KERN_NOTICE "ff: tun dev set to %s\n", ff.tun_dev_name); + __ff_tun_capture(); + spin_unlock_bh(&ff_lock); + return len; +} + +static struct device_attribute dev_attr_tun = { + .attr = { .name = "ff_tun_dev", .mode = (S_IRUGO | S_IWUSR) }, + .show = ff_show_tun_dev, + .store = ff_store_tun_dev, +}; + +static struct ff_dev swlan = { + .desc = "swlan", + .id = FF_DEV_SWLAN_ID, + .port_index = FF_DEV_SWLAN_PORT_INDEX, + .bridge_member = true, + .pvirt_dev = &ff.lan_dev_sw, +}; + +static struct ff_dev sfplan = { + .desc = "sfplan", + .id = FF_DEV_SFPLAN_ID, + .port_index = FF_DEV_SFPLAN_PORT_INDEX, + .bridge_member = true, + .pvirt_dev = &ff.lan_dev_sfp, +}; + +static struct ff_dev wan = { + .desc = "wan", + .id = FF_DEV_WAN_ID, + .port_index = FF_DEV_WAN_PORT_INDEX, + .vlan = 836, + .pvirt_dev = &ff.wan_dev, +}; + +static void ff_init(struct device *dev) +{ + static bool done; + + if (done) + return; + + device_create_file(dev, &dev_attr_ff); + device_create_file(dev, &dev_attr_tun); + + printk(KERN_DEBUG "ff_init\n"); + + list_add(&swlan.next, &ff_devs); + list_add(&sfplan.next, &ff_devs); + list_add(&wan.next, &ff_devs); + done = true; +} +#endif + + /* Parser configuration routines */ /* Update parser tcam and sram hw entries */ @@ -3819,7 +6102,6 @@ val |= MVPP2_BM_START_MASK; mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); - bm_pool->type = MVPP2_BM_FREE; bm_pool->size = size; bm_pool->pkt_size = 0; bm_pool->buf_num = 0; @@ -3872,11 +6154,17 @@ /* Free all buffers from the pool */ static void mvpp2_bm_bufs_free(struct device *dev, struct mvpp2 *priv, - struct mvpp2_bm_pool *bm_pool) + struct mvpp2_bm_pool *bm_pool, int buf_num) { int i; - for (i = 0; i < bm_pool->buf_num; i++) { + if (buf_num > bm_pool->buf_num) { + WARN(1, "Pool does not have so many bufs pool(%d) bufs(%d)\n", + bm_pool->id, buf_num); + buf_num = bm_pool->buf_num; + } + + for (i = 0; i < buf_num; i++) { dma_addr_t buf_dma_addr; phys_addr_t buf_phys_addr; void *data; @@ -3898,16 +6186,39 @@ bm_pool->buf_num -= i; } +/* Check number of buffers in BM pool */ +static int mvpp2_check_hw_buf_num(struct mvpp2 *priv, struct mvpp2_bm_pool *bm_pool) +{ + int buf_num = 0; + + buf_num += mvpp2_read(priv, MVPP2_BM_POOL_PTRS_NUM_REG(bm_pool->id)) & + MVPP22_BM_POOL_PTRS_NUM_MASK; + buf_num += mvpp2_read(priv, MVPP2_BM_BPPI_PTRS_NUM_REG(bm_pool->id)) & + MVPP2_BM_BPPI_PTR_NUM_MASK; + + /* HW has one buffer ready which is not reflected in the counters */ + if (buf_num) + buf_num += 1; + + return buf_num; +} + /* Cleanup pool */ static int mvpp2_bm_pool_destroy(struct platform_device *pdev, struct mvpp2 *priv, struct mvpp2_bm_pool *bm_pool) { + int buf_num; u32 val; - mvpp2_bm_bufs_free(&pdev->dev, priv, bm_pool); - if (bm_pool->buf_num) { - WARN(1, "cannot free all buffers in pool %d\n", bm_pool->id); + buf_num = mvpp2_check_hw_buf_num(priv, bm_pool); + mvpp2_bm_bufs_free(&pdev->dev, priv, bm_pool, buf_num); + + /* Check buffer counters after free */ + buf_num = mvpp2_check_hw_buf_num(priv, bm_pool); + if (buf_num) { + WARN(1, "cannot free all buffers in pool %d, buf_num left %d\n", + bm_pool->id, bm_pool->buf_num); return 0; } @@ -3969,6 +6280,21 @@ return 0; } +static void mvpp2_setup_bm_pool(void) +{ + /* Short pool */ + mvpp2_pools[MVPP2_BM_SHORT].buf_num = MVPP2_BM_SHORT_BUF_NUM; + mvpp2_pools[MVPP2_BM_SHORT].pkt_size = MVPP2_BM_SHORT_PKT_SIZE; + + /* Long pool */ + mvpp2_pools[MVPP2_BM_LONG].buf_num = MVPP2_BM_LONG_BUF_NUM; + mvpp2_pools[MVPP2_BM_LONG].pkt_size = MVPP2_BM_LONG_PKT_SIZE; + + /* Jumbo pool */ + mvpp2_pools[MVPP2_BM_JUMBO].buf_num = MVPP2_BM_JUMBO_BUF_NUM; + mvpp2_pools[MVPP2_BM_JUMBO].pkt_size = MVPP2_BM_JUMBO_PKT_SIZE; +} + /* Attach long pool to rxq */ static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port, int lrxq, int long_pool) @@ -4056,7 +6382,7 @@ << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) & MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK; - mvpp2_percpu_write(port->priv, cpu, + mvpp2_percpu_write_relaxed(port->priv, cpu, MVPP22_BM_ADDR_HIGH_RLS_REG, val); } @@ -4065,9 +6391,9 @@ * descriptor. Instead of storing the virtual address, we * store the physical address */ - mvpp2_percpu_write(port->priv, cpu, + mvpp2_percpu_write_relaxed(port->priv, cpu, MVPP2_BM_VIRT_RLS_REG, buf_phys_addr); - mvpp2_percpu_write(port->priv, cpu, + mvpp2_percpu_write_relaxed(port->priv, cpu, MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr); put_cpu(); @@ -4107,13 +6433,11 @@ bm_pool->buf_num += i; netdev_dbg(port->dev, - "%s pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n", - bm_pool->type == MVPP2_BM_SWF_SHORT ? "short" : " long", + "pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n", bm_pool->id, bm_pool->pkt_size, buf_size, total_size); netdev_dbg(port->dev, - "%s pool %d: %d of %d buffers added\n", - bm_pool->type == MVPP2_BM_SWF_SHORT ? "short" : " long", + "pool %d: %d of %d buffers added\n", bm_pool->id, i, buf_num); return i; } @@ -4122,25 +6446,20 @@ * pool pointer on success */ static struct mvpp2_bm_pool * -mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type, - int pkt_size) +mvpp2_bm_pool_use(struct mvpp2_port *port, unsigned pool, int pkt_size) { struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool]; int num; - if (new_pool->type != MVPP2_BM_FREE && new_pool->type != type) { - netdev_err(port->dev, "mixing pool types is forbidden\n"); + if (pool >= MVPP2_BM_POOLS_NUM) { + netdev_err(port->dev, "Invalid pool %d\n", pool); return NULL; } - if (new_pool->type == MVPP2_BM_FREE) - new_pool->type = type; - /* Allocate buffers in case BM pool is used as long pool, but packet * size doesn't match MTU or BM pool hasn't being used yet */ - if (((type == MVPP2_BM_SWF_LONG) && (pkt_size > new_pool->pkt_size)) || - (new_pool->pkt_size == 0)) { + if (new_pool->pkt_size == 0) { int pkts_num; /* Set default buffer number or free all the buffers in case @@ -4148,12 +6467,10 @@ */ pkts_num = new_pool->buf_num; if (pkts_num == 0) - pkts_num = type == MVPP2_BM_SWF_LONG ? - MVPP2_BM_LONG_BUF_NUM : - MVPP2_BM_SHORT_BUF_NUM; + pkts_num = mvpp2_pools[pool].buf_num; else mvpp2_bm_bufs_free(port->dev->dev.parent, - port->priv, new_pool); + port->priv, new_pool, pkts_num); new_pool->pkt_size = pkt_size; new_pool->frag_size = @@ -4179,16 +6496,28 @@ static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port) { int rxq; + enum mvpp2_bm_pool_log_num long_log_pool, short_log_pool; + + /* If port pkt_size is higher than 1518B: + * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool + * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool + */ + if (port->pkt_size > MVPP2_BM_LONG_PKT_SIZE) { + long_log_pool = MVPP2_BM_JUMBO; + short_log_pool = MVPP2_BM_LONG; + } else { + long_log_pool = MVPP2_BM_LONG; + short_log_pool = MVPP2_BM_SHORT; + } if (!port->pool_long) { port->pool_long = - mvpp2_bm_pool_use(port, MVPP2_BM_SWF_LONG_POOL(port->id), - MVPP2_BM_SWF_LONG, - port->pkt_size); + mvpp2_bm_pool_use(port, long_log_pool, + mvpp2_pools[long_log_pool].pkt_size); if (!port->pool_long) return -ENOMEM; - port->pool_long->port_map |= (1 << port->id); + port->pool_long->port_map |= BIT(port->id); for (rxq = 0; rxq < port->nrxqs; rxq++) mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id); @@ -4196,13 +6525,12 @@ if (!port->pool_short) { port->pool_short = - mvpp2_bm_pool_use(port, MVPP2_BM_SWF_SHORT_POOL, - MVPP2_BM_SWF_SHORT, - MVPP2_BM_SHORT_PKT_SIZE); + mvpp2_bm_pool_use(port, short_log_pool, + mvpp2_pools[long_log_pool].pkt_size); if (!port->pool_short) return -ENOMEM; - port->pool_short->port_map |= (1 << port->id); + port->pool_short->port_map |= BIT(port->id); for (rxq = 0; rxq < port->nrxqs; rxq++) mvpp2_rxq_short_pool_set(port, rxq, @@ -4215,30 +6543,49 @@ static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu) { struct mvpp2_port *port = netdev_priv(dev); - struct mvpp2_bm_pool *port_pool = port->pool_long; - int num, pkts_num = port_pool->buf_num; + enum mvpp2_bm_pool_log_num new_long_pool; int pkt_size = MVPP2_RX_PKT_SIZE(mtu); - /* Update BM pool with new buffer size */ - mvpp2_bm_bufs_free(dev->dev.parent, port->priv, port_pool); - if (port_pool->buf_num) { - WARN(1, "cannot free all buffers in pool %d\n", port_pool->id); - return -EIO; - } + /* If port MTU is higher than 1518B: + * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool + * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool + */ + if (pkt_size > MVPP2_BM_LONG_PKT_SIZE) + new_long_pool = MVPP2_BM_JUMBO; + else + new_long_pool = MVPP2_BM_LONG; - port_pool->pkt_size = pkt_size; - port_pool->frag_size = SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) + - MVPP2_SKB_SHINFO_SIZE; - num = mvpp2_bm_bufs_add(port, port_pool, pkts_num); - if (num != pkts_num) { - WARN(1, "pool %d: %d of %d allocated\n", - port_pool->id, num, pkts_num); - return -EIO; + if (new_long_pool != port->pool_long->id) { + /* Remove port from old short & long pool */ + port->pool_long = mvpp2_bm_pool_use(port, port->pool_long->id, + port->pool_long->pkt_size); + port->pool_long->port_map &= ~BIT(port->id); + port->pool_long = NULL; + + port->pool_short = mvpp2_bm_pool_use(port, port->pool_short->id, + port->pool_short->pkt_size); + port->pool_short->port_map &= ~BIT(port->id); + port->pool_short = NULL; + + port->pkt_size = pkt_size; + + /* Add port to new short & long pool */ + mvpp2_swf_bm_pool_init(port); + + /* Update L4 checksum when jumbo enable/disable on port */ + if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) { + dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); + dev->hw_features &= ~(NETIF_F_IP_CSUM | + NETIF_F_IPV6_CSUM); + } else { + dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; + dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; + } } - mvpp2_bm_pool_bufsize_set(port->priv, port_pool, - MVPP2_RX_BUF_SIZE(port_pool->pkt_size)); dev->mtu = mtu; + dev->wanted_features = dev->features; + netdev_update_features(dev); return 0; } @@ -4423,6 +6770,8 @@ mvpp22_gop_init_rgmii(port); break; case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: mvpp22_gop_init_sgmii(port); break; case PHY_INTERFACE_MODE_10GKR: @@ -4460,7 +6809,9 @@ u32 val; if (phy_interface_mode_is_rgmii(port->phy_interface) || - port->phy_interface == PHY_INTERFACE_MODE_SGMII) { + port->phy_interface == PHY_INTERFACE_MODE_SGMII || + port->phy_interface == PHY_INTERFACE_MODE_1000BASEX || + port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { /* Enable the GMAC link status irq for this port */ val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; @@ -4490,7 +6841,9 @@ } if (phy_interface_mode_is_rgmii(port->phy_interface) || - port->phy_interface == PHY_INTERFACE_MODE_SGMII) { + port->phy_interface == PHY_INTERFACE_MODE_SGMII || + port->phy_interface == PHY_INTERFACE_MODE_1000BASEX || + port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); @@ -4502,7 +6855,9 @@ u32 val; if (phy_interface_mode_is_rgmii(port->phy_interface) || - port->phy_interface == PHY_INTERFACE_MODE_SGMII) { + port->phy_interface == PHY_INTERFACE_MODE_SGMII || + port->phy_interface == PHY_INTERFACE_MODE_1000BASEX || + port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { val = readl(port->base + MVPP22_GMAC_INT_MASK); val |= MVPP22_GMAC_INT_MASK_LINK_STAT; writel(val, port->base + MVPP22_GMAC_INT_MASK); @@ -4527,8 +6882,12 @@ switch (port->phy_interface) { case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: mode = PHY_MODE_SGMII; break; + case PHY_INTERFACE_MODE_2500BASEX: + mode = PHY_MODE_HS_SGMII; + break; case PHY_INTERFACE_MODE_10GKR: mode = PHY_MODE_10GKR; break; @@ -4547,7 +6906,9 @@ { u32 val; - if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) { + if (port->phy_interface == PHY_INTERFACE_MODE_SGMII || + port->phy_interface == PHY_INTERFACE_MODE_1000BASEX || + port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { val = readl(port->base + MVPP22_GMAC_CTRL_4_REG); val |= MVPP22_CTRL4_SYNC_BYPASS_DIS | MVPP22_CTRL4_DP_CLK_SEL | MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; @@ -4562,17 +6923,61 @@ writel(val, port->base + MVPP22_GMAC_CTRL_4_REG); } - /* The port is connected to a copper PHY */ val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); + if (port->phy_interface == PHY_INTERFACE_MODE_1000BASEX || + port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) + /* + * The port is connected to an SFP cage of a direct + * backplane connection. + */ + val |= MVPP2_GMAC_PORT_TYPE_MASK; + else + /* The port is connected to a copper PHY */ val &= ~MVPP2_GMAC_PORT_TYPE_MASK; writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); - val |= MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS | - MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG | - MVPP2_GMAC_AN_DUPLEX_EN; - if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) + + /* + * clear all fields we may want to explicitely set below + */ + val &= ~(MVPP2_GMAC_IN_BAND_AUTONEG | + MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS | + MVPP2_GMAC_AN_SPEED_EN | + MVPP2_GMAC_CONFIG_MII_SPEED | + MVPP2_GMAC_CONFIG_GMII_SPEED | + MVPP2_GMAC_FC_ADV_EN | + MVPP2_GMAC_FLOW_CTRL_AUTONEG | + MVPP2_GMAC_CONFIG_FULL_DUPLEX | + MVPP2_GMAC_AN_DUPLEX_EN); + + if (port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) { + /* + * enable autonegation, advertise disabled flow + * control, note that hardware does not support half + * duplex + */ val |= MVPP2_GMAC_IN_BAND_AUTONEG; + val |= MVPP2_GMAC_FLOW_CTRL_AUTONEG; + val |= MVPP2_GMAC_CONFIG_GMII_SPEED; + val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX; + + } else if (port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { + /* + * 2500BaseX sets both GMII_SPEED and MII_SPEED in the + * LSP. + */ + val |= MVPP2_GMAC_CONFIG_GMII_SPEED; + val |= MVPP2_GMAC_CONFIG_MII_SPEED; + val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX; + } else { + /* + * otherwise, allow normal negotiation of speed and + * duplex + */ + val |= MVPP2_GMAC_AN_SPEED_EN; + val |= MVPP2_GMAC_AN_DUPLEX_EN; + } writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); } @@ -4594,7 +6999,11 @@ /* Configure the PCS and in-band AN */ val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) { - val |= MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK; + val |= MVPP2_GMAC_INBAND_AN_SGMII_MASK | + MVPP2_GMAC_PCS_ENABLE_MASK; + } else if (port->phy_interface == PHY_INTERFACE_MODE_1000BASEX || + port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { + val |= MVPP2_GMAC_PCS_ENABLE_MASK; } else if (phy_interface_mode_is_rgmii(port->phy_interface)) { val &= ~MVPP2_GMAC_PCS_ENABLE_MASK; } @@ -4655,7 +7064,9 @@ mvpp22_port_mii_set(port); if (phy_interface_mode_is_rgmii(port->phy_interface) || - port->phy_interface == PHY_INTERFACE_MODE_SGMII) + port->phy_interface == PHY_INTERFACE_MODE_SGMII || + port->phy_interface == PHY_INTERFACE_MODE_1000BASEX || + port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) mvpp2_port_mii_gmac_configure(port); else if (port->phy_interface == PHY_INTERFACE_MODE_10GKR) mvpp2_port_mii_xlg_configure(port); @@ -4721,18 +7132,21 @@ } /* Configure loopback port */ -static void mvpp2_port_loopback_set(struct mvpp2_port *port) +static void mvpp2_port_loopback_set(struct mvpp2_port *port, + const struct phylink_link_state *state) { u32 val; val = readl(port->base + MVPP2_GMAC_CTRL_1_REG); - if (port->speed == 1000) + if (state->speed == 1000) val |= MVPP2_GMAC_GMII_LB_EN_MASK; else val &= ~MVPP2_GMAC_GMII_LB_EN_MASK; - if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) + if (port->phy_interface == PHY_INTERFACE_MODE_SGMII || + port->phy_interface == PHY_INTERFACE_MODE_1000BASEX || + port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) val |= MVPP2_GMAC_PCS_LB_EN_MASK; else val &= ~MVPP2_GMAC_PCS_LB_EN_MASK; @@ -4740,9 +7154,309 @@ writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); } +enum mvpp2_ethtool_type { + MVPP2_MIB = 0, + MVPP2_OVERRUN_DROP, + MVPP2_CLS_DROP, + MVPP2_RXQ_STATS, + MVPP2_TXQ_STATS, +}; + +struct mvpp2_ethtool_counter { + enum mvpp2_ethtool_type type; + unsigned int offset; + const char string[ETH_GSTRING_LEN]; + bool reg_is_64b; + unsigned int queue; +}; + +static u64 mvpp2_read_count(struct mvpp2_port *port, + const struct mvpp2_ethtool_counter *counter) +{ + u64 val = 0; + + switch (counter->type) { + case MVPP2_MIB: + val = readl(port->stats_base + counter->offset); + if (counter->reg_is_64b) + val += (u64)readl(port->stats_base + counter->offset + 4) << 32; + break; + + case MVPP2_OVERRUN_DROP: + val = mvpp2_read(port->priv, MVPP22_PCTR_OVERRUN_REG(port->id)); + break; + + case MVPP2_CLS_DROP: + val = mvpp2_read(port->priv, MVPP22_PCTR_CLS_DROPPED_REG(port->id)); + break; + + case MVPP2_RXQ_STATS: + { + int cpu = get_cpu(); + + mvpp2_percpu_write(port->priv, + cpu, + MVPP22_PCTR_CTR_IDX_REG, + port->first_rxq + counter->queue); + val = mvpp2_percpu_read(port->priv, cpu, counter->offset); + put_cpu(); + break; + } + + case MVPP2_TXQ_STATS: + { + int cpu = get_cpu(); + + mvpp2_percpu_write(port->priv, + cpu, + MVPP22_PCTR_CTR_IDX_REG, + port->txqs[counter->queue]->id); + val = mvpp2_percpu_read(port->priv, cpu, counter->offset); + put_cpu(); + break; + } + } + + return val; +} + +/* Due to the fact that software statistics and hardware statistics are, by + * design, incremented at different moments in the chain of packet processing, + * it is very likely that incoming packets could have been dropped after being + * counted by hardware but before reaching software statistics (most probably + * multicast packets), and in the oppposite way, during transmission, FCS bytes + * are added in between as well as TSO skb will be split and header bytes added. + * Hence, statistics gathered from userspace with ifconfig (software) and + * ethtool (hardware) cannot be compared. + */ +static const struct mvpp2_ethtool_counter mvpp2_ethtool_regs[] = { + { MVPP2_MIB, MVPP2_MIB_GOOD_OCTETS_RCVD, "good_octets_received", true }, + { MVPP2_MIB, MVPP2_MIB_BAD_OCTETS_RCVD, "bad_octets_received" }, + { MVPP2_MIB, MVPP2_MIB_CRC_ERRORS_SENT, "crc_errors_sent" }, + { MVPP2_MIB, MVPP2_MIB_UNICAST_FRAMES_RCVD, "unicast_frames_received" }, + { MVPP2_MIB, MVPP2_MIB_BROADCAST_FRAMES_RCVD, "broadcast_frames_received" }, + { MVPP2_MIB, MVPP2_MIB_MULTICAST_FRAMES_RCVD, "multicast_frames_received" }, + { MVPP2_MIB, MVPP2_MIB_FRAMES_64_OCTETS, "frames_64_octets" }, + { MVPP2_MIB, MVPP2_MIB_FRAMES_65_TO_127_OCTETS, "frames_65_to_127_octet" }, + { MVPP2_MIB, MVPP2_MIB_FRAMES_128_TO_255_OCTETS, "frames_128_to_255_octet" }, + { MVPP2_MIB, MVPP2_MIB_FRAMES_256_TO_511_OCTETS, "frames_256_to_511_octet" }, + { MVPP2_MIB, MVPP2_MIB_FRAMES_512_TO_1023_OCTETS, "frames_512_to_1023_octet" }, + { MVPP2_MIB, MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS, "frames_1024_to_max_octet" }, + { MVPP2_MIB, MVPP2_MIB_GOOD_OCTETS_SENT, "good_octets_sent", true }, + { MVPP2_MIB, MVPP2_MIB_UNICAST_FRAMES_SENT, "unicast_frames_sent" }, + { MVPP2_MIB, MVPP2_MIB_MULTICAST_FRAMES_SENT, "multicast_frames_sent" }, + { MVPP2_MIB, MVPP2_MIB_BROADCAST_FRAMES_SENT, "broadcast_frames_sent" }, + { MVPP2_MIB, MVPP2_MIB_FC_SENT, "fc_sent" }, + { MVPP2_MIB, MVPP2_MIB_FC_RCVD, "fc_received" }, + { MVPP2_MIB, MVPP2_MIB_RX_FIFO_OVERRUN, "rx_fifo_overrun" }, + { MVPP2_MIB, MVPP2_MIB_UNDERSIZE_RCVD, "undersize_received" }, + { MVPP2_MIB, MVPP2_MIB_FRAGMENTS_RCVD, "fragments_received" }, + { MVPP2_MIB, MVPP2_MIB_OVERSIZE_RCVD, "oversize_received" }, + { MVPP2_MIB, MVPP2_MIB_JABBER_RCVD, "jabber_received" }, + { MVPP2_MIB, MVPP2_MIB_MAC_RCV_ERROR, "mac_receive_error" }, + { MVPP2_MIB, MVPP2_MIB_BAD_CRC_EVENT, "bad_crc_event" }, + { MVPP2_MIB, MVPP2_MIB_COLLISION, "collision" }, + { MVPP2_MIB, MVPP2_MIB_LATE_COLLISION, "late_collision" }, + + { MVPP2_OVERRUN_DROP, 0, "overrun_drop_pkts" }, + { MVPP2_CLS_DROP, 0, "classifier_drop_pkts" }, + + { MVPP2_RXQ_STATS, MVPP22_PCTR_RX_ENQUEUE_REG, "rxq0_desc_enqueue", false, 0 }, + { MVPP2_RXQ_STATS, MVPP22_PCTR_RX_FULL_DROP_REG, "rxq0_full_drop", false, 0 }, + { MVPP2_RXQ_STATS, MVPP22_PCTR_RX_EARLY_DROP_REG, "rxq0_early_drop", false, 0 }, + { MVPP2_RXQ_STATS, MVPP22_PCTR_RX_BM_DROP_REG, "rxq0_bm_drop", false, 0 }, + { MVPP2_RXQ_STATS, MVPP22_PCTR_RX_ENQUEUE_REG, "rxq1_desc_enqueue", false, 1 }, + { MVPP2_RXQ_STATS, MVPP22_PCTR_RX_FULL_DROP_REG, "rxq1_full_drop", false, 1 }, + { MVPP2_RXQ_STATS, MVPP22_PCTR_RX_EARLY_DROP_REG, "rxq1_early_drop", false, 1 }, + { MVPP2_RXQ_STATS, MVPP22_PCTR_RX_BM_DROP_REG, "rxq1_bm_drop", false, 1 }, + { MVPP2_RXQ_STATS, MVPP22_PCTR_RX_ENQUEUE_REG, "rxq2_desc_enqueue", false, 2 }, + { MVPP2_RXQ_STATS, MVPP22_PCTR_RX_FULL_DROP_REG, "rxq2_full_drop", false, 2 }, + { MVPP2_RXQ_STATS, MVPP22_PCTR_RX_EARLY_DROP_REG, "rxq2_early_drop", false, 2 }, + { MVPP2_RXQ_STATS, MVPP22_PCTR_RX_BM_DROP_REG, "rxq2_bm_drop", false, 2 }, + { MVPP2_RXQ_STATS, MVPP22_PCTR_RX_ENQUEUE_REG, "rxq3_desc_enqueue", false, 3 }, + { MVPP2_RXQ_STATS, MVPP22_PCTR_RX_FULL_DROP_REG, "rxq3_full_drop", false, 3 }, + { MVPP2_RXQ_STATS, MVPP22_PCTR_RX_EARLY_DROP_REG, "rxq3_early_drop", false, 3 }, + { MVPP2_RXQ_STATS, MVPP22_PCTR_RX_BM_DROP_REG, "rxq3_bm_drop", false, 3 }, + + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_ENQUEUE_REG, "txq0_desc_enqueue", false, 0 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_ENQUEUE_DESC_DDR_REG, "txq0_descs_ddr", false, 0 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_ENQUEUE_BUF_DDR_REG, "txq0_bufs_ddr", false, 0 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_ENQUEUE_HWFWD_REG, "txq0_desc_hwfwd", false, 0 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_DEQUEUE_REG, "txq0_desc_dequeue", false, 0 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_FULL_DROP_REG, "txq0_full_drop", false, 0 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_EARLY_DROP_REG, "txq0_early_drop", false, 0 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_BM_DROP_REG, "txq0_bm_drop", false, 0 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_BM_MC_DROP_REG, "txq0_bm_mc_drop", false, 0 }, + + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_ENQUEUE_REG, "txq1_desc_enqueue", false, 1 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_ENQUEUE_DESC_DDR_REG, "txq1_descs_ddr", false, 1 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_ENQUEUE_BUF_DDR_REG, "txq1_bufs_ddr", false, 1 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_ENQUEUE_HWFWD_REG, "txq1_desc_hwfwd", false, 1 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_DEQUEUE_REG, "txq1_desc_dequeue", false, 1 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_FULL_DROP_REG, "txq1_full_drop", false, 1 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_EARLY_DROP_REG, "txq1_early_drop", false, 1 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_BM_DROP_REG, "txq1_bm_drop", false, 1 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_BM_MC_DROP_REG, "txq1_bm_mc_drop", false, 1 }, + + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_ENQUEUE_REG, "txq2_desc_enqueue", false, 2 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_ENQUEUE_DESC_DDR_REG, "txq2_descs_ddr", false, 2 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_ENQUEUE_BUF_DDR_REG, "txq2_bufs_ddr", false, 2 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_ENQUEUE_HWFWD_REG, "txq2_desc_hwfwd", false, 2 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_DEQUEUE_REG, "txq2_desc_dequeue", false, 2 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_FULL_DROP_REG, "txq2_full_drop", false, 2 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_EARLY_DROP_REG, "txq2_early_drop", false, 2 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_BM_DROP_REG, "txq2_bm_drop", false, 2 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_BM_MC_DROP_REG, "txq2_bm_mc_drop", false, 2 }, + + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_ENQUEUE_REG, "txq3_desc_enqueue", false, 3 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_ENQUEUE_DESC_DDR_REG, "txq3_descs_ddr", false, 3 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_ENQUEUE_BUF_DDR_REG, "txq3_bufs_ddr", false, 3 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_ENQUEUE_HWFWD_REG, "txq3_desc_hwfwd", false, 3 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_DEQUEUE_REG, "txq3_desc_dequeue", false, 3 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_FULL_DROP_REG, "txq3_full_drop", false, 3 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_EARLY_DROP_REG, "txq3_early_drop", false, 3 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_BM_DROP_REG, "txq3_bm_drop", false, 3 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_BM_MC_DROP_REG, "txq3_bm_mc_drop", false, 3 }, + + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_ENQUEUE_REG, "txq4_desc_enqueue", false, 4 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_ENQUEUE_DESC_DDR_REG, "txq4_descs_ddr", false, 4 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_ENQUEUE_BUF_DDR_REG, "txq4_bufs_ddr", false, 4 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_ENQUEUE_HWFWD_REG, "txq4_desc_hwfwd", false, 4 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_DEQUEUE_REG, "txq4_desc_dequeue", false, 4 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_FULL_DROP_REG, "txq4_full_drop", false, 4 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_EARLY_DROP_REG, "txq4_early_drop", false, 4 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_BM_DROP_REG, "txq4_bm_drop", false, 4 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_BM_MC_DROP_REG, "txq4_bm_mc_drop", false, 4 }, + + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_ENQUEUE_REG, "txq5_desc_enqueue", false, 5 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_ENQUEUE_DESC_DDR_REG, "txq5_descs_ddr", false, 5 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_ENQUEUE_BUF_DDR_REG, "txq5_bufs_ddr", false, 5 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_ENQUEUE_HWFWD_REG, "txq5_desc_hwfwd", false, 5 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_DEQUEUE_REG, "txq5_desc_dequeue", false, 5 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_FULL_DROP_REG, "txq5_full_drop", false, 5 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_EARLY_DROP_REG, "txq5_early_drop", false, 5 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_BM_DROP_REG, "txq5_bm_drop", false, 5 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_BM_MC_DROP_REG, "txq5_bm_mc_drop", false, 5 }, + + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_ENQUEUE_REG, "txq6_desc_enqueue", false, 6 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_ENQUEUE_DESC_DDR_REG, "txq6_descs_ddr", false, 6 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_ENQUEUE_BUF_DDR_REG, "txq6_bufs_ddr", false, 6 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_ENQUEUE_HWFWD_REG, "txq6_desc_hwfwd", false, 6 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_DEQUEUE_REG, "txq6_desc_dequeue", false, 6 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_FULL_DROP_REG, "txq6_full_drop", false, 6 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_EARLY_DROP_REG, "txq6_early_drop", false, 6 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_BM_DROP_REG, "txq6_bm_drop", false, 6 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_BM_MC_DROP_REG, "txq6_bm_mc_drop", false, 6 }, + + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_ENQUEUE_REG, "txq7_desc_enqueue", false, 7 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_ENQUEUE_DESC_DDR_REG, "txq7_descs_ddr", false, 7 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_ENQUEUE_BUF_DDR_REG, "txq7_bufs_ddr", false, 7 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_ENQUEUE_HWFWD_REG, "txq7_desc_hwfwd", false, 7 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_DEQUEUE_REG, "txq7_desc_dequeue", false, 7 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_FULL_DROP_REG, "txq7_full_drop", false, 7 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_EARLY_DROP_REG, "txq7_early_drop", false, 7 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_BM_DROP_REG, "txq7_bm_drop", false, 7 }, + { MVPP2_TXQ_STATS, MVPP22_PCTR_TX_BM_MC_DROP_REG, "txq7_bm_mc_drop", false, 7 }, +}; + +struct ethtool_priv_flags_strings { + const char string[ETH_GSTRING_LEN]; +}; + +static const struct ethtool_priv_flags_strings mvpp2_priv_flags_strings[] = { + { .string = "en-fbx-10g1g-switch" }, + { .string = "en-fbx-10g" }, + { .string = "en-fbx-1g" }, + { .string = "st-fbx-10g" }, + { .string = "st-fbx-1g" }, + { .string = "st-sync-ok", }, + { .string = "clear-mib", }, +}; + +static void mvpp2_ethtool_get_strings(struct net_device *netdev, u32 sset, + u8 *data) +{ + if (sset == ETH_SS_STATS) { + int i; + + for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++) + memcpy(data + i * ETH_GSTRING_LEN, + &mvpp2_ethtool_regs[i].string, ETH_GSTRING_LEN); + } + if (sset == ETH_SS_PRIV_FLAGS) + memcpy(data, mvpp2_priv_flags_strings, + sizeof (mvpp2_priv_flags_strings)); +} + +static void mvpp2_gather_hw_statistics(struct work_struct *work) +{ + struct delayed_work *del_work = to_delayed_work(work); + struct mvpp2_port *port = container_of(del_work, struct mvpp2_port, + stats_work); + u64 *pstats; + int i; + + if (port->pending_10g_reset && !netif_carrier_ok(port->dev)) { + mvpp2_port_disable(port); + phy_power_off(port->comphy); + msleep(10); + mvpp22_comphy_init(port); + mvpp22_gop_init(port); + mvpp2_port_enable(port); + } + port->pending_10g_reset = false; + + mutex_lock(&port->gather_stats_lock); + + pstats = port->ethtool_stats; + for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++) + *pstats++ += mvpp2_read_count(port, &mvpp2_ethtool_regs[i]); + + /* No need to read again the counters right after this function if it + * was called asynchronously by the user (ie. use of ethtool). + */ + cancel_delayed_work(&port->stats_work); + queue_delayed_work(port->priv->stats_queue, &port->stats_work, + MVPP2_MIB_COUNTERS_STATS_DELAY); + + mutex_unlock(&port->gather_stats_lock); +} + +static void mvpp2_ethtool_get_stats(struct net_device *dev, + struct ethtool_stats *stats, u64 *data) +{ + struct mvpp2_port *port = netdev_priv(dev); + + /* Update statistics for the given port, then take the lock to avoid + * concurrent accesses on the ethtool_stats structure during its copy. + */ + mvpp2_gather_hw_statistics(&port->stats_work.work); + + mutex_lock(&port->gather_stats_lock); + memcpy(data, port->ethtool_stats, + sizeof(u64) * ARRAY_SIZE(mvpp2_ethtool_regs)); + mutex_unlock(&port->gather_stats_lock); +} + +static int mvpp2_ethtool_get_sset_count(struct net_device *dev, int sset) +{ + if (sset == ETH_SS_STATS) + return ARRAY_SIZE(mvpp2_ethtool_regs); + + if (sset == ETH_SS_PRIV_FLAGS) + return ARRAY_SIZE(mvpp2_priv_flags_strings); + + return -EOPNOTSUPP; +} + static void mvpp2_port_reset(struct mvpp2_port *port) { u32 val; + unsigned int i; + + /* Read the GOP statistics to reset the hardware counters */ + for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++) + mvpp2_read_count(port, &mvpp2_ethtool_regs[i]); val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) & ~MVPP2_GMAC_PORT_RESET_MASK; @@ -4783,10 +7497,6 @@ int tx_port_num, val, queue, lrxq; if (port->priv->hw_version == MVPP21) { - /* Configure port to loopback if needed */ - if (port->flags & MVPP2_F_LOOPBACK) - mvpp2_port_loopback_set(port); - /* Update TX FIFO MIN Threshold */ val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK; @@ -4801,6 +7511,17 @@ tx_port_num); mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0); + /* setup fixed prio queue mask, rest are WRR */ + mvpp2_write(port->priv, MVPP2_TXP_SCHED_FIXED_PRIO_REG, + MVPP2_TX_FIXED_PRIO_QUEUES); + + /* setup non zero WRR value for all ports (otherwise WRR seems + * biased) */ + for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) + mvpp2_write(port->priv, + MVPP2_TXQ_SCHED_BCOUNT_CFG_REG(queue), + 64); + /* Close bandwidth for all queues */ for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) mvpp2_write(port->priv, @@ -5012,15 +7733,16 @@ static int mvpp2_aggr_desc_num_check(struct mvpp2 *priv, struct mvpp2_tx_queue *aggr_txq, int num) { - if ((aggr_txq->count + num) > aggr_txq->size) { + if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) { /* Update number of occupied aggregated Tx descriptors */ int cpu = smp_processor_id(); - u32 val = mvpp2_read(priv, MVPP2_AGGR_TXQ_STATUS_REG(cpu)); + u32 val = mvpp2_read_relaxed(priv, + MVPP2_AGGR_TXQ_STATUS_REG(cpu)); aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK; } - if ((aggr_txq->count + num) > aggr_txq->size) + if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) return -ENOMEM; return 0; @@ -5039,9 +7761,9 @@ int cpu = smp_processor_id(); val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num; - mvpp2_percpu_write(priv, cpu, MVPP2_TXQ_RSVD_REQ_REG, val); + mvpp2_percpu_write_relaxed(priv, cpu, MVPP2_TXQ_RSVD_REQ_REG, val); - val = mvpp2_percpu_read(priv, cpu, MVPP2_TXQ_RSVD_RSLT_REG); + val = mvpp2_percpu_read_relaxed(priv, cpu, MVPP2_TXQ_RSVD_RSLT_REG); return val & MVPP2_TXQ_RSVD_RSLT_MASK; } @@ -5073,18 +7795,30 @@ desc_count += txq_pcpu_aux->reserved_num; } +#ifdef CONFIG_MVPP2_FBX_FF + if (txq->log_id == MVPP2_FF_TXQ_ID) { + if (desc_count >= txq->size) + return -ENOMEM; + + req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num); + if (req > txq->size - desc_count) + req = txq->size - desc_count; + } else +#endif + { req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num); desc_count += req; - if (desc_count > (txq->size - (num_present_cpus() * MVPP2_CPU_DESC_CHUNK))) return -ENOMEM; + } txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(priv, txq, req); /* OK, the descriptor cound has been updated: check again. */ if (txq_pcpu->reserved_num < num) return -ENOMEM; + return 0; } @@ -5146,7 +7880,7 @@ u32 val; /* Reading status reg resets transmitted descriptor counter */ - val = mvpp2_percpu_read(port->priv, smp_processor_id(), + val = mvpp2_percpu_read_relaxed(port->priv, smp_processor_id(), MVPP2_TXQ_SENT_REG(txq->id)); return (val & MVPP2_TRANSMITTED_COUNT_MASK) >> @@ -5316,6 +8050,17 @@ struct mvpp2_txq_pcpu_buf *tx_buf = txq_pcpu->buffs + txq_pcpu->txq_get_index; +#ifdef CONFIG_MVPP2_FBX_FF + if (tx_buf->is_rx_buf) { + mvpp2_bm_pool_put(port, + tx_buf->pool, + tx_buf->bm_dma, + tx_buf->bm_phys); + mvpp2_txq_inc_get(txq_pcpu); + continue; + } +#endif + if (!IS_TSO_HEADER(txq_pcpu, tx_buf->dma)) dma_unmap_single(port->dev->dev.parent, tx_buf->dma, tx_buf->size, DMA_TO_DEVICE); @@ -5351,6 +8096,9 @@ if (txq_pcpu->cpu != smp_processor_id()) netdev_err(port->dev, "wrong cpu on the end of Tx processing\n"); +#ifdef CONFIG_MVPP2_FBX_FF + WARN_ON(txq->log_id == MVPP2_FF_TXQ_ID); +#endif tx_done = mvpp2_txq_sent_desc_proc(port, txq); if (!tx_done) @@ -5360,7 +8108,7 @@ txq_pcpu->count -= tx_done; if (netif_tx_queue_stopped(nq)) - if (txq_pcpu->size - txq_pcpu->count >= MAX_SKB_FRAGS + 1) + if (txq_pcpu->count <= txq_pcpu->wake_threshold) netif_tx_wake_queue(nq); } @@ -5404,7 +8152,7 @@ if (!aggr_txq->descs) return -ENOMEM; - aggr_txq->last_desc = aggr_txq->size - 1; + aggr_txq->last_desc = MVPP2_AGGR_TXQ_SIZE - 1; /* Aggr TXQ no reset WA */ aggr_txq->next_desc_to_proc = mvpp2_read(priv, @@ -5602,6 +8350,10 @@ txq_pcpu->reserved_num = 0; txq_pcpu->txq_put_index = 0; txq_pcpu->txq_get_index = 0; + txq_pcpu->tso_headers = NULL; + + txq_pcpu->stop_threshold = txq->size - MVPP2_MAX_SKB_DESCS; + txq_pcpu->wake_threshold = txq_pcpu->stop_threshold - 100; txq_pcpu->tso_headers = dma_alloc_coherent(port->dev->dev.parent, @@ -5626,10 +8378,13 @@ txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); kfree(txq_pcpu->buffs); + if (txq_pcpu->tso_headers) dma_free_coherent(port->dev->dev.parent, txq_pcpu->size * TSO_HEADER_SIZE, txq_pcpu->tso_headers, txq_pcpu->tso_headers_dma); + + txq_pcpu->tso_headers = NULL; } if (txq->descs) @@ -5814,7 +8569,9 @@ link = true; } } else if (phy_interface_mode_is_rgmii(port->phy_interface) || - port->phy_interface == PHY_INTERFACE_MODE_SGMII) { + port->phy_interface == PHY_INTERFACE_MODE_SGMII || + port->phy_interface == PHY_INTERFACE_MODE_1000BASEX || + port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) { val = readl(port->base + MVPP22_GMAC_INT_STAT); if (val & MVPP22_GMAC_INT_STAT_LINK) { event = true; @@ -5835,12 +8592,21 @@ netif_carrier_on(dev); netif_tx_wake_all_queues(dev); } else { + bool was_up = netif_carrier_ok(dev); + netif_tx_stop_all_queues(dev); netif_carrier_off(dev); mvpp2_ingress_disable(port); mvpp2_egress_disable(port); mvpp2_interrupts_disable(port); + + if (was_up && + port->gop_id == 0 && + port->phy_interface == PHY_INTERFACE_MODE_10GKR) { + // schedule reset + port->pending_10g_reset = true; + } } handled: @@ -5848,111 +8614,6 @@ return IRQ_HANDLED; } -static void mvpp2_gmac_set_autoneg(struct mvpp2_port *port, - struct phy_device *phydev) -{ - u32 val; - - if (port->phy_interface != PHY_INTERFACE_MODE_RGMII && - port->phy_interface != PHY_INTERFACE_MODE_RGMII_ID && - port->phy_interface != PHY_INTERFACE_MODE_RGMII_RXID && - port->phy_interface != PHY_INTERFACE_MODE_RGMII_TXID && - port->phy_interface != PHY_INTERFACE_MODE_SGMII) - return; - - val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); - val &= ~(MVPP2_GMAC_CONFIG_MII_SPEED | - MVPP2_GMAC_CONFIG_GMII_SPEED | - MVPP2_GMAC_CONFIG_FULL_DUPLEX | - MVPP2_GMAC_AN_SPEED_EN | - MVPP2_GMAC_AN_DUPLEX_EN); - - if (phydev->duplex) - val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX; - - if (phydev->speed == SPEED_1000) - val |= MVPP2_GMAC_CONFIG_GMII_SPEED; - else if (phydev->speed == SPEED_100) - val |= MVPP2_GMAC_CONFIG_MII_SPEED; - - writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); -} - -/* Adjust link */ -static void mvpp2_link_event(struct net_device *dev) -{ - struct mvpp2_port *port = netdev_priv(dev); - struct phy_device *phydev = dev->phydev; - bool link_reconfigured = false; - u32 val; - - if (phydev->link) { - if (port->phy_interface != phydev->interface && port->comphy) { - /* disable current port for reconfiguration */ - mvpp2_interrupts_disable(port); - netif_carrier_off(port->dev); - mvpp2_port_disable(port); - phy_power_off(port->comphy); - - /* comphy reconfiguration */ - port->phy_interface = phydev->interface; - mvpp22_comphy_init(port); - - /* gop/mac reconfiguration */ - mvpp22_gop_init(port); - mvpp2_port_mii_set(port); - - link_reconfigured = true; - } - - if ((port->speed != phydev->speed) || - (port->duplex != phydev->duplex)) { - mvpp2_gmac_set_autoneg(port, phydev); - - port->duplex = phydev->duplex; - port->speed = phydev->speed; - } - } - - if (phydev->link != port->link || link_reconfigured) { - port->link = phydev->link; - - if (phydev->link) { - if (port->phy_interface == PHY_INTERFACE_MODE_RGMII || - port->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || - port->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || - port->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID || - port->phy_interface == PHY_INTERFACE_MODE_SGMII) { - val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); - val |= (MVPP2_GMAC_FORCE_LINK_PASS | - MVPP2_GMAC_FORCE_LINK_DOWN); - writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); - } - - mvpp2_interrupts_enable(port); - mvpp2_port_enable(port); - - mvpp2_egress_enable(port); - mvpp2_ingress_enable(port); - netif_carrier_on(dev); - netif_tx_wake_all_queues(dev); - } else { - port->duplex = -1; - port->speed = 0; - - netif_tx_stop_all_queues(dev); - netif_carrier_off(dev); - mvpp2_ingress_disable(port); - mvpp2_egress_disable(port); - - mvpp2_port_disable(port); - mvpp2_interrupts_disable(port); - } - - phy_print_status(phydev); - } -} - static void mvpp2_timer_set(struct mvpp2_port_pcpu *port_pcpu) { ktime_t interval; @@ -6047,7 +8708,60 @@ phys_addr_t phys_addr; void *buf; - /* No recycle or too many buffers are in use, so allocate a new skb */ +#ifdef CONFIG_MVPP2_FBX_FF + if (ff_enabled) { + struct mvpp2_port *opp_ports[2]; + unsigned int i, count; + + /* + * try to reclaim from opposite fast forward dedicated + * tx queues + */ + count = ff_get_opposite_ports(port, opp_ports); + if (!count) + goto alloc; + + for (i = 0; i < count; i++) { + struct mvpp2_port *opp_port = opp_ports[i]; + struct mvpp2_tx_queue *txq; + struct mvpp2_txq_pcpu *txq_pcpu; + struct mvpp2_txq_pcpu_buf *tx_buf; + + txq = opp_port->ff_txq; + if (WARN_ON(txq->log_id != MVPP2_FF_TXQ_ID)) + continue; + + txq_pcpu = this_cpu_ptr(txq->pcpu); + if (!txq_pcpu->count) + continue; + + if (!txq_pcpu->release_pending) + txq_pcpu->release_pending = + mvpp2_txq_sent_desc_proc(opp_port, txq); + + if (!txq_pcpu->release_pending) + continue; + + tx_buf = txq_pcpu->buffs + txq_pcpu->txq_get_index; + if (WARN_ON(!tx_buf->is_rx_buf)) + continue; + + mvpp2_bm_pool_put(port, + tx_buf->pool, + tx_buf->bm_dma, + tx_buf->bm_phys); + + txq_pcpu->release_pending--; + txq_pcpu->count--; + mvpp2_txq_inc_get(txq_pcpu); + return 0; + } + } +alloc: +#endif + + /* No recycle or too many buffers are in use, so allocate a + * new skb */ buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr, &phys_addr, GFP_ATOMIC); if (!buf) @@ -6100,6 +8814,10 @@ u32 rcvd_pkts = 0; u32 rcvd_bytes = 0; +#ifdef CONFIG_MVPP2_FBX_FF + spin_lock(&ff_lock); +#endif + /* Get number of received packets and clamp the to-do */ rx_received = mvpp2_rxq_received(port, rxq->id); if (rx_todo > rx_received) @@ -6142,6 +8860,18 @@ continue; } +#ifdef CONFIG_MVPP2_FBX_FF + if (ff_receive(port, + pool, + rx_desc, + data, + MVPP2_MH_SIZE + NET_SKB_PAD, rx_bytes)) { + rcvd_pkts++; + rcvd_bytes += rx_bytes; + continue; + } +#endif + if (bm_pool->frag_size > PAGE_SIZE) frag_size = 0; else @@ -6173,6 +8903,10 @@ napi_gro_receive(napi, skb); } +#ifdef CONFIG_MVPP2_FBX_FF + spin_unlock(&ff_lock); +#endif + if (rcvd_pkts) { struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); @@ -6231,10 +8965,7 @@ goto cleanup; } - mvpp2_txdesc_offset_set(port, tx_desc, - buf_dma_addr & MVPP2_TX_DESC_ALIGN); - mvpp2_txdesc_dma_addr_set(port, tx_desc, - buf_dma_addr & ~MVPP2_TX_DESC_ALIGN); + mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); if (i == (skb_shinfo(skb)->nr_frags - 1)) { /* Last descriptor */ @@ -6277,8 +9008,7 @@ addr = txq_pcpu->tso_headers_dma + txq_pcpu->txq_put_index * TSO_HEADER_SIZE; - mvpp2_txdesc_offset_set(port, tx_desc, addr & MVPP2_TX_DESC_ALIGN); - mvpp2_txdesc_dma_addr_set(port, tx_desc, addr & ~MVPP2_TX_DESC_ALIGN); + mvpp2_txdesc_dma_addr_set(port, tx_desc, addr); mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) | MVPP2_TXD_F_DESC | @@ -6307,10 +9037,7 @@ return -ENOMEM; } - mvpp2_txdesc_offset_set(port, tx_desc, - buf_dma_addr & MVPP2_TX_DESC_ALIGN); - mvpp2_txdesc_dma_addr_set(port, tx_desc, - buf_dma_addr & ~MVPP2_TX_DESC_ALIGN); + mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); if (!left) { mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC); @@ -6422,10 +9149,7 @@ goto out; } - mvpp2_txdesc_offset_set(port, tx_desc, - buf_dma_addr & MVPP2_TX_DESC_ALIGN); - mvpp2_txdesc_dma_addr_set(port, tx_desc, - buf_dma_addr & ~MVPP2_TX_DESC_ALIGN); + mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); tx_cmd = mvpp2_skb_tx_csum(port, skb); @@ -6444,7 +9168,6 @@ if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) { tx_desc_unmap_put(port, txq, tx_desc); frags = 0; - goto out; } } @@ -6461,7 +9184,7 @@ wmb(); mvpp2_aggr_txq_pend_desc_add(port, frags); - if (txq_pcpu->size - txq_pcpu->count < MAX_SKB_FRAGS + 1) + if (txq_pcpu->count >= txq_pcpu->stop_threshold) netif_tx_stop_queue(nq); u64_stats_update_begin(&stats->syncp); @@ -6506,6 +9229,10 @@ struct mvpp2_queue_vector *qv; int cpu = smp_processor_id(); +#ifdef CONFIG_MVPP2_FBX_FF + ff.jiffies = jiffies; +#endif + qv = container_of(napi, struct mvpp2_queue_vector, napi); /* Rx/Tx cause register @@ -6518,7 +9245,7 @@ * * Each CPU has its own Rx/Tx cause register */ - cause_rx_tx = mvpp2_percpu_read(port->priv, qv->sw_thread_id, + cause_rx_tx = mvpp2_percpu_read_relaxed(port->priv, qv->sw_thread_id, MVPP2_ISR_RX_TX_CAUSE_REG(port->id)); cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK; @@ -6577,7 +9304,6 @@ /* Set hw internals when starting port */ static void mvpp2_start_dev(struct mvpp2_port *port) { - struct net_device *ndev = port->dev; int i; if (port->gop_id == 0 && @@ -6602,15 +9328,14 @@ mvpp2_port_mii_set(port); mvpp2_port_enable(port); - if (ndev->phydev) - phy_start(ndev->phydev); + if (port->phylink) + phylink_start(port->phylink); netif_tx_start_all_queues(port->dev); } /* Set hw internals when stopping port */ static void mvpp2_stop_dev(struct mvpp2_port *port) { - struct net_device *ndev = port->dev; int i; /* Stop new packets from arriving to RXQs */ @@ -6629,8 +9354,8 @@ mvpp2_egress_disable(port); mvpp2_port_disable(port); - if (ndev->phydev) - phy_stop(ndev->phydev); + if (port->phylink) + phylink_stop(port->phylink); phy_power_off(port->comphy); } @@ -6643,16 +9368,22 @@ if (ring->rx_pending == 0 || ring->tx_pending == 0) return -EINVAL; - if (ring->rx_pending > MVPP2_MAX_RXD) - new_rx_pending = MVPP2_MAX_RXD; + if (ring->rx_pending > MVPP2_MAX_RXD_MAX) + new_rx_pending = MVPP2_MAX_RXD_MAX; else if (!IS_ALIGNED(ring->rx_pending, 16)) new_rx_pending = ALIGN(ring->rx_pending, 16); - if (ring->tx_pending > MVPP2_MAX_TXD) - new_tx_pending = MVPP2_MAX_TXD; + if (ring->tx_pending > MVPP2_MAX_TXD_MAX) + new_tx_pending = MVPP2_MAX_TXD_MAX; else if (!IS_ALIGNED(ring->tx_pending, 32)) new_tx_pending = ALIGN(ring->tx_pending, 32); + /* The Tx ring size cannot be smaller than the minimum number of + * descriptors needed for TSO. + */ + if (new_tx_pending < MVPP2_MAX_SKB_DESCS) + new_tx_pending = ALIGN(MVPP2_MAX_SKB_DESCS, 32); + if (ring->rx_pending != new_rx_pending) { netdev_info(dev, "illegal Rx ring size value %d, round to %d\n", ring->rx_pending, new_rx_pending); @@ -6683,40 +9414,6 @@ addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF; } -static int mvpp2_phy_connect(struct mvpp2_port *port) -{ - struct phy_device *phy_dev; - - /* No PHY is attached */ - if (!port->phy_node) - return 0; - - phy_dev = of_phy_connect(port->dev, port->phy_node, mvpp2_link_event, 0, - port->phy_interface); - if (!phy_dev) { - netdev_err(port->dev, "cannot connect to phy\n"); - return -ENODEV; - } - phy_dev->supported &= PHY_GBIT_FEATURES; - phy_dev->advertising = phy_dev->supported; - - port->link = 0; - port->duplex = 0; - port->speed = 0; - - return 0; -} - -static void mvpp2_phy_disconnect(struct mvpp2_port *port) -{ - struct net_device *ndev = port->dev; - - if (!ndev->phydev) - return; - - phy_disconnect(ndev->phydev); -} - static int mvpp2_irqs_init(struct mvpp2_port *port) { int err, i; @@ -6761,6 +9458,63 @@ } } +static inline u32 mvpp22_rxfh_indir(struct mvpp2_port *port, u32 rxq) +{ + int nrxqs, cpus = num_present_cpus(); + + /* Number of RXQs per CPU */ + nrxqs = port->nrxqs / cpus; + + /* Indirection to better distribute the paquets on the CPUs when + * configuring the RSS queues. + */ + return (rxq * nrxqs + rxq / cpus) % port->nrxqs; +} + +static void mvpp22_rss_fill_table(struct mvpp2_port *port, u32 table) +{ + struct mvpp2 *priv = port->priv; + int i; + + for (i = 0; i < MVPP22_RSS_TABLE_ENTRIES; i++) { + u32 sel = MVPP22_RSS_INDEX_TABLE(table) | + MVPP22_RSS_INDEX_TABLE_ENTRY(i); + mvpp2_write(priv, MVPP22_RSS_INDEX, sel); + + mvpp2_write(priv, MVPP22_RSS_TABLE_ENTRY, + mvpp22_rxfh_indir(port, port->indir[i])); + } +} + +static void mvpp22_init_rss(struct mvpp2_port *port) +{ + struct mvpp2 *priv = port->priv; + int i; + + /* Set the table width: replace the whole classifier Rx queue number + * with the ones configured in RSS table entries. + */ + mvpp2_write(priv, MVPP22_RSS_INDEX, MVPP22_RSS_INDEX_TABLE(0)); + mvpp2_write(priv, MVPP22_RSS_WIDTH, 8); + + /* Loop through the classifier Rx Queues and map them to a RSS table. + * Map them all to the first table (0) by default. + */ + for (i = 0; i < MVPP2_CLS_RX_QUEUES; i++) { + mvpp2_write(priv, MVPP22_RSS_INDEX, MVPP22_RSS_INDEX_QUEUE(i)); + mvpp2_write(priv, MVPP22_RSS_TABLE, + MVPP22_RSS_TABLE_POINTER(0)); + } + + /* Configure the first table to evenly distribute the packets across + * real Rx Queues. The table entries map a hash to a port Rx Queue. + */ + for (i = 0; i < MVPP22_RSS_TABLE_ENTRIES; i++) + port->indir[i] = ethtool_rxfh_indir_default(i, port->nrxqs); + + mvpp22_rss_fill_table(port, 0); +} + static int mvpp2_open(struct net_device *dev) { struct mvpp2_port *port = netdev_priv(dev); @@ -6810,7 +9564,16 @@ goto err_cleanup_txqs; } - if (priv->hw_version == MVPP22 && !port->phy_node && port->link_irq) { + /* In default link is down */ + netif_carrier_off(port->dev); + + if (port->phylink) { + err = phylink_of_phy_connect(port->phylink, port->of_node); + if (err) { + netdev_err(port->dev, "could not attach PHY (%d)\n", err); + goto err_free_irq; + } + } else if (port->link_irq) { err = request_irq(port->link_irq, mvpp2_link_status_isr, 0, dev->name, port); if (err) { @@ -6820,14 +9583,15 @@ } mvpp22_gop_setup_irq(port); + } else { + netdev_err(dev, "cannot use phylink or GoP link IRQ\n"); + goto err_free_irq; } - /* In default link is down */ - netif_carrier_off(port->dev); - err = mvpp2_phy_connect(port); - if (err < 0) - goto err_free_link_irq; +#ifdef CONFIG_MVPP2_FBX_FF + port->ff_txq = port->txqs[MVPP2_FF_TXQ_ID]; +#endif /* Unmask interrupts on all CPUs */ on_each_cpu(mvpp2_interrupts_unmask, port, 1); @@ -6835,11 +9599,22 @@ mvpp2_start_dev(port); + if (priv->hw_version == MVPP22) + mvpp22_init_rss(port); + + /* Start hardware statistics gathering */ + queue_delayed_work(priv->stats_queue, &port->stats_work, + MVPP2_MIB_COUNTERS_STATS_DELAY); + +#ifdef CONFIG_MVPP2_FBX_FF + { + int ff_idx = (port->priv->id << 1) | port->index; + WARN_ON(ports_by_idx[ff_idx] != NULL); + ports_by_idx[ff_idx] = port; + } +#endif return 0; -err_free_link_irq: - if (priv->hw_version == MVPP22 && !port->phy_node && port->link_irq) - free_irq(port->link_irq, port); err_free_irq: mvpp2_irqs_deinit(port); err_cleanup_txqs: @@ -6853,17 +9628,24 @@ { struct mvpp2_port *port = netdev_priv(dev); struct mvpp2_port_pcpu *port_pcpu; - struct mvpp2 *priv = port->priv; int cpu; +#ifdef CONFIG_MVPP2_FBX_FF + { + int ff_idx = (port->priv->id << 1) | port->index; + ports_by_idx[ff_idx] = NULL; + } +#endif + mvpp2_stop_dev(port); - mvpp2_phy_disconnect(port); + if (port->phylink) + phylink_disconnect_phy(port->phylink); /* Mask interrupts on all CPUs */ on_each_cpu(mvpp2_interrupts_mask, port, 1); mvpp2_shared_interrupt_mask_unmask(port, true); - if (priv->hw_version == MVPP22 && !port->phy_node && port->link_irq) + if (port->link_irq) free_irq(port->link_irq, port); mvpp2_irqs_deinit(port); @@ -6879,6 +9661,12 @@ mvpp2_cleanup_rxqs(port); mvpp2_cleanup_txqs(port); + cancel_delayed_work_sync(&port->stats_work); + +#ifdef CONFIG_MVPP2_FBX_FF + port->ff_txq = NULL; +#endif + return 0; } @@ -7031,22 +9819,65 @@ stats->tx_dropped = dev->stats.tx_dropped; } +static int mii_bus_read(struct net_device *dev, int mii_id, int regnum) +{ + struct mvpp2_port *port = netdev_priv(dev); + + return port->mii_bus->read(port->mii_bus, mii_id, regnum); +} + +static void mii_bus_write(struct net_device *dev, int mii_id, int regnum, + int value) +{ + struct mvpp2_port *port = netdev_priv(dev); + + port->mii_bus->write(port->mii_bus, mii_id, regnum, value); +} + static int mvpp2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) { - int ret; + struct mvpp2_port *port = netdev_priv(dev); + + if (!port->phylink) { + struct mii_if_info mii; - if (!dev->phydev) + if (!port->mii_bus) return -ENOTSUPP; - ret = phy_mii_ioctl(dev->phydev, ifr, cmd); - if (!ret) - mvpp2_link_event(dev); + mii.dev = dev; + mii.mdio_read = mii_bus_read; + mii.mdio_write = mii_bus_write; + mii.phy_id = 0; + mii.phy_id_mask = 0x3f; + mii.reg_num_mask = 0x1f; + return generic_mii_ioctl(&mii, if_mii(ifr), cmd, NULL); + } - return ret; + return phylink_mii_ioctl(port->phylink, ifr, cmd); } /* Ethtool methods */ +static int mvpp2_ethtool_nway_reset(struct net_device *dev) +{ + struct mvpp2_port *port = netdev_priv(dev); + + if (!port->phylink) { + u32 val; + + /* actually we are testing if autoneg is enabled */ + if (port->phy_interface != PHY_INTERFACE_MODE_1000BASEX) + return -ENOTSUPP; + + val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); + val |= MVPP2_GMAC_IN_BAND_RESTART_AN; + writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); + return 0; + } + + return phylink_ethtool_nway_reset(port->phylink); +} + /* Set interrupt coalescing for ethtools */ static int mvpp2_ethtool_set_coalesce(struct net_device *dev, struct ethtool_coalesce *c) @@ -7089,6 +9920,7 @@ c->rx_coalesce_usecs = port->rxqs[0]->time_coal; c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal; c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal; + c->tx_coalesce_usecs = port->tx_time_coal; return 0; } @@ -7108,8 +9940,8 @@ { struct mvpp2_port *port = netdev_priv(dev); - ring->rx_max_pending = MVPP2_MAX_RXD; - ring->tx_max_pending = MVPP2_MAX_TXD; + ring->rx_max_pending = MVPP2_MAX_RXD_MAX; + ring->tx_max_pending = MVPP2_MAX_TXD_MAX; ring->rx_pending = port->rx_ring_size; ring->tx_pending = port->tx_ring_size; } @@ -7174,6 +10006,278 @@ return err; } +static void mvpp2_ethtool_get_pause_param(struct net_device *dev, + struct ethtool_pauseparam *pause) +{ + struct mvpp2_port *port = netdev_priv(dev); + + if (!port->phylink) + return; + + phylink_ethtool_get_pauseparam(port->phylink, pause); +} + +static int mvpp2_ethtool_set_pause_param(struct net_device *dev, + struct ethtool_pauseparam *pause) +{ + struct mvpp2_port *port = netdev_priv(dev); + + if (!port->phylink) + return -ENOTSUPP; + + return phylink_ethtool_set_pauseparam(port->phylink, pause); +} + +static int mvpp2_ethtool_get_link_ksettings(struct net_device *dev, + struct ethtool_link_ksettings *cmd) +{ + struct mvpp2_port *port = netdev_priv(dev); + + if (!port->phylink) + return -ENOTSUPP; + + return phylink_ethtool_ksettings_get(port->phylink, cmd); +} + +static int mvpp2_ethtool_set_link_ksettings(struct net_device *dev, + const struct ethtool_link_ksettings *cmd) +{ + struct mvpp2_port *port = netdev_priv(dev); + + if (!port->phylink) + return -ENOTSUPP; + + return phylink_ethtool_ksettings_set(port->phylink, cmd); +} + +static int mvpp2_ethtool_get_rxnfc(struct net_device *dev, + struct ethtool_rxnfc *info, u32 *rules) +{ + struct mvpp2_port *port = netdev_priv(dev); + struct mvpp2 *priv = port->priv; + + if (priv->hw_version != MVPP22) + return -EOPNOTSUPP; + + switch (info->cmd) { + case ETHTOOL_GRXRINGS: + info->data = port->nrxqs; + break; + default: + return -ENOTSUPP; + } + + return 0; +} + +static u32 mvpp2_ethtool_get_rxfh_indir_size(struct net_device *dev) +{ + struct mvpp2_port *port = netdev_priv(dev); + struct mvpp2 *priv = port->priv; + + return (priv->hw_version != MVPP22) ? 0 : MVPP22_RSS_TABLE_ENTRIES; +} + +static int mvpp2_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, + u8 *hfunc) +{ + struct mvpp2_port *port = netdev_priv(dev); + struct mvpp2 *priv = port->priv; + + if (priv->hw_version != MVPP22) + return -EOPNOTSUPP; + + if (indir) + memcpy(indir, port->indir, + ARRAY_SIZE(port->indir) * sizeof(port->indir[0])); + + if (hfunc) + *hfunc = ETH_RSS_HASH_TOP; + + return 0; +} + +static int mvpp2_ethtool_set_rxfh(struct net_device *dev, const u32 *indir, + const u8 *key, const u8 hfunc) +{ + struct mvpp2_port *port = netdev_priv(dev); + struct mvpp2 *priv = port->priv; + + if (priv->hw_version != MVPP22) + return -EOPNOTSUPP; + + if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP) + return -ENOTSUPP; + + if (key) + return -ENOTSUPP; + + if (indir) { + memcpy(port->indir, indir, + ARRAY_SIZE(port->indir) * sizeof(port->indir[0])); + mvpp22_rss_fill_table(port, 0); + } + + return 0; +} + +/* + * changes the phy interface mode of the interface to either + * 1000Base-X or 10000Base-X depending on what was requested via the + * ethetool private flags interface. + */ +static int maybe_switch_mode(struct net_device *dev, u32 flags) +{ + struct mvpp2_port *port = netdev_priv(dev); + int target_phy_mode; + + /* + * port must be 10G capable (i.e. gop port 0) + */ + if (port->gop_id != 0) + return -EINVAL; + + /* + * can't enable both 1G and 10G at the same time + */ + if ((flags & FBX_ALL_EN_MASK) == FBX_ALL_EN_MASK) + return -EINVAL; + + /* + * select proper target phy mode (or return early if non is + * set yet). + */ + if (flags & (1 << FBX_10G_EN_BIT)) + target_phy_mode = PHY_INTERFACE_MODE_10GKR; + else if (flags & (1 << FBX_1G_EN_BIT)) + target_phy_mode = PHY_INTERFACE_MODE_1000BASEX; + else + return 0; + + if (port->phy_interface == target_phy_mode) + return 0; + + netdev_info(dev, "switching PHY interface mode from %s to %s\n", + phy_modes(port->phy_interface), phy_modes(target_phy_mode)); + + if (!netif_running(dev)) { + port->phy_interface = target_phy_mode; + return 0; + } + + mvpp2_stop_dev(port); + + port->phy_interface = target_phy_mode; + + if (port->link_irq) + /* + * link interrupt configuration depends on port PHY + * interface mode. + */ + mvpp22_gop_setup_irq(port); + + mvpp2_start_dev(port); + mvpp2_egress_enable(port); + mvpp2_ingress_enable(port); + + return 0; +} + +static int mvpp2_ethtool_set_priv_flags(struct net_device *dev, u32 flags) +{ + struct mvpp2_port *port = netdev_priv(dev); + + if (flags & (1 << FBX_CLEAR_MIB_BIT)) { + memset(port->ethtool_stats, 0, + sizeof(u64) * ARRAY_SIZE(mvpp2_ethtool_regs)); + flags &= ~(1 << FBX_CLEAR_MIB_BIT); + } + + if (!flags) + return 0; + + if (port->gop_id != 0) + /* + * only GOP port ID0 supports 10G speeds. + */ + return -ENOTSUPP; + + if (flags & (1 << FBX_101G_SWITCH_EN_BIT)) + /* set only */ + port->en_fbx_10g1g_switch = true; + + if (!port->en_fbx_10g1g_switch) + return 0; + + return maybe_switch_mode(dev, flags); +} + +static int mvpp2_get_port_sync_ok(struct net_device *dev) +{ + struct mvpp2_port *port = netdev_priv(dev); + struct mvpp2 *priv = port->priv; + u32 v; + + if (!netif_running(dev)) + return 0; + + if (port->gop_id == 0 && + port->phy_interface == PHY_INTERFACE_MODE_10GKR) { + /* + * on port0 in 10GKR mode, get sync ok from MPCS + * gearbox register, field Lane Locked. + */ + void __iomem *mpcs = priv->iface_base + + MVPP22_MPCS_BASE(port->gop_id); + + v = readl(mpcs + MVPP22_MPCS_GEARBOX_STATUS) & + MVPP22_MPCS_GEARBOX_STATUS_LANELOCK; + } else + /* otherwise default to GMAC SyncOk status.*/ + v = readl(port->base + MVPP2_GMAC_STATUS0) & + MVPP2_GMAC_STATUS0_SYNC_OK; + return !!v; +} + +static u32 mvpp2_ethtool_get_priv_flags(struct net_device *dev) +{ + struct mvpp2_port *port = netdev_priv(dev); + u32 ret = 0; + + ret |= (!!port->en_fbx_10g1g_switch << FBX_101G_SWITCH_EN_BIT); + + if (!ret) + return ret; + + switch (port->phy_interface) { + case PHY_INTERFACE_MODE_1000BASEX: + ret |= (1 << FBX_1G_ST_BIT); + break; + case PHY_INTERFACE_MODE_10GKR: + ret |= (1 << FBX_10G_ST_BIT); + break; + default: + break; + } + + ret |= mvpp2_get_port_sync_ok(dev) << FBX_SYNC_OK_BIT; + + return ret; +} + +/* + * netdevice ->ndo_select_queue() callback + */ +static u16 mvpp2_select_queue(struct net_device *dev, + struct sk_buff *skb, + void *accel_priv, + select_queue_fallback_t fallback) +{ + if (skb->priority >= TC_PRIO_INTERACTIVE) + return MVPP2_USABLE_TX_QUEUES - 1; + return 0; +} + /* Device ops */ static const struct net_device_ops mvpp2_netdev_ops = { @@ -7185,18 +10289,30 @@ .ndo_change_mtu = mvpp2_change_mtu, .ndo_get_stats64 = mvpp2_get_stats64, .ndo_do_ioctl = mvpp2_ioctl, + .ndo_select_queue = mvpp2_select_queue, }; static const struct ethtool_ops mvpp2_eth_tool_ops = { - .nway_reset = phy_ethtool_nway_reset, + .nway_reset = mvpp2_ethtool_nway_reset, .get_link = ethtool_op_get_link, .set_coalesce = mvpp2_ethtool_set_coalesce, .get_coalesce = mvpp2_ethtool_get_coalesce, .get_drvinfo = mvpp2_ethtool_get_drvinfo, .get_ringparam = mvpp2_ethtool_get_ringparam, .set_ringparam = mvpp2_ethtool_set_ringparam, - .get_link_ksettings = phy_ethtool_get_link_ksettings, - .set_link_ksettings = phy_ethtool_set_link_ksettings, + .get_pauseparam = mvpp2_ethtool_get_pause_param, + .set_pauseparam = mvpp2_ethtool_set_pause_param, + .get_strings = mvpp2_ethtool_get_strings, + .get_ethtool_stats = mvpp2_ethtool_get_stats, + .get_sset_count = mvpp2_ethtool_get_sset_count, + .get_link_ksettings = mvpp2_ethtool_get_link_ksettings, + .set_link_ksettings = mvpp2_ethtool_set_link_ksettings, + .get_rxnfc = mvpp2_ethtool_get_rxnfc, + .get_rxfh_indir_size = mvpp2_ethtool_get_rxfh_indir_size, + .get_rxfh = mvpp2_ethtool_get_rxfh, + .set_rxfh = mvpp2_ethtool_set_rxfh, + .set_priv_flags = mvpp2_ethtool_set_priv_flags, + .get_priv_flags = mvpp2_ethtool_get_priv_flags, }; /* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that @@ -7496,17 +10612,185 @@ eth_hw_addr_random(dev); } +static void mvpp2_phylink_validate(struct net_device *dev, + unsigned long *supported, + struct phylink_link_state *state) +{ + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; + + phylink_set_port_modes(mask); + + phylink_set(mask, Autoneg); + phylink_set(mask, Pause); + phylink_set(mask, Asym_Pause); + + phylink_set(mask, 10baseT_Half); + phylink_set(mask, 10baseT_Full); + phylink_set(mask, 100baseT_Half); + phylink_set(mask, 100baseT_Full); + phylink_set(mask, 1000baseT_Half); + phylink_set(mask, 1000baseT_Full); + phylink_set(mask, 1000baseX_Full); + phylink_set(mask, 10000baseKR_Full); + + bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); + bitmap_and(state->advertising, state->advertising, mask, + __ETHTOOL_LINK_MODE_MASK_NBITS); +} + +static int mvpp2_phylink_mac_link_state(struct net_device *dev, + struct phylink_link_state *state) +{ + struct mvpp2_port *port = netdev_priv(dev); + u32 val; + + if (!phy_interface_mode_is_rgmii(port->phy_interface) && + port->phy_interface != PHY_INTERFACE_MODE_SGMII) + return 0; + + val = readl(port->base + MVPP2_GMAC_STATUS0); + + state->an_complete = !!(val & MVPP2_GMAC_STATUS0_AN_COMPLETE); + state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP); + state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX); + + if (val & MVPP2_GMAC_STATUS0_GMII_SPEED) + state->speed = SPEED_1000; + else + state->speed = (val & MVPP2_GMAC_STATUS0_MII_SPEED) ? + SPEED_100 : SPEED_10; + + state->pause = 0; + if (val & MVPP2_GMAC_STATUS0_RX_PAUSE) + state->pause |= MLO_PAUSE_RX; + if (val & MVPP2_GMAC_STATUS0_TX_PAUSE) + state->pause |= MLO_PAUSE_TX; + + return 1; +} + +static void mvpp2_mac_an_restart(struct net_device *dev) +{ + struct mvpp2_port *port = netdev_priv(dev); + u32 val; + + if (!phy_interface_mode_is_rgmii(port->phy_interface) && + port->phy_interface != PHY_INTERFACE_MODE_SGMII) + return; + + val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); + val |= MVPP2_GMAC_IN_BAND_RESTART_AN; + writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); +} + +static void mvpp2_mac_config(struct net_device *dev, unsigned int mode, + const struct phylink_link_state *state) +{ + struct mvpp2_port *port = netdev_priv(dev); + u32 val; + + /* disable current port for reconfiguration */ + mvpp2_interrupts_disable(port); + netif_carrier_off(port->dev); + mvpp2_port_disable(port); + phy_power_off(port->comphy); + + /* comphy reconfiguration */ + port->phy_interface = state->interface; + mvpp22_comphy_init(port); + + /* gop/mac reconfiguration */ + mvpp22_gop_init(port); + mvpp2_port_mii_set(port); + + if (!phy_interface_mode_is_rgmii(port->phy_interface) && + port->phy_interface != PHY_INTERFACE_MODE_SGMII) + return; + + val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); + val &= ~(MVPP2_GMAC_CONFIG_MII_SPEED | + MVPP2_GMAC_CONFIG_GMII_SPEED | + MVPP2_GMAC_CONFIG_FULL_DUPLEX | + MVPP2_GMAC_AN_SPEED_EN | + MVPP2_GMAC_AN_DUPLEX_EN); + + if (state->duplex) + val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX; + + if (state->speed == SPEED_1000) + val |= MVPP2_GMAC_CONFIG_GMII_SPEED; + else if (state->speed == SPEED_100) + val |= MVPP2_GMAC_CONFIG_MII_SPEED; + + writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); + + if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK) + mvpp2_port_loopback_set(port, state); +} + +static void mvpp2_mac_link_down(struct net_device *dev, unsigned int mode) +{ + struct mvpp2_port *port = netdev_priv(dev); + u32 val; + + netif_tx_stop_all_queues(dev); + netif_carrier_off(dev); + mvpp2_ingress_disable(port); + mvpp2_egress_disable(port); + + mvpp2_port_disable(port); + mvpp2_interrupts_disable(port); + + if (!phylink_autoneg_inband(mode)) { + val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); + val &= ~MVPP2_GMAC_FORCE_LINK_PASS; + val |= MVPP2_GMAC_FORCE_LINK_DOWN; + writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); + } +} + +static void mvpp2_mac_link_up(struct net_device *dev, unsigned int mode, + struct phy_device *phy) +{ + struct mvpp2_port *port = netdev_priv(dev); + u32 val; + + if (!phylink_autoneg_inband(mode)) { + val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); + val &= ~MVPP2_GMAC_FORCE_LINK_DOWN; + val |= MVPP2_GMAC_FORCE_LINK_PASS; + writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); + } + + mvpp2_interrupts_enable(port); + mvpp2_port_enable(port); + + mvpp2_egress_enable(port); + mvpp2_ingress_enable(port); + netif_carrier_on(dev); + netif_tx_wake_all_queues(dev); +} + +static const struct phylink_mac_ops mvpp2_phylink_ops = { + .validate = mvpp2_phylink_validate, + .mac_link_state = mvpp2_phylink_mac_link_state, + .mac_an_restart = mvpp2_mac_an_restart, + .mac_config = mvpp2_mac_config, + .mac_link_down = mvpp2_mac_link_down, + .mac_link_up = mvpp2_mac_link_up, +}; + /* Ports initialization */ static int mvpp2_port_probe(struct platform_device *pdev, struct device_node *port_node, struct mvpp2 *priv, int index) { - struct device_node *phy_node; struct phy *comphy; struct mvpp2_port *port; struct mvpp2_port_pcpu *port_pcpu; struct net_device *dev; struct resource *res; + struct phylink *phylink; char *mac_from = ""; unsigned int ntxqs, nrxqs; bool has_tx_irqs; @@ -7514,6 +10798,7 @@ int features; int phy_mode; int err, i, cpu; + struct device_node *mdio_node; has_tx_irqs = mvpp2_port_has_tx_irqs(priv, port_node); @@ -7530,7 +10815,6 @@ if (!dev) return -ENOMEM; - phy_node = of_parse_phandle(port_node, "phy", 0); phy_mode = of_get_phy_mode(port_node); if (phy_mode < 0) { dev_err(&pdev->dev, "incorrect phy mode\n"); @@ -7553,7 +10837,7 @@ goto err_free_netdev; } - dev->tx_queue_len = MVPP2_MAX_TXD; + dev->tx_queue_len = MVPP2_MAX_TXD_MAX; dev->watchdog_timeo = 5 * HZ; dev->netdev_ops = &mvpp2_netdev_ops; dev->ethtool_ops = &mvpp2_eth_tool_ops; @@ -7565,19 +10849,19 @@ port->priv = priv; port->has_tx_irqs = has_tx_irqs; + mdio_node = of_parse_phandle(port_node, "mdio-bus", 0); + if (mdio_node) { + port->mii_bus = of_mdio_find_bus(mdio_node); + if (!port->mii_bus) { + err = -EPROBE_DEFER; + goto err_free_netdev; + } + } + err = mvpp2_queue_vectors_init(port, port_node); if (err) goto err_free_netdev; - port->link_irq = of_irq_get_byname(port_node, "link"); - if (port->link_irq == -EPROBE_DEFER) { - err = -EPROBE_DEFER; - goto err_deinit_qvecs; - } - if (port->link_irq <= 0) - /* the link irq is optional */ - port->link_irq = 0; - if (of_property_read_bool(port_node, "marvell,loopback")) port->flags |= MVPP2_F_LOOPBACK; @@ -7587,7 +10871,7 @@ else port->first_rxq = port->id * priv->max_port_rxqs; - port->phy_node = phy_node; + port->of_node = port_node; port->phy_interface = phy_mode; port->comphy = comphy; @@ -7596,8 +10880,12 @@ port->base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(port->base)) { err = PTR_ERR(port->base); - goto err_free_irq; + goto err_deinit_qvecs; } + + port->stats_base = port->priv->lms_base + + MVPP21_MIB_COUNTERS_OFFSET + + port->gop_id * MVPP21_MIB_COUNTERS_PORT_SZ; } else { if (of_property_read_u32(port_node, "gop-port-id", &port->gop_id)) { @@ -7607,20 +10895,36 @@ } port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id); + port->stats_base = port->priv->iface_base + + MVPP22_MIB_COUNTERS_OFFSET + + port->gop_id * MVPP22_MIB_COUNTERS_PORT_SZ; } - /* Alloc per-cpu stats */ + /* Alloc per-cpu and ethtool stats */ port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats); if (!port->stats) { err = -ENOMEM; - goto err_free_irq; + goto err_deinit_qvecs; + } + + port->ethtool_stats = devm_kcalloc(&pdev->dev, + ARRAY_SIZE(mvpp2_ethtool_regs), + sizeof(u64), GFP_KERNEL); + if (!port->ethtool_stats) { + err = -ENOMEM; + goto err_free_stats; } + mutex_init(&port->gather_stats_lock); + INIT_DELAYED_WORK(&port->stats_work, mvpp2_gather_hw_statistics); + mvpp2_port_copy_mac_addr(dev, priv, port_node, &mac_from); - port->tx_ring_size = MVPP2_MAX_TXD; - port->rx_ring_size = MVPP2_MAX_RXD; + port->tx_ring_size = MVPP2_MAX_TXD_DFLT; + port->rx_ring_size = MVPP2_MAX_RXD_DFLT; SET_NETDEV_DEV(dev, &pdev->dev); + port->index = index; + dev->dev_port = index; err = mvpp2_port_init(port); if (err < 0) { @@ -7656,26 +10960,71 @@ } } - features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; + features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | + NETIF_F_TSO; dev->features = features | NETIF_F_RXCSUM; dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO; - dev->vlan_features |= features; - /* MTU range: 68 - 9676 */ + if (port->pool_long->id == MVPP2_BM_JUMBO && port->id != 0) { + dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); + dev->hw_features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); + } + + dev->vlan_features |= (features & ~NETIF_F_IP_CSUM); + dev->gso_max_segs = MVPP2_MAX_TSO_SEGS; + + /* MTU range: 68 - 9704 */ dev->min_mtu = ETH_MIN_MTU; - /* 9676 == 9700 - 20 and rounding to 8 */ - dev->max_mtu = 9676; + /* 9704 == 9728 - 20 and rounding to 8 */ + dev->max_mtu = MVPP2_BM_JUMBO_PKT_SIZE; + + /* The PHY node is optional. If not present the GoP link IRQ will be + * used to handle link updates. Otherwise use phylink. + */ + if (of_find_property(port_node, "phy", NULL)) { + phylink = phylink_create(dev, port_node, phy_mode, + &mvpp2_phylink_ops); + if (IS_ERR(phylink)) { + err = PTR_ERR(phylink); + goto err_free_port_pcpu; + } + port->phylink = phylink; + port->link_irq = 0; + } else { + port->phylink = NULL; + if (priv->hw_version == MVPP22) { + port->link_irq = of_irq_get_byname(port_node, "link"); + if (port->link_irq == -EPROBE_DEFER) { + err = -EPROBE_DEFER; + goto err_free_port_pcpu; + } + if (port->link_irq <= 0) + /* the link irq is optional */ + port->link_irq = 0; + } + } err = register_netdev(dev); if (err < 0) { dev_err(&pdev->dev, "failed to register netdev\n"); - goto err_free_port_pcpu; + goto err_phylink_irq; } netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr); priv->port_list[index] = port; + +#ifdef CONFIG_MVPP2_FBX_FF + port->ff_notifier.notifier_call = ff_device_event; + register_netdevice_notifier(&port->ff_notifier); +#endif + return 0; +err_phylink_irq: + if (port->phylink) + phylink_destroy(port->phylink); + else if (port->link_irq) + irq_dispose_mapping(port->link_irq); err_free_port_pcpu: free_percpu(port->pcpu); err_free_txq_pcpu: @@ -7683,13 +11032,9 @@ free_percpu(port->txqs[i]->pcpu); err_free_stats: free_percpu(port->stats); -err_free_irq: - if (port->link_irq) - irq_dispose_mapping(port->link_irq); err_deinit_qvecs: mvpp2_queue_vectors_deinit(port); err_free_netdev: - of_node_put(phy_node); free_netdev(dev); return err; } @@ -7699,8 +11044,13 @@ { int i; +#ifdef CONFIG_MVPP2_FBX_FF + unregister_netdevice_notifier(&port->ff_notifier); +#endif + unregister_netdev(port->dev); - of_node_put(port->phy_node); + if (port->phylink) + phylink_destroy(port->phylink); free_percpu(port->pcpu); free_percpu(port->stats); for (i = 0; i < port->ntxqs; i++) @@ -7751,9 +11101,9 @@ for (port = 0; port < MVPP2_MAX_PORTS; port++) { mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), - MVPP2_RX_FIFO_PORT_DATA_SIZE); + MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB); mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), - MVPP2_RX_FIFO_PORT_ATTR_SIZE); + MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB); } mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, @@ -7761,6 +11111,60 @@ mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); } +static void mvpp22_rx_fifo_init(struct mvpp2 *priv) +{ + int port; + + /* The FIFO size parameters are set depending on the maximum speed a + * given port can handle: + * - Port 0: 10Gbps + * - Port 1: 2.5Gbps + * - Ports 2 and 3: 1Gbps + */ + + mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(0), + MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB); + mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(0), + MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB); + + mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(1), + MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB); + mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(1), + MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB); + + for (port = 2; port < MVPP2_MAX_PORTS; port++) { + mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), + MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB); + mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), + MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB); + } + + mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, + MVPP2_RX_FIFO_PORT_MIN_PKT); + mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); +} + +/* Initialize Tx FIFO's: the total FIFO size is 19kB on PPv2.2 and 10G + * interfaces must have a Tx FIFO size of 10kB. As only port 0 can do 10G, + * configure its Tx FIFO size to 10kB and the others ports Tx FIFO size to 3kB. + */ +static void mvpp22_tx_fifo_init(struct mvpp2 *priv) +{ + int port, size, thrs; + + for (port = 0; port < MVPP2_MAX_PORTS; port++) { + if (port == 0) { + size = MVPP22_TX_FIFO_DATA_SIZE_10KB; + thrs = MVPP2_TX_FIFO_THRESHOLD_10KB; + } else { + size = MVPP22_TX_FIFO_DATA_SIZE_3KB; + thrs = MVPP2_TX_FIFO_THRESHOLD_3KB; + } + mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size); + mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), thrs); + } +} + static void mvpp2_axi_init(struct mvpp2 *priv) { u32 val, rdval, wrval; @@ -7856,8 +11260,13 @@ return err; } - /* Rx Fifo Init */ + /* Fifo Init */ + if (priv->hw_version == MVPP21) { mvpp2_rx_fifo_init(priv); + } else { + mvpp22_rx_fifo_init(priv); + mvpp22_tx_fifo_init(priv); + } if (priv->hw_version == MVPP21) writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT, @@ -7889,9 +11298,13 @@ struct mvpp2 *priv; struct resource *res; void __iomem *base; - int port_count, i; + int i; int err; +#ifdef CONFIG_MVPP2_FBX_FF + ff_init(&pdev->dev); +#endif + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; @@ -7904,6 +11317,17 @@ if (IS_ERR(base)) return PTR_ERR(base); +#ifdef CONFIG_MVPP2_FBX_FF + if (res->start == 0xf2000000) { + priv->id = 0; + } else if (res->start == 0xf4000000) { + priv->id = 1; + } else { + WARN(1, "unknown mvpp2 unit for fastpath: %llx\n", + res->start); + } +#endif + if (priv->hw_version == MVPP21) { res = platform_get_resource(pdev, IORESOURCE_MEM, 1); priv->lms_base = devm_ioremap_resource(&pdev->dev, res); @@ -7927,6 +11351,8 @@ priv->sysctrl_base = NULL; } + mvpp2_setup_bm_pool(); + for (i = 0; i < MVPP2_MAX_THREADS; i++) { u32 addr_space_sz; @@ -7984,9 +11410,24 @@ priv->tclk = clk_get_rate(priv->pp_clk); if (priv->hw_version == MVPP22) { - err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(40)); + /* If dma_mask points to coherent_dma_mask, setting both will + * override the value of the other. This is problematic as the + * PPv2 driver uses a 32-bit-mask for coherent accesses (txq, + * rxq, bm) and a 40-bit mask for all other accesses. + */ + if (pdev->dev.dma_mask == &pdev->dev.coherent_dma_mask) { + pdev->dev.dma_mask = kzalloc(sizeof(*pdev->dev.dma_mask), + GFP_KERNEL); + if (!pdev->dev.dma_mask) { + err = -ENOMEM; + goto err_mg_clk; + } + } + + err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK); if (err) goto err_mg_clk; + /* Sadly, the BM pools all share the same register to * store the high 32 bits of their address. So they * must all have the same high 32 bits, which forces @@ -7997,26 +11438,31 @@ goto err_mg_clk; } + /* Assign the reserved memory region to the device for DMA allocations, + * if a memory-region phandle is found. + */ + of_reserved_mem_device_init_by_idx(&pdev->dev, pdev->dev.of_node, 0); + /* Initialize network controller */ err = mvpp2_init(pdev, priv); if (err < 0) { dev_err(&pdev->dev, "failed to initialize controller\n"); - goto err_mg_clk; + goto err_mem_device; } - port_count = of_get_available_child_count(dn); - if (port_count == 0) { + priv->port_count = of_get_available_child_count(dn); + if (priv->port_count == 0) { dev_err(&pdev->dev, "no ports enabled\n"); err = -ENODEV; - goto err_mg_clk; + goto err_mem_device; } - priv->port_list = devm_kcalloc(&pdev->dev, port_count, + priv->port_list = devm_kcalloc(&pdev->dev, priv->port_count, sizeof(*priv->port_list), GFP_KERNEL); if (!priv->port_list) { err = -ENOMEM; - goto err_mg_clk; + goto err_mem_device; } /* Initialize ports */ @@ -8024,13 +11470,38 @@ for_each_available_child_of_node(dn, port_node) { err = mvpp2_port_probe(pdev, port_node, priv, i); if (err < 0) - goto err_mg_clk; + goto err_port_probe; i++; } + /* Statistics must be gathered regularly because some of them (like + * packets counters) are 32-bit registers and could overflow quite + * quickly. For instance, a 10Gb link used at full bandwidth with the + * smallest packets (64B) will overflow a 32-bit counter in less than + * 30 seconds. Then, use a workqueue to fill 64-bit counters. + */ + snprintf(priv->queue_name, sizeof(priv->queue_name), + "stats-wq-%s%s", netdev_name(priv->port_list[0]->dev), + priv->port_count > 1 ? "+" : ""); + priv->stats_queue = create_singlethread_workqueue(priv->queue_name); + if (!priv->stats_queue) { + err = -ENOMEM; + goto err_mg_clk; + } + platform_set_drvdata(pdev, priv); return 0; +err_port_probe: + i = 0; + for_each_available_child_of_node(dn, port_node) { + if (priv->port_list[i]) + mvpp2_port_remove(priv->port_list[i]); + ++i; + } + +err_mem_device: + of_reserved_mem_device_release(&pdev->dev); err_mg_clk: clk_disable_unprepare(priv->axi_clk); if (priv->hw_version == MVPP22) @@ -8049,9 +11520,14 @@ struct device_node *port_node; int i = 0; + flush_workqueue(priv->stats_queue); + destroy_workqueue(priv->stats_queue); + for_each_available_child_of_node(dn, port_node) { - if (priv->port_list[i]) + if (priv->port_list[i]) { + mutex_destroy(&priv->port_list[i]->gather_stats_lock); mvpp2_port_remove(priv->port_list[i]); + } i++; } diff -ruw linux-4.14.127/drivers/net/ppp/ppp_generic.c linux-4.14.127-fbx/drivers/net/ppp/ppp_generic.c --- linux-4.14.127/drivers/net/ppp/ppp_generic.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/net/ppp/ppp_generic.c 2019-02-15 14:29:40.274649446 +0100 @@ -177,6 +177,7 @@ struct ppp *ppp; /* ppp unit we're connected to */ struct net *chan_net; /* the net channel belongs to */ struct list_head clist; /* link in list of channels per unit */ + int stopped; /* channel is stopped */ rwlock_t upl; /* protects `ppp' */ #ifdef CONFIG_PPP_MULTILINK u8 avail; /* flag used in multilink stuff */ @@ -1429,11 +1430,29 @@ ppp_send_frame(ppp, skb); /* If there's no work left to do, tell the core net code that we can accept some more. */ - if (!ppp->xmit_pending && !skb_peek(&ppp->file.xq)) + if (!ppp->xmit_pending && !skb_peek(&ppp->file.xq)) { + /* only enable net queue if at least one + * channel is not stopped */ + struct list_head *list; + struct channel *pch; + bool need_wake; + + list = &ppp->channels; + need_wake = false; + while ((list = list->next) != &ppp->channels) { + pch = list_entry(list, struct channel, clist); + if (!pch->stopped) { + need_wake = true; + break; + } + } + + if (need_wake) netif_wake_queue(ppp->dev); else netif_stop_queue(ppp->dev); } + } ppp_xmit_unlock(ppp); } @@ -2695,10 +2714,24 @@ if (!pch) return; + pch->stopped = 0; ppp_channel_push(pch); } /* + * Callback from a channel when it want to prevent further transmit on it + */ +void +ppp_output_stop(struct ppp_channel *chan) +{ + struct channel *pch = chan->ppp; + + if (pch == 0) + return; + pch->stopped = 1; +} + +/* * Compression control. */ @@ -3295,6 +3328,7 @@ EXPORT_SYMBOL(ppp_input); EXPORT_SYMBOL(ppp_input_error); EXPORT_SYMBOL(ppp_output_wakeup); +EXPORT_SYMBOL(ppp_output_stop); EXPORT_SYMBOL(ppp_register_compressor); EXPORT_SYMBOL(ppp_unregister_compressor); MODULE_LICENSE("GPL"); diff -ruw linux-4.14.127/drivers/net/ppp/pptp.c linux-4.14.127-fbx/drivers/net/ppp/pptp.c --- linux-4.14.127/drivers/net/ppp/pptp.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/net/ppp/pptp.c 2019-05-10 11:02:37.364383264 +0200 @@ -368,6 +368,7 @@ po = lookup_chan(htons(header->call_id), iph->saddr); if (po) { skb_dst_drop(skb); + skb->mark = 0; nf_reset(skb); return sk_receive_skb(sk_pppox(po), skb, 0); } diff -ruw linux-4.14.127/drivers/net/tun.c linux-4.14.127-fbx/drivers/net/tun.c --- linux-4.14.127/drivers/net/tun.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/net/tun.c 2019-05-10 11:02:37.368383281 +0200 @@ -75,6 +75,10 @@ #include #include #include +#include +#include +#include +#include #include @@ -188,6 +192,31 @@ unsigned long updated; }; +/* + * smalltun definitions + */ +#define SMALLTUN_MAGIC 0x6660 +#define SMALLTUN_VERSION 0x1 + +#define TYPE_MASK 0xf +#define TYPE_CLT (1 << 3) + +#define TYPE_TRIGGER 0x0 +#define TYPE_CHALLENGE 0x1 +#define TYPE_CLIENT_HELLO 0x2 +#define TYPE_SERVER_HELLO 0x3 + +#define TYPE_CLT_DATA (TYPE_CLT | 0x0) +#define TYPE_CLT_GET_PARAMS (TYPE_CLT | 0x1) +#define TYPE_CLT_PARAMS (TYPE_CLT | 0x2) + +struct smalltun_pkt_hdr { + u16 magic; + u8 version; + u8 flag_type; + u8 data[0]; +}; + #define TUN_NUM_FLOW_ENTRIES 1024 /* Since the socket were moved to tun_file, to preserve the behavior of persist @@ -201,6 +230,11 @@ kuid_t owner; kgid_t group; + struct smalltun_fp smalltun_fps[4]; + unsigned int smalltun_valid_count; + unsigned int smalltun_valid[4]; + struct rtable *smalltun_rt_cache[4]; + struct net_device *dev; netdev_features_t set_features; #define TUN_USER_FEATURES (NETIF_F_HW_CSUM|NETIF_F_TSO_ECN|NETIF_F_TSO| \ @@ -853,6 +887,181 @@ return 0; } +static int smalltun_is_fastpath(struct tun_struct *tun, + struct sk_buff *skb) +{ + struct iphdr *iph; + const struct smalltun_fp *fp; + struct rtable **prt_cache, *rt_cache; + struct flowi4 fl; + bool match; + size_t i; + + if (!tun->smalltun_valid_count) + return 0; + + if (skb->protocol != htons(ETH_P_IP)) + return 0; + + if (!pskb_may_pull(skb, sizeof(struct iphdr))) + return 0; + + iph = ip_hdr(skb); + + /* lookup smalltun fastpath */ + fp = NULL; + rt_cache = NULL; + for (i = 0; i < ARRAY_SIZE(tun->smalltun_fps); i++) { + if (!tun->smalltun_valid[i]) + continue; + + if (iph->daddr == tun->smalltun_fps[i].inner_dst) { + fp = &tun->smalltun_fps[i]; + prt_cache = &tun->smalltun_rt_cache[i]; + break; + } + } + + if (!fp) + return 0; + + if (fp->af != AF_INET) { + /* FIXME: implement IPv6 transport */ + return 0; + } + + if (!pskb_may_pull(skb, iph->ihl * 4)) + return 0; + + match = false; + for (i = 0; i < fp->rule_count; i++) { + const struct smalltun_rule *r = &fp->rules[i]; + unsigned int sport, dport; + + if (iph->protocol != r->proto) + continue; + + switch (iph->protocol) { + case IPPROTO_UDP: + { + const struct udphdr *udp; + udp = (struct udphdr *)((u8 *)iph + (iph->ihl << 2)); + sport = ntohs(udp->source); + dport = ntohs(udp->dest); + break; + } + case IPPROTO_TCP: + { + const struct tcphdr *tcp; + tcp = (struct tcphdr *)((u8 *)iph + (iph->ihl << 2)); + sport = ntohs(tcp->source); + dport = ntohs(tcp->dest); + break; + } + default: + match = true; + break; + } + + if (r->src_port_start && r->src_port_end) { + if (sport < ntohs(r->src_port_start) || + sport > ntohs(r->src_port_end)) + continue; + } + + if (r->dst_port_start && r->dst_port_end) { + if (dport < ntohs(r->dst_port_start) || + dport > ntohs(r->dst_port_end)) + continue; + } + match = true; + } + + if (!match) + return 0; + + if (fp->af == AF_INET) { + struct iphdr *oiph; + struct udphdr *oudph; + struct smalltun_pkt_hdr *pkt; + unsigned int payload_len; + + payload_len = skb->len; + + if (skb_cow_head(skb, + sizeof (struct iphdr) + + sizeof (struct udphdr) + + sizeof (struct smalltun_pkt_hdr))) + return 0; + + pkt = skb_push(skb, sizeof (struct smalltun_pkt_hdr)); + oudph = skb_push(skb, sizeof (struct udphdr)); + skb_reset_transport_header(skb); + oiph = skb_push(skb, sizeof (struct iphdr)); + skb_reset_network_header(skb); + + /* ip */ + oiph->version = 4; + oiph->tos = 0; + oiph->id = 0; + oiph->ihl = 5; + oiph->frag_off = 0; + oiph->ttl = 64; + oiph->protocol = IPPROTO_UDP; + memcpy(&oiph->saddr, fp->outer_src, 4); + memcpy(&oiph->daddr, fp->outer_dst, 4); + + /* udp */ + oudph->source = fp->outer_src_port; + oudph->dest = fp->outer_dst_port; + oudph->len = htons(payload_len + sizeof (*oudph) + + sizeof (*pkt)); + oudph->check = 0; + + /* smalltun */ + pkt->magic = htons(SMALLTUN_MAGIC); + pkt->version = SMALLTUN_VERSION; + pkt->flag_type = TYPE_CLT_DATA; + + memset(&fl, 0x00, sizeof (fl)); + memcpy(&fl.saddr, fp->outer_src, 4); + memcpy(&fl.daddr, fp->outer_dst, 4); + + if (*prt_cache && (*prt_cache)->dst.obsolete > 0) { + rt_cache = *prt_cache; + *prt_cache = NULL; + ip_rt_put(rt_cache); + } + + rt_cache = *prt_cache; + if (!rt_cache) { + rt_cache = ip_route_output_key(&init_net, &fl); + if (IS_ERR(rt_cache)) { + pr_err("ip_route_output_key(%pI4): %li\n", + &fl.daddr, PTR_ERR(rt_cache)); + return 0; + } + + if (!rt_cache->dst.dev) { + pr_err("ip_route_output_key(%pI4): no dev\n", + &fl.daddr); + return 0; + } + + *prt_cache = rt_cache; + } + + skb_dst_set(skb, dst_clone(&rt_cache->dst)); + skb->dev = skb_dst(skb)->dev; + ip_local_out(&init_net, NULL, skb); + return 1; + } + + /* find route */ + + return 0; +} + /* Net device start xmit */ static netdev_tx_t tun_net_xmit(struct sk_buff *skb, struct net_device *dev) { @@ -911,6 +1120,11 @@ */ skb_orphan(skb); + if (smalltun_is_fastpath(tun, skb)) { + rcu_read_unlock(); + return NETDEV_TX_OK; + } + nf_reset(skb); if (skb_array_produce(&tfile->tx_array, skb)) @@ -2552,6 +2766,100 @@ ret = 0; break; + case TUNSMALLTUNSETFP: + { + struct smalltun_fp fp; + unsigned int i; + int free_idx; + + ret = -EFAULT; + if (copy_from_user(&fp, argp, sizeof(fp))) + break; + + /* look for duplicate */ + ret = 0; + free_idx = -1; + for (i = 0; i < ARRAY_SIZE(tun->smalltun_fps); i++) { + if (!tun->smalltun_valid[i]) { + if (free_idx == -1) + free_idx = i; + continue; + } + + if (fp.inner_src == tun->smalltun_fps[i].inner_src && + fp.inner_dst == tun->smalltun_fps[i].inner_dst) { + ret = -EEXIST; + break; + } + } + + if (ret) + break; + + if (free_idx == -1) { + ret = -ENOSPC; + break; + } + + memcpy(&tun->smalltun_fps[free_idx], &fp, sizeof (fp)); + tun->smalltun_valid[free_idx] = 1; + tun->smalltun_valid_count++; + tun_debug(KERN_INFO, tun, "new fp rule for %pI4 <=> %pI4 (%u rules)\n", + &fp.inner_src, + &fp.inner_dst, + fp.rule_count); + + if (fp.af == AF_INET) { + tun_debug(KERN_INFO, tun, "outer %pI4:%u <=> %pI4:%u\n", + fp.outer_src, + ntohs(fp.outer_src_port), + fp.outer_dst, + ntohs(fp.outer_dst_port)); + } else { + tun_debug(KERN_INFO, tun, "outer %pI6:%u <=> %pI6:%u\n", + fp.outer_src, + ntohs(fp.outer_src_port), + fp.outer_dst, + ntohs(fp.outer_dst_port)); + } + break; + } + + case TUNSMALLTUNDELFP: + { + struct smalltun_fp fp; + unsigned int i; + + ret = -EFAULT; + if (copy_from_user(&fp, argp, sizeof(fp))) + break; + + /* lookup */ + ret = -ENOENT; + for (i = 0; i < ARRAY_SIZE(tun->smalltun_fps); i++) { + if (fp.inner_src == tun->smalltun_fps[i].inner_src && + fp.inner_dst == tun->smalltun_fps[i].inner_dst) { + ret = 0; + break; + } + } + + if (ret) + break; + + tun->smalltun_valid[i] = 0; + tun->smalltun_valid_count--; + if (tun->smalltun_rt_cache[i]) { + ip_rt_put(tun->smalltun_rt_cache[i]); + tun->smalltun_rt_cache[i] = NULL; + } + + tun_debug(KERN_INFO, tun, "removed fp rule for %pI4 <=> %pI4\n", + &fp.inner_src, + &fp.inner_dst); + break; + } + default: ret = -EINVAL; break; diff -ruw linux-4.14.127/drivers/net/usb/usbnet.c linux-4.14.127-fbx/drivers/net/usb/usbnet.c --- linux-4.14.127/drivers/net/usb/usbnet.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/net/usb/usbnet.c 2019-07-22 10:44:47.978827491 +0200 @@ -460,7 +460,7 @@ set_bit (work, &dev->flags); if (!schedule_work (&dev->kevent)) { if (net_ratelimit()) - netdev_err(dev->net, "kevent %d may have been dropped\n", work); + netdev_dbg(dev->net, "kevent %d may have been dropped\n", work); } else { netdev_dbg(dev->net, "kevent %d scheduled\n", work); } diff -ruw linux-4.14.127/drivers/net/wireless/ath/Kconfig linux-4.14.127-fbx/drivers/net/wireless/ath/Kconfig --- linux-4.14.127/drivers/net/wireless/ath/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/net/wireless/ath/Kconfig 2019-02-15 14:29:40.318649621 +0100 @@ -36,6 +36,9 @@ This option enables tracepoints for atheros wireless drivers. Currently, ath9k makes use of this facility. +config ATH_REG_IGNORE + bool "ignore all eeprom regulation" + config ATH_REG_DYNAMIC_USER_REG_HINTS bool "Atheros dynamic user regulatory hints" depends on CFG80211_CERTIFICATION_ONUS diff -ruw linux-4.14.127/drivers/net/wireless/ath/ath.h linux-4.14.127-fbx/drivers/net/wireless/ath/ath.h --- linux-4.14.127/drivers/net/wireless/ath/ath.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/net/wireless/ath/ath.h 2019-02-15 14:29:40.318649621 +0100 @@ -186,6 +186,8 @@ int last_rssi; struct ieee80211_supported_band sbands[NUM_NL80211_BANDS]; + + int dfs_pulse_valid_diff_ts; }; static inline const struct ath_ps_ops *ath_ps_ops(struct ath_common *common) diff -ruw linux-4.14.127/drivers/net/wireless/ath/ath10k/core.c linux-4.14.127-fbx/drivers/net/wireless/ath/ath10k/core.c --- linux-4.14.127/drivers/net/wireless/ath/ath10k/core.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/net/wireless/ath/ath10k/core.c 2019-02-15 14:29:40.318649621 +0100 @@ -519,7 +519,7 @@ dir = "."; snprintf(filename, sizeof(filename), "%s/%s", dir, file); - ret = request_firmware(&fw, filename, ar->dev); + ret = request_firmware_nowarn(&fw, filename, ar->dev); ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot fw request '%s': %d\n", filename, ret); @@ -974,6 +974,7 @@ static int ath10k_fetch_cal_file(struct ath10k *ar) { char filename[100]; + unsigned int i; /* pre-cal--.bin */ scnprintf(filename, sizeof(filename), "pre-cal-%s-%s.bin", @@ -987,6 +988,11 @@ scnprintf(filename, sizeof(filename), "cal-%s-%s.bin", ath10k_bus_str(ar->hif.bus), dev_name(ar->dev)); + for (i = 0; filename[i]; i++) { + if (filename[i] == ':') + filename[i] = '_'; + } + ar->cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename); if (IS_ERR(ar->cal_file)) /* calibration file is optional, don't print any warnings */ @@ -1719,6 +1725,7 @@ switch (ar->state) { case ATH10K_STATE_ON: + case ATH10K_STATE_PRE_ON: ar->state = ATH10K_STATE_RESTARTING; ath10k_halt(ar); ath10k_scan_finish(ar); diff -ruw linux-4.14.127/drivers/net/wireless/ath/ath10k/core.h linux-4.14.127-fbx/drivers/net/wireless/ath/ath10k/core.h --- linux-4.14.127/drivers/net/wireless/ath/ath10k/core.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/net/wireless/ath/ath10k/core.h 2019-03-18 16:21:05.296370861 +0100 @@ -364,11 +364,11 @@ struct rate_info txrate; struct work_struct update_wk; + u64 rx_duration; #ifdef CONFIG_MAC80211_DEBUGFS /* protected by conf_mutex */ bool aggr_mode; - u64 rx_duration; #endif }; @@ -476,6 +476,7 @@ bool fw_stats_done; unsigned long htt_stats_mask; + unsigned long reset_htt_stats; struct delayed_work htt_stats_dwork; struct ath10k_dfs_stats dfs_stats; struct ath_dfs_pool_stats dfs_pool_stats; @@ -488,16 +489,17 @@ /* protected by conf_mutex */ u64 fw_dbglog_mask; u32 fw_dbglog_level; - u32 pktlog_filter; u32 reg_addr; u32 nf_cal_period; void *cal_data; + u32 burst_dur[4]; struct ath10k_fw_crash_data *fw_crash_data; }; enum ath10k_state { ATH10K_STATE_OFF = 0, + ATH10K_STATE_PRE_ON, ATH10K_STATE_ON, /* When doing firmware recovery the device is first powered down. @@ -927,6 +929,8 @@ struct work_struct register_work; struct work_struct restart_work; + struct work_struct powerup_work; + bool powerup_pending; /* cycle count is reported twice for each visited channel during scan. * access protected by data_lock @@ -960,6 +964,7 @@ } spectral; #endif + u32 pktlog_filter; struct { /* protected by conf_mutex */ struct ath10k_fw_components utf_mode_fw; diff -ruw linux-4.14.127/drivers/net/wireless/ath/ath10k/debug.c linux-4.14.127-fbx/drivers/net/wireless/ath/ath10k/debug.c --- linux-4.14.127/drivers/net/wireless/ath/ath10k/debug.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/net/wireless/ath/ath10k/debug.c 2019-03-18 16:21:05.296370861 +0100 @@ -1149,7 +1149,7 @@ cookie = get_jiffies_64(); ret = ath10k_htt_h2t_stats_req(&ar->htt, ar->debug.htt_stats_mask, - cookie); + ar->debug.reset_htt_stats, cookie); if (ret) { ath10k_warn(ar, "failed to send htt stats request: %d\n", ret); return ret; @@ -1958,14 +1958,14 @@ ret); } - if (ar->debug.pktlog_filter) { + if (ar->pktlog_filter) { ret = ath10k_wmi_pdev_pktlog_enable(ar, - ar->debug.pktlog_filter); + ar->pktlog_filter); if (ret) /* not serious */ ath10k_warn(ar, "failed to enable pktlog filter %x: %d\n", - ar->debug.pktlog_filter, ret); + ar->pktlog_filter, ret); } else { ret = ath10k_wmi_pdev_pktlog_disable(ar); if (ret) @@ -2105,12 +2105,12 @@ mutex_lock(&ar->conf_mutex); if (ar->state != ATH10K_STATE_ON) { - ar->debug.pktlog_filter = filter; + ar->pktlog_filter = filter; ret = count; goto out; } - if (filter == ar->debug.pktlog_filter) { + if (filter == ar->pktlog_filter) { ret = count; goto out; } @@ -2119,7 +2119,7 @@ ret = ath10k_wmi_pdev_pktlog_enable(ar, filter); if (ret) { ath10k_warn(ar, "failed to enable pktlog filter %x: %d\n", - ar->debug.pktlog_filter, ret); + ar->pktlog_filter, ret); goto out; } } else { @@ -2130,7 +2130,7 @@ } } - ar->debug.pktlog_filter = filter; + ar->pktlog_filter = filter; ret = count; out: @@ -2147,7 +2147,7 @@ mutex_lock(&ar->conf_mutex); len = scnprintf(buf, sizeof(buf) - len, "%08x\n", - ar->debug.pktlog_filter); + ar->pktlog_filter); mutex_unlock(&ar->conf_mutex); return simple_read_from_buffer(ubuf, count, ppos, buf, len); @@ -2408,6 +2408,118 @@ .llseek = default_llseek, }; +static ssize_t ath10k_write_reset_htt_stats(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath10k *ar = file->private_data; + unsigned long reset; + int ret; + + ret = kstrtoul_from_user(user_buf, count, 0, &reset); + if (ret) + return ret; + + if (reset == 0 || reset > 0x1ffff) + return -EINVAL; + + mutex_lock(&ar->conf_mutex); + + ar->debug.reset_htt_stats = reset; + + ret = ath10k_debug_htt_stats_req(ar); + if (ret) + goto out; + + ar->debug.reset_htt_stats = 0; + ret = count; + +out: + mutex_unlock(&ar->conf_mutex); + return ret; +} + +static const struct file_operations fops_reset_htt_stats = { + .write = ath10k_write_reset_htt_stats, + .owner = THIS_MODULE, + .open = simple_open, + .llseek = default_llseek, +}; + + +static ssize_t ath10k_write_burst_dur(struct file *file, const char __user *user_buf, + size_t count, loff_t *ppos) +{ + + struct ath10k *ar = file->private_data; + u32 dur[4]; + int ret; + int ac; + char buf[128]; + + simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, user_buf, count); + + /* make sure that buf is null terminated */ + buf[sizeof(buf) - 1] = 0; + + ret = sscanf(buf, "%u %u %u %u", &dur[0], &dur[1], &dur[2], &dur[3]); + + if (!ret) + return -EINVAL; + + mutex_lock(&ar->conf_mutex); + + if (ar->state != ATH10K_STATE_ON && + ar->state != ATH10K_STATE_RESTARTED) { + ret = -ENETDOWN; + goto exit; + } + + for (ac = 0; ac < 4; ac++) { + if (dur[ac] < MIN_BURST_DUR || dur[ac] > MAX_BURST_DUR) { + ret = -EINVAL; + goto exit; + } + + ret = ath10k_wmi_pdev_set_param(ar, ar->wmi.pdev_param->aggr_burst, + (SM(ac, ATH10K_AGGR_BURST_AC) | + SM(dur[ac], ATH10K_AGGR_BURST_DUR))); + if (ret) { + ath10k_warn(ar, "failed to set aggr burst duration for ac %d: %d\n", ac, ret); + goto exit; + } + ar->debug.burst_dur[ac] = dur[ac]; + } + + ret = count; + +exit: + mutex_unlock(&ar->conf_mutex); + return ret; +} + +static ssize_t ath10k_read_burst_dur(struct file *file, char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath10k *ar = file->private_data; + int len = 0; + char buf[128]; + + len = scnprintf(buf, sizeof(buf) - len, "%u %u %u %u\n", + ar->debug.burst_dur[0], ar->debug.burst_dur[1], + ar->debug.burst_dur[2], ar->debug.burst_dur[3]); + + return simple_read_from_buffer(user_buf, count, ppos, buf, len); +} + +static const struct file_operations fops_burst_dur = { + .read = ath10k_read_burst_dur, + .write = ath10k_write_burst_dur, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + int ath10k_debug_create(struct ath10k *ar) { ar->debug.fw_crash_data = vzalloc(sizeof(*ar->debug.fw_crash_data)); @@ -2501,6 +2613,9 @@ debugfs_create_file("nf_cal_period", 0600, ar->debug.debugfs_phy, ar, &fops_nf_cal_period); + debugfs_create_file("burst_dur", S_IRUSR | S_IWUSR, + ar->debug.debugfs_phy, ar, &fops_burst_dur); + if (IS_ENABLED(CONFIG_ATH10K_DFS_CERTIFIED)) { debugfs_create_file("dfs_simulate_radar", 0200, ar->debug.debugfs_phy, ar, &fops_simulate_radar); @@ -2533,6 +2648,10 @@ debugfs_create_file("fw_checksums", 0400, ar->debug.debugfs_phy, ar, &fops_fw_checksums); + debugfs_create_file("reset_htt_stats", 0200, ar->debug.debugfs_phy, ar, + &fops_reset_htt_stats); + + return 0; } diff -ruw linux-4.14.127/drivers/net/wireless/ath/ath10k/debug.h linux-4.14.127-fbx/drivers/net/wireless/ath/ath10k/debug.h --- linux-4.14.127/drivers/net/wireless/ath/ath10k/debug.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/net/wireless/ath/ath10k/debug.h 2019-03-18 16:21:05.296370861 +0100 @@ -51,7 +51,8 @@ ATH10K_PKTLOG_RCFIND = 0x000000004, ATH10K_PKTLOG_RCUPDATE = 0x000000008, ATH10K_PKTLOG_DBG_PRINT = 0x000000010, - ATH10K_PKTLOG_ANY = 0x00000001f, + ATH10K_PKTLOG_PEER_STATS = 0x000000040, + ATH10K_PKTLOG_ANY = 0x00000005f, }; enum ath10k_dbg_aggr_mode { @@ -60,6 +61,21 @@ ATH10K_DBG_AGGR_MODE_MAX, }; +/* Types of packet log events */ +enum ath_pktlog_type { + ATH_PKTLOG_TYPE_TX_CTRL = 1, + ATH_PKTLOG_TYPE_TX_STAT, +}; + +struct ath10k_pktlog_hdr { + __le16 flags; + __le16 missed_cnt; + __le16 log_type; /* Type of log information foll this header */ + __le16 size; /* Size of variable length log information in bytes */ + __le32 timestamp; + u8 payload[0]; +} __packed; + /* FIXME: How to calculate the buffer size sanely? */ #define ATH10K_FW_STATS_BUF_SIZE (1024 * 1024) @@ -69,6 +85,15 @@ __printf(2, 3) void ath10k_err(struct ath10k *ar, const char *fmt, ...); __printf(2, 3) void ath10k_warn(struct ath10k *ar, const char *fmt, ...); +#define ATH10K_AGGR_BURST_AC_MASK 0xff000000 +#define ATH10K_AGGR_BURST_AC_LSB 24 +#define ATH10K_AGGR_BURST_DUR_MASK 0x00ffffff +#define ATH10K_AGGR_BURST_DUR_LSB 0 + +/* burst duration in usec */ +#define MIN_BURST_DUR 0 +#define MAX_BURST_DUR 8000 + void ath10k_debug_print_hwfw_info(struct ath10k *ar); void ath10k_debug_print_board_info(struct ath10k *ar); void ath10k_debug_print_boot_info(struct ath10k *ar); @@ -190,9 +215,6 @@ struct ieee80211_sta *sta, struct dentry *dir); void ath10k_sta_update_rx_duration(struct ath10k *ar, struct ath10k_fw_stats *stats); -void ath10k_sta_statistics(struct ieee80211_hw *hw, struct ieee80211_vif *vif, - struct ieee80211_sta *sta, - struct station_info *sinfo); #else static inline void ath10k_sta_update_rx_duration(struct ath10k *ar, diff -ruw linux-4.14.127/drivers/net/wireless/ath/ath10k/htt.h linux-4.14.127-fbx/drivers/net/wireless/ath/ath10k/htt.h --- linux-4.14.127/drivers/net/wireless/ath/ath10k/htt.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/net/wireless/ath/ath10k/htt.h 2019-03-18 16:21:05.296370861 +0100 @@ -1497,6 +1497,23 @@ u8 payload[0]; } __packed; +#define ATH10K_10_2_TX_STATS_OFFSET 136 +#define PEER_STATS_FOR_NO_OF_PPDUS 4 + +struct ath10k_10_2_peer_tx_stats { + u8 ratecode[PEER_STATS_FOR_NO_OF_PPDUS]; + u8 success_pkts[PEER_STATS_FOR_NO_OF_PPDUS]; + __le16 success_bytes[PEER_STATS_FOR_NO_OF_PPDUS]; + u8 retry_pkts[PEER_STATS_FOR_NO_OF_PPDUS]; + __le16 retry_bytes[PEER_STATS_FOR_NO_OF_PPDUS]; + u8 failed_pkts[PEER_STATS_FOR_NO_OF_PPDUS]; + __le16 failed_bytes[PEER_STATS_FOR_NO_OF_PPDUS]; + u8 flags[PEER_STATS_FOR_NO_OF_PPDUS]; + __le32 tx_duration; + u8 tx_ppdu_cnt; + u8 peer_id; +} __packed; + union htt_rx_pn_t { /* WEP: 24-bit PN */ u32 pn24; @@ -1802,7 +1819,8 @@ void ath10k_htt_htc_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb); bool ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb); int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt); -int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie); +int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u8 reset_mask, + u64 cookie); int ath10k_htt_send_frag_desc_bank_cfg(struct ath10k_htt *htt); int ath10k_htt_send_rx_ring_cfg_ll(struct ath10k_htt *htt); int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt, diff -ruw linux-4.14.127/drivers/net/wireless/ath/ath10k/htt_rx.c linux-4.14.127-fbx/drivers/net/wireless/ath/ath10k/htt_rx.c --- linux-4.14.127/drivers/net/wireless/ath/ath10k/htt_rx.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/net/wireless/ath/ath10k/htt_rx.c 2019-02-15 14:29:40.322649636 +0100 @@ -605,6 +605,9 @@ #define GROUP_ID_IS_SU_MIMO(x) ((x) == 0 || (x) == 63) +static const u8 ath10k_bw_to_mac80211[] = { RATE_INFO_BW_20, RATE_INFO_BW_40, + RATE_INFO_BW_80, RATE_INFO_BW_160 }; + static void ath10k_htt_rx_h_rates(struct ath10k *ar, struct ieee80211_rx_status *status, struct htt_rx_desc *rxd) @@ -707,23 +710,7 @@ if (sgi) status->enc_flags |= RX_ENC_FLAG_SHORT_GI; - switch (bw) { - /* 20MHZ */ - case 0: - break; - /* 40MHZ */ - case 1: - status->bw = RATE_INFO_BW_40; - break; - /* 80MHZ */ - case 2: - status->bw = RATE_INFO_BW_80; - break; - case 3: - status->bw = RATE_INFO_BW_160; - break; - } - + status->bw = ath10k_bw_to_mac80211[bw]; status->encoding = RX_ENC_VHT; break; default: @@ -2369,7 +2356,7 @@ arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; arsta->txrate.nss = txrate.nss; - arsta->txrate.bw = txrate.bw + RATE_INFO_BW_20; + arsta->txrate.bw = ath10k_bw_to_mac80211[txrate.bw]; } static void ath10k_htt_fetch_peer_stats(struct ath10k *ar, @@ -2427,6 +2414,62 @@ rcu_read_unlock(); } +static void ath10k_fetch_10_2_tx_stats(struct ath10k *ar, u8 *data) +{ + struct ath10k_pktlog_hdr *hdr = (struct ath10k_pktlog_hdr *)data; + struct ath10k_per_peer_tx_stats *p_tx_stats = &ar->peer_tx_stats; + struct ath10k_10_2_peer_tx_stats *tx_stats; + struct ieee80211_sta *sta; + struct ath10k_peer *peer; + u16 log_type = __le16_to_cpu(hdr->log_type); + u32 peer_id = 0, i; + + if (log_type != ATH_PKTLOG_TYPE_TX_STAT) + return; + + tx_stats = (struct ath10k_10_2_peer_tx_stats *)((hdr->payload) + + ATH10K_10_2_TX_STATS_OFFSET); + + if (!tx_stats->tx_ppdu_cnt) + return; + + peer_id = tx_stats->peer_id; + + rcu_read_lock(); + spin_lock_bh(&ar->data_lock); + peer = ath10k_peer_find_by_id(ar, peer_id); + if (!peer) { + ath10k_warn(ar, "Invalid peer id %d in peer stats buffer\n", + peer_id); + goto out; + } + + sta = peer->sta; + for (i = 0; i < tx_stats->tx_ppdu_cnt; i++) { + p_tx_stats->succ_bytes = + __le16_to_cpu(tx_stats->success_bytes[i]); + p_tx_stats->retry_bytes = + __le16_to_cpu(tx_stats->retry_bytes[i]); + p_tx_stats->failed_bytes = + __le16_to_cpu(tx_stats->failed_bytes[i]); + p_tx_stats->ratecode = tx_stats->ratecode[i]; + p_tx_stats->flags = tx_stats->flags[i]; + p_tx_stats->succ_pkts = tx_stats->success_pkts[i]; + p_tx_stats->retry_pkts = tx_stats->retry_pkts[i]; + p_tx_stats->failed_pkts = tx_stats->failed_pkts[i]; + + ath10k_update_per_peer_tx_stats(ar, sta, p_tx_stats); + } + spin_unlock_bh(&ar->data_lock); + rcu_read_unlock(); + + return; + +out: + spin_unlock_bh(&ar->data_lock); + rcu_read_unlock(); +} + bool ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb) { struct ath10k_htt *htt = &ar->htt; @@ -2544,6 +2587,10 @@ skb->len - offsetof(struct htt_resp, pktlog_msg.payload)); + + if (ath10k_peer_stats_enabled(ar)) + ath10k_fetch_10_2_tx_stats(ar, + resp->pktlog_msg.payload); break; } case HTT_T2H_MSG_TYPE_RX_FLUSH: { diff -ruw linux-4.14.127/drivers/net/wireless/ath/ath10k/htt_tx.c linux-4.14.127-fbx/drivers/net/wireless/ath/ath10k/htt_tx.c --- linux-4.14.127/drivers/net/wireless/ath/ath10k/htt_tx.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/net/wireless/ath/ath10k/htt_tx.c 2019-03-18 16:21:05.300370873 +0100 @@ -502,7 +502,8 @@ return 0; } -int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie) +int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u8 reset_mask, + u64 cookie) { struct ath10k *ar = htt->ar; struct htt_stats_req *req; @@ -529,7 +530,7 @@ * about endian support */ req->upload_types[0] = mask; - req->reset_types[0] = mask; + req->reset_types[0] = reset_mask; req->stat_type = HTT_STATS_REQ_CFG_STAT_TYPE_INVALID; req->cookie_lsb = cpu_to_le32(cookie & 0xffffffff); req->cookie_msb = cpu_to_le32((cookie & 0xffffffff00000000ULL) >> 32); diff -ruw linux-4.14.127/drivers/net/wireless/ath/ath10k/mac.c linux-4.14.127-fbx/drivers/net/wireless/ath/ath10k/mac.c --- linux-4.14.127/drivers/net/wireless/ath/ath10k/mac.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/net/wireless/ath/ath10k/mac.c 2019-02-15 14:29:40.326649652 +0100 @@ -2456,7 +2456,7 @@ const u16 *vht_mcs_mask; u8 ampdu_factor; u8 max_nss, vht_mcs; - int i; + int i, nss160; if (WARN_ON(ath10k_mac_vif_chan(vif, &def))) return; @@ -2516,23 +2516,45 @@ __le16_to_cpu(vht_cap->vht_mcs.tx_highest); arg->peer_vht_rates.tx_mcs_set = ath10k_peer_assoc_h_vht_limit( __le16_to_cpu(vht_cap->vht_mcs.tx_mcs_map), vht_mcs_mask); + arg->peer_bw_rxnss_override = 0; + nss160 = 1; /* 1x1 default config for VHT160 */ + + /* only local 4x4 configuration do support 2x2 for VHT160, + * everything else must use 1x1 + */ - ath10k_dbg(ar, ATH10K_DBG_MAC, "mac vht peer %pM max_mpdu %d flags 0x%x\n", - sta->addr, arg->peer_max_mpdu, arg->peer_flags); + if (ar->cfg_rx_chainmask == 15) + nss160 = arg->peer_num_spatial_streams < 2 ? 1 : 2; - if (arg->peer_vht_rates.rx_max_rate && - (sta->vht_cap.cap & IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_MASK)) { - switch (arg->peer_vht_rates.rx_max_rate) { - case 1560: - /* Must be 2x2 at 160Mhz is all it can do. */ - arg->peer_bw_rxnss_override = 2; - break; - case 780: - /* Can only do 1x1 at 160Mhz (Long Guard Interval) */ - arg->peer_bw_rxnss_override = 1; + /* if peer provides 1x1 nss160 information using max rate + * vht information, we reduce local nss160 to 1x1. + * consider that it has been observed that some client + * devices provide zero here, no matter which transmission + * rate is possible. in that case the local nss configuration + * will be used at maxmimum configuration possible. (see above) + */ + + if (arg->peer_vht_rates.rx_max_rate == 780) + nss160 = 1; + + /* in case if peer is connected with vht160 or vht80+80, + * we need to properly adjust rxnss parameters otherwise + * firmware will raise a assert + */ + switch (arg->peer_phymode) { + case MODE_11AC_VHT80_80: + arg->peer_bw_rxnss_override = BW_NSS_FWCONF_80_80(nss160); + /* fall through */ + case MODE_11AC_VHT160: + arg->peer_bw_rxnss_override |= BW_NSS_FWCONF_160(nss160); + break; + default: break; } - } + + ath10k_dbg(ar, ATH10K_DBG_MAC, "mac vht peer %pM max_mpdu %d flags 0x%x peer_bw_rxnss_override 0x%x\n", + sta->addr, arg->peer_max_mpdu, arg->peer_flags, + arg->peer_bw_rxnss_override); } static void ath10k_peer_assoc_h_qos(struct ath10k *ar, @@ -2684,9 +2706,9 @@ ath10k_peer_assoc_h_crypto(ar, vif, sta, arg); ath10k_peer_assoc_h_rates(ar, vif, sta, arg); ath10k_peer_assoc_h_ht(ar, vif, sta, arg); + ath10k_peer_assoc_h_phymode(ar, vif, sta, arg); ath10k_peer_assoc_h_vht(ar, vif, sta, arg); ath10k_peer_assoc_h_qos(ar, vif, sta, arg); - ath10k_peer_assoc_h_phymode(ar, vif, sta, arg); return 0; } @@ -4409,13 +4431,6 @@ vht_cap.cap |= val; } - /* Currently the firmware seems to be buggy, don't enable 80+80 - * mode until that's resolved. - */ - if ((ar->vht_cap_info & IEEE80211_VHT_CAP_SHORT_GI_160) && - (ar->vht_cap_info & IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_MASK) == 0) - vht_cap.cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ; - mcs_map = 0; for (i = 0; i < 8; i++) { if ((i < ar->num_rf_chains) && (ar->cfg_tx_chainmask & BIT(i))) @@ -4579,11 +4594,82 @@ return ret; } +static int ath10k_get_powered(struct ieee80211_hw *hw, bool *up, bool *busy) +{ + struct ath10k *ar = hw->priv; + *up = (ar->state == ATH10K_STATE_ON || + ar->state == ATH10K_STATE_PRE_ON); + *busy = ar->powerup_pending; + return 0; +} + +static int ath10k_set_powered(struct ieee80211_hw *hw) +{ + struct ath10k *ar = hw->priv; + + switch (ar->state) { + case ATH10K_STATE_OFF: + case ATH10K_STATE_PRE_ON: + break; + default: + return 0; + } + + if (ar->powerup_pending) + return 0; + + queue_work(ar->workqueue, &ar->powerup_work); + ar->powerup_pending = true; + return 0; +} + +static void ath10k_powerup_work(struct work_struct *work) +{ + struct ath10k *ar = container_of(work, struct ath10k, powerup_work); + int ret; + + mutex_lock(&ar->conf_mutex); + + if (ar->state != ATH10K_STATE_OFF) { + mutex_unlock(&ar->conf_mutex); + return; + } + + ret = ath10k_hif_power_up(ar); + if (ret) { + ath10k_err(ar, "Could not init hif: %d\n", ret); + goto err_off; + } + + ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_NORMAL, + &ar->normal_mode_fw); + if (ret) { + ath10k_err(ar, "Could not init core: %d\n", ret); + goto err_power_down; + } + + ar->state = ATH10K_STATE_PRE_ON; + ar->powerup_pending = false; + mutex_unlock(&ar->conf_mutex); + return; + +err_power_down: + ath10k_hif_power_down(ar); + +err_off: + ar->state = ATH10K_STATE_OFF; + + ar->powerup_pending = false; + mutex_unlock(&ar->conf_mutex); + return; +} + static int ath10k_start(struct ieee80211_hw *hw) { struct ath10k *ar = hw->priv; u32 param; int ret = 0; + bool skip_core_start = false; /* * This makes sense only when restarting hw. It is harmless to call @@ -4598,6 +4684,10 @@ case ATH10K_STATE_OFF: ar->state = ATH10K_STATE_ON; break; + case ATH10K_STATE_PRE_ON: + skip_core_start = true; + ar->state = ATH10K_STATE_ON; + break; case ATH10K_STATE_RESTARTING: ar->state = ATH10K_STATE_RESTARTED; break; @@ -4612,6 +4702,7 @@ goto err; } + if (!skip_core_start) { ret = ath10k_hif_power_up(ar); if (ret) { ath10k_err(ar, "Could not init hif: %d\n", ret); @@ -4624,6 +4715,7 @@ ath10k_err(ar, "Could not init core: %d\n", ret); goto err_power_down; } + } param = ar->wmi.pdev_param->pmf_qos; ret = ath10k_wmi_pdev_set_param(ar, param, 1); @@ -4752,6 +4844,9 @@ ath10k_drain_tx(ar); + cancel_work_sync(&ar->powerup_work); + ar->powerup_pending = false; + mutex_lock(&ar->conf_mutex); if (ar->state != ATH10K_STATE_OFF) { ath10k_halt(ar); @@ -7552,6 +7647,16 @@ arvif->vdev_id, ret); } + if (ath10k_peer_stats_enabled(ar)) { + ar->pktlog_filter |= ATH10K_PKTLOG_PEER_STATS; + ret = ath10k_wmi_pdev_pktlog_enable(ar, + ar->pktlog_filter); + if (ret) { + ath10k_warn(ar, "failed to enable pktlog %d\n", ret); + goto err_stop; + } + } + mutex_unlock(&ar->conf_mutex); return 0; @@ -7636,9 +7741,39 @@ peer->removed = true; } +static void ath10k_sta_statistics(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + struct ieee80211_sta *sta, + struct station_info *sinfo) +{ + struct ath10k_sta *arsta = (struct ath10k_sta *)sta->drv_priv; + struct ath10k *ar = arsta->arvif->ar; + + if (!ath10k_peer_stats_enabled(ar)) + return; + + sinfo->rx_duration = arsta->rx_duration; + sinfo->filled |= 1ULL << NL80211_STA_INFO_RX_DURATION; + + if (!arsta->txrate.legacy && !arsta->txrate.nss) + return; + + if (arsta->txrate.legacy) { + sinfo->txrate.legacy = arsta->txrate.legacy; + } else { + sinfo->txrate.mcs = arsta->txrate.mcs; + sinfo->txrate.nss = arsta->txrate.nss; + sinfo->txrate.bw = arsta->txrate.bw; + } + sinfo->txrate.flags = arsta->txrate.flags; + sinfo->filled |= 1ULL << NL80211_STA_INFO_TX_BITRATE; +} + static const struct ieee80211_ops ath10k_ops = { .tx = ath10k_mac_op_tx, .wake_tx_queue = ath10k_mac_op_wake_tx_queue, + .get_powered = ath10k_get_powered, + .set_powered = ath10k_set_powered, .start = ath10k_start, .stop = ath10k_stop, .config = ath10k_config, @@ -7677,6 +7812,7 @@ .unassign_vif_chanctx = ath10k_mac_op_unassign_vif_chanctx, .switch_vif_chanctx = ath10k_mac_op_switch_vif_chanctx, .sta_pre_rcu_remove = ath10k_mac_op_sta_pre_rcu_remove, + .sta_statistics = ath10k_sta_statistics, CFG80211_TESTMODE_CMD(ath10k_tm_cmd) @@ -7687,7 +7823,6 @@ #endif #ifdef CONFIG_MAC80211_DEBUGFS .sta_add_debugfs = ath10k_sta_add_debugfs, - .sta_statistics = ath10k_sta_statistics, #endif }; @@ -7845,6 +7980,7 @@ .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | BIT(NL80211_CHAN_WIDTH_20) | BIT(NL80211_CHAN_WIDTH_40) | + BIT(NL80211_CHAN_WIDTH_160) | BIT(NL80211_CHAN_WIDTH_80), #endif }, @@ -7969,6 +8105,7 @@ .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | BIT(NL80211_CHAN_WIDTH_20) | BIT(NL80211_CHAN_WIDTH_40) | + BIT(NL80211_CHAN_WIDTH_160) | BIT(NL80211_CHAN_WIDTH_80), #endif }, @@ -8008,6 +8145,8 @@ #define WRD_METHOD "WRDD" #define WRDD_WIFI (0x07) +#define ATH10K_DFS_PULSE_VALID_DIFF_TS 100 + static u32 ath10k_mac_wrdd_get_mcc(struct ath10k *ar, union acpi_object *wrdd) { union acpi_object *mcc_pkg; @@ -8197,6 +8336,7 @@ ieee80211_hw_set(ar->hw, SUPPORT_FAST_XMIT); ieee80211_hw_set(ar->hw, CONNECTION_MONITOR); ieee80211_hw_set(ar->hw, SUPPORTS_PER_STA_GTK); + ieee80211_hw_set(ar->hw, APVLAN_NEED_MCAST_TO_UCAST); ieee80211_hw_set(ar->hw, WANT_MONITOR_VIF); ieee80211_hw_set(ar->hw, CHANCTX_STA_CSA); ieee80211_hw_set(ar->hw, QUEUE_CONTROL); @@ -8320,6 +8460,8 @@ if (IS_ENABLED(CONFIG_ATH10K_DFS_CERTIFIED)) { /* Init ath dfs pattern detector */ ar->ath_common.debug_mask = ATH_DBG_DFS; + ar->ath_common.dfs_pulse_valid_diff_ts = + ATH10K_DFS_PULSE_VALID_DIFF_TS; ar->dfs_detector = dfs_pattern_detector_init(&ar->ath_common, NL80211_DFS_UNSET); @@ -8358,18 +8500,23 @@ wiphy_ext_feature_set(ar->hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST); + INIT_WORK(&ar->powerup_work, ath10k_powerup_work); + ar->powerup_pending = false; + ret = ieee80211_register_hw(ar->hw); if (ret) { ath10k_err(ar, "failed to register ieee80211: %d\n", ret); goto err_dfs_detector_exit; } +#ifndef CONFIG_ATH_REG_IGNORE if (!ath_is_world_regd(&ar->ath_common.regulatory)) { ret = regulatory_hint(ar->hw->wiphy, ar->ath_common.regulatory.alpha2); if (ret) goto err_unregister; } +#endif return 0; @@ -8391,6 +8538,7 @@ void ath10k_mac_unregister(struct ath10k *ar) { ieee80211_unregister_hw(ar->hw); + cancel_work_sync(&ar->powerup_work); if (IS_ENABLED(CONFIG_ATH10K_DFS_CERTIFIED) && ar->dfs_detector) ar->dfs_detector->exit(ar->dfs_detector); diff -ruw linux-4.14.127/drivers/net/wireless/ath/ath10k/pci.c linux-4.14.127-fbx/drivers/net/wireless/ath/ath10k/pci.c --- linux-4.14.127/drivers/net/wireless/ath/ath10k/pci.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/net/wireless/ath/ath10k/pci.c 2019-02-15 14:29:40.326649652 +0100 @@ -20,6 +20,7 @@ #include #include #include +#include #include "core.h" #include "debug.h" @@ -711,7 +712,8 @@ /* Check if the shared legacy irq is for us */ cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CAUSE_ADDRESS); - if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL)) + if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL) && + cause != 0xdeadbeef) return true; return false; @@ -2351,12 +2353,6 @@ return 0; } -static int ath10k_pci_qca99x0_soft_chip_reset(struct ath10k *ar) -{ - ath10k_pci_irq_disable(ar); - return ath10k_pci_qca99x0_chip_reset(ar); -} - static int ath10k_pci_safe_chip_reset(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); @@ -3194,7 +3190,7 @@ .get_num_banks = ath10k_pci_get_num_banks, }; -static int ath10k_pci_probe(struct pci_dev *pdev, +static int __ath10k_pci_probe(struct pci_dev *pdev, const struct pci_device_id *pci_dev) { int ret = 0; @@ -3233,21 +3229,21 @@ case QCA99X0_2_0_DEVICE_ID: hw_rev = ATH10K_HW_QCA99X0; pci_ps = false; - pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; + pci_soft_reset = NULL;; pci_hard_reset = ath10k_pci_qca99x0_chip_reset; targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; break; case QCA9984_1_0_DEVICE_ID: hw_rev = ATH10K_HW_QCA9984; pci_ps = false; - pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; + pci_soft_reset = NULL;; pci_hard_reset = ath10k_pci_qca99x0_chip_reset; targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; break; case QCA9888_2_0_DEVICE_ID: hw_rev = ATH10K_HW_QCA9888; pci_ps = false; - pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; + pci_soft_reset = NULL;; pci_hard_reset = ath10k_pci_qca99x0_chip_reset; targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; break; @@ -3431,6 +3427,23 @@ ath10k_pci_pm_suspend, ath10k_pci_pm_resume); +static int ath10k_pci_probe(struct pci_dev *pdev, + const struct pci_device_id *pci_dev) +{ + int cnt = 0; + int rv; + do { + rv = __ath10k_pci_probe(pdev, pci_dev); + if (rv == 0) + return rv; + + pr_err("ath10k: failed to probe PCI : %d, retry-count: %d\n", rv, cnt); + mdelay(10); /* let the ath10k firmware gerbil take a small break */ + } while (cnt++ < 3); + + return rv; +} + static struct pci_driver ath10k_pci_driver = { .name = "ath10k_pci", .id_table = ath10k_pci_id_table, diff -ruw linux-4.14.127/drivers/net/wireless/ath/ath10k/wmi-tlv.c linux-4.14.127-fbx/drivers/net/wireless/ath/ath10k/wmi-tlv.c --- linux-4.14.127/drivers/net/wireless/ath/ath10k/wmi-tlv.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/net/wireless/ath/ath10k/wmi-tlv.c 2019-03-29 17:33:21.529534915 +0100 @@ -553,7 +553,7 @@ ath10k_wmi_tlv_event_tx_pause(ar, skb); break; default: - ath10k_warn(ar, "Unknown eventid: %d\n", id); + ath10k_dbg(ar, ATH10K_DBG_WMI, "Unknown eventid: %d\n", id); break; } diff -ruw linux-4.14.127/drivers/net/wireless/ath/ath10k/wmi.c linux-4.14.127-fbx/drivers/net/wireless/ath/ath10k/wmi.c --- linux-4.14.127/drivers/net/wireless/ath/ath10k/wmi.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/net/wireless/ath/ath10k/wmi.c 2019-05-10 11:02:37.376383314 +0200 @@ -1660,13 +1660,18 @@ flags |= WMI_CHAN_FLAG_HT40_PLUS; if (arg->chan_radar) flags |= WMI_CHAN_FLAG_DFS; - + ch->band_center_freq2 = 0; ch->mhz = __cpu_to_le32(arg->freq); ch->band_center_freq1 = __cpu_to_le32(arg->band_center_freq1); if (arg->mode == MODE_11AC_VHT80_80) ch->band_center_freq2 = __cpu_to_le32(arg->band_center_freq2); + if (arg->mode == MODE_11AC_VHT160) { + if (arg->freq < arg->band_center_freq1) + ch->band_center_freq1 = __cpu_to_le32(arg->band_center_freq1 - 40); else - ch->band_center_freq2 = 0; + ch->band_center_freq1 = __cpu_to_le32(arg->band_center_freq1 + 40); + ch->band_center_freq2 = __cpu_to_le32(arg->band_center_freq1); + } ch->min_power = arg->min_power; ch->max_power = arg->max_power; ch->reg_power = arg->max_reg_power; @@ -5468,6 +5473,7 @@ case WMI_10_4_WOW_WAKEUP_HOST_EVENTID: case WMI_10_4_PEER_RATECODE_LIST_EVENTID: case WMI_10_4_WDS_PEER_EVENTID: + case WMI_10_4_DEBUG_FATAL_CONDITION_EVENTID: ath10k_dbg(ar, ATH10K_DBG_WMI, "received event id %d not implemented\n", id); break; @@ -6765,12 +6771,7 @@ struct wmi_10_4_peer_assoc_complete_cmd *cmd = buf; ath10k_wmi_peer_assoc_fill_10_2(ar, buf, arg); - if (arg->peer_bw_rxnss_override) - cmd->peer_bw_rxnss_override = - __cpu_to_le32((arg->peer_bw_rxnss_override - 1) | - BIT(PEER_BW_RXNSS_OVERRIDE_OFFSET)); - else - cmd->peer_bw_rxnss_override = 0; + cmd->peer_bw_rxnss_override = __cpu_to_le32(arg->peer_bw_rxnss_override); } static int diff -ruw linux-4.14.127/drivers/net/wireless/ath/ath10k/wmi.h linux-4.14.127-fbx/drivers/net/wireless/ath/ath10k/wmi.h --- linux-4.14.127/drivers/net/wireless/ath/ath10k/wmi.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/net/wireless/ath/ath10k/wmi.h 2019-02-15 14:29:40.334649684 +0100 @@ -6210,7 +6210,19 @@ __le32 info0; /* WMI_PEER_ASSOC_INFO0_ */ } __packed; -#define PEER_BW_RXNSS_OVERRIDE_OFFSET 31 +#define BW_NSS_FWCONF_MAP_ENABLE BIT(31) +#define BW_NSS_FWCONF_MAP_160MHZ_LSB (0) +#define BW_NSS_FWCONF_MAP_160MHZ_MASK (0x00000007) +#define BW_NSS_FWCONF_MAP_80_80MHZ_LSB (3) +#define BW_NSS_FWCONF_MAP_80_80MHZ_MASK (0x00000038) +#define BW_NSS_FWCONF_MAP_MASK (0x0000003F) + +#define GET_BW_NSS_FWCONF_160(x) (MS(x, BW_NSS_FWCONF_MAP_160MHZ) + 1) +#define GET_BW_NSS_FWCONF_80_80(x) (MS(x, BW_NSS_FWCONF_MAP_80_80MHZ) + 1) + +/* Values defined to set 160 MHz Bandwidth NSS Mapping into FW*/ +#define BW_NSS_FWCONF_160(x) (BW_NSS_FWCONF_MAP_ENABLE | SM(x - 1, BW_NSS_FWCONF_MAP_160MHZ)) +#define BW_NSS_FWCONF_80_80(x) (BW_NSS_FWCONF_MAP_ENABLE | SM(x - 1, BW_NSS_FWCONF_MAP_80_80MHZ)) struct wmi_10_4_peer_assoc_complete_cmd { struct wmi_10_2_peer_assoc_complete_cmd cmd; diff -ruw linux-4.14.127/drivers/net/wireless/ath/dfs_pattern_detector.c linux-4.14.127-fbx/drivers/net/wireless/ath/dfs_pattern_detector.c --- linux-4.14.127/drivers/net/wireless/ath/dfs_pattern_detector.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/net/wireless/ath/dfs_pattern_detector.c 2019-02-15 14:29:40.378649858 +0100 @@ -272,6 +272,7 @@ { u32 i; struct channel_detector *cd; + int diff_ts; /* * pulses received for a non-supported or un-initialized @@ -284,8 +285,9 @@ if (cd == NULL) return false; + diff_ts = event->ts - dpd->last_pulse_ts; /* reset detector on time stamp wraparound, caused by TSF reset */ - if (event->ts < dpd->last_pulse_ts) + if (diff_ts < dpd->common->dfs_pulse_valid_diff_ts) dpd_reset(dpd); dpd->last_pulse_ts = event->ts; diff -ruw linux-4.14.127/drivers/net/wireless/ath/dfs_pattern_detector.h linux-4.14.127-fbx/drivers/net/wireless/ath/dfs_pattern_detector.h --- linux-4.14.127/drivers/net/wireless/ath/dfs_pattern_detector.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/net/wireless/ath/dfs_pattern_detector.h 2019-02-15 14:29:40.378649858 +0100 @@ -24,7 +24,7 @@ /* tolerated deviation of radar time stamp in usecs on both sides * TODO: this might need to be HW-dependent */ -#define PRI_TOLERANCE 16 +#define PRI_TOLERANCE 6 /** * struct ath_dfs_pool_stats - DFS Statistics for global pools diff -ruw linux-4.14.127/drivers/net/wireless/ath/regd.c linux-4.14.127-fbx/drivers/net/wireless/ath/regd.c --- linux-4.14.127/drivers/net/wireless/ath/regd.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/net/wireless/ath/regd.c 2019-02-15 14:29:40.382649874 +0100 @@ -345,6 +345,10 @@ struct ieee80211_channel *ch; unsigned int i; +#ifdef CONFIG_ATH_REG_IGNORE + return; +#endif + for (band = 0; band < NUM_NL80211_BANDS; band++) { if (!wiphy->bands[band]) continue; @@ -378,6 +382,10 @@ { struct ieee80211_supported_band *sband; +#ifdef CONFIG_ATH_REG_IGNORE + return; +#endif + sband = wiphy->bands[NL80211_BAND_2GHZ]; if (!sband) return; @@ -407,6 +415,9 @@ struct ieee80211_channel *ch; unsigned int i; +#ifdef CONFIG_ATH_REG_IGNORE + return; +#endif if (!wiphy->bands[NL80211_BAND_5GHZ]) return; @@ -639,6 +650,11 @@ const struct ieee80211_regdomain *regd; wiphy->reg_notifier = reg_notifier; + +#ifdef CONFIG_ATH_REG_IGNORE + return 0; +#endif + wiphy->regulatory_flags |= REGULATORY_STRICT_REG | REGULATORY_CUSTOM_REG; @@ -703,7 +719,7 @@ regdmn == CTRY_DEFAULT) { printk(KERN_DEBUG "ath: EEPROM indicates default " "country code should be used\n"); - reg->country_code = CTRY_UNITED_STATES; + reg->country_code = CTRY_FRANCE; } if (reg->country_code == CTRY_DEFAULT) { diff -ruw linux-4.14.127/drivers/net/wireless/marvell/mwl8k.c linux-4.14.127-fbx/drivers/net/wireless/marvell/mwl8k.c --- linux-4.14.127/drivers/net/wireless/marvell/mwl8k.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/net/wireless/marvell/mwl8k.c 2019-07-22 10:44:47.990827540 +0200 @@ -24,6 +24,7 @@ #include #include #include +#include #define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver" #define MWL8K_NAME KBUILD_MODNAME @@ -35,6 +36,17 @@ MODULE_PARM_DESC(ap_mode_default, "Set to 1 to make ap mode the default instead of sta mode"); +static u8 ap_base_mac_addr[18] = "00:00:00:00:00:00"; +module_param_string(base_mac_addr, ap_base_mac_addr, 18, 0); +MODULE_PARM_DESC(ap_base_mac_addr, + "Override EEPROM defined base mac address in AP mode"); + +static int mac_addr_count = -1; +module_param(mac_addr_count, int, 0); +MODULE_PARM_DESC(ap_base_mac_addr, + "Override EEPROM defined mac address count"); + + /* Register definitions */ #define MWL8K_HIU_GEN_PTR 0x00000c10 #define MWL8K_MODE_STA 0x0000005a @@ -181,6 +193,7 @@ struct mwl8k_priv { struct ieee80211_hw *hw; struct pci_dev *pdev; + struct mac_address addresses[8]; int irq; struct mwl8k_device_info *device_info; @@ -300,6 +313,9 @@ struct ieee80211_channel *acs_chan; unsigned long channel_time; struct survey_info survey[MWL8K_NUM_CHANS]; + + unsigned int last_short_preamble; + unsigned int last_basic_rates; }; #define MAX_WEP_KEY_LEN 13 @@ -327,6 +343,9 @@ /* A flag to indicate is HW crypto is enabled for this bssid */ bool is_hw_crypto_enabled; + + u32 last_beacon_crc; + unsigned int last_beacon_int; }; #define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv)) #define IEEE80211_KEY_CONF(_u8) ((struct ieee80211_key_conf *)(_u8)) @@ -796,6 +815,11 @@ return loops ? 0 : -ETIMEDOUT; } +static bool disable_5g = 0; +module_param(disable_5g, bool, 0); +MODULE_PARM_DESC(disable_5g, + "Set to 1 to disable 5G band usage"); + /* DMA header used by firmware and hardware. */ struct mwl8k_dma_data { @@ -1012,6 +1036,9 @@ } } + if (le16_to_cpu(rxd->htsig2) & (1 << 7)) + status->enc_flags |= RX_ENC_FLAG_SHORT_GI; + if (rxd->channel > 14) { status->band = NL80211_BAND_5GHZ; if (!(status->encoding == RX_ENC_HT) && @@ -1656,6 +1683,8 @@ */ #define RI_FORMAT(a) (a & 0x0001) +#define RI_SHORT_GI(a) (a & 0x0002) +#define RI_40MHZ(a) (a & 0x0004) #define RI_RATE_ID_MCS(a) ((a & 0x01f8) >> 3) static int @@ -1713,6 +1742,8 @@ tx_desc->pkt_len = 0; info = IEEE80211_SKB_CB(skb); + rate_info = le16_to_cpu(tx_desc->rate_info); + if (ieee80211_is_data(wh->frame_control)) { rcu_read_lock(); sta = ieee80211_find_sta_by_ifaddr(hw, wh->addr1, @@ -1720,7 +1751,6 @@ if (sta) { sta_info = MWL8K_STA(sta); BUG_ON(sta_info == NULL); - rate_info = le16_to_cpu(tx_desc->rate_info); /* If rate is < 6.5 Mpbs for an ht station * do not form an ampdu. If the station is a * legacy station (format = 0), do not form an @@ -1734,18 +1764,25 @@ } } rcu_read_unlock(); - } - - ieee80211_tx_info_clear_status(info); - /* Rate control is happening in the firmware. - * Ensure no tx rate is being reported. - */ + info->status.rates[0].idx = RI_RATE_ID_MCS(rate_info); + info->status.rates[0].flags = 0; + if (RI_FORMAT(rate_info)) + info->status.rates[0].flags |= IEEE80211_TX_RC_MCS; + if (RI_SHORT_GI(rate_info)) + info->status.rates[0].flags |= IEEE80211_TX_RC_SHORT_GI; + if (RI_40MHZ(rate_info)) + info->status.rates[0].flags |= IEEE80211_TX_RC_40_MHZ_WIDTH; + info->status.rates[1].idx = -1; + } else info->status.rates[0].idx = -1; - info->status.rates[0].count = 1; + + ieee80211_tx_info_clear_status(info); if (MWL8K_TXD_SUCCESS(status)) info->flags |= IEEE80211_TX_STAT_ACK; + if (index >= MWL8K_TX_WMM_QUEUES) + info->flags |= IEEE80211_TX_STAT_AMPDU; ieee80211_tx_status_irqsafe(hw, skb); @@ -2434,7 +2471,7 @@ mwl8k_set_ht_caps(hw, &priv->band_24, caps); } - if (caps & MWL8K_CAP_5GHZ) { + if (!disable_5g && (caps & MWL8K_CAP_5GHZ)) { mwl8k_setup_5ghz_band(hw); if (caps & MWL8K_CAP_MIMO) mwl8k_set_ht_caps(hw, &priv->band_50, caps); @@ -2508,6 +2545,20 @@ __le32 wcbbase_ampdu[MWL8K_MAX_AMPDU_QUEUES]; } __packed; +static void inc_mac(u8 *base, unsigned int count) +{ + unsigned int i; + + for (i = 0; i < count; i++) { + int j; + + for (j = 5; j >= 0; j--) { + if (++base[j] != 0) + break; + } + } +} + static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw) { struct mwl8k_priv *priv = hw->priv; @@ -2529,6 +2580,7 @@ if (!rc) { int off; + u8 ap_base_mac[ETH_ALEN]; api_version = le32_to_cpu(cmd->fw_api_version); if (priv->device_info->fw_api_ap != api_version) { @@ -2540,7 +2592,27 @@ rc = -EINVAL; goto done; } + + if (mac_pton(ap_base_mac_addr, ap_base_mac) && + !is_zero_ether_addr(ap_base_mac)) + SET_IEEE80211_PERM_ADDR(hw, ap_base_mac); + else SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr); + + if (mac_addr_count > 0) { + unsigned int i; + + for (i = 0; i < mac_addr_count && + i < ARRAY_SIZE(priv->addresses); i++) { + memcpy(&priv->addresses[i], + hw->wiphy->perm_addr, 6); + inc_mac(priv->addresses[i].addr, i); + } + + hw->wiphy->addresses = priv->addresses; + hw->wiphy->n_addresses = i; + } + priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs); priv->fw_rev = le32_to_cpu(cmd->fw_rev); priv->hw_rev = cmd->hw_rev; @@ -4704,10 +4776,6 @@ } priv->irq = priv->pdev->irq; - /* Enable TX reclaim and RX tasklets. */ - tasklet_enable(&priv->poll_tx_task); - tasklet_enable(&priv->poll_rx_task); - /* Enable interrupts */ iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); iowrite32(MWL8K_A2H_EVENTS, @@ -4742,12 +4810,15 @@ iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); free_irq(priv->pdev->irq, hw); priv->irq = -1; - tasklet_disable(&priv->poll_tx_task); - tasklet_disable(&priv->poll_rx_task); + tasklet_kill(&priv->poll_tx_task); + tasklet_kill(&priv->poll_rx_task); } else { ieee80211_wake_queues(hw); } + priv->last_short_preamble = ~0; + priv->last_basic_rates = ~0; + return rc; } @@ -4775,8 +4846,8 @@ dev_kfree_skb(priv->beacon_skb); /* Stop TX reclaim and RX tasklets. */ - tasklet_disable(&priv->poll_tx_task); - tasklet_disable(&priv->poll_rx_task); + tasklet_kill(&priv->poll_tx_task); + tasklet_kill(&priv->poll_rx_task); /* Return all skbs to mac80211 */ for (i = 0; i < mwl8k_tx_queues(priv); i++) @@ -4851,6 +4922,8 @@ mwl8k_vif->seqno = 0; memcpy(mwl8k_vif->bssid, vif->addr, ETH_ALEN); mwl8k_vif->is_hw_crypto_enabled = false; + mwl8k_vif->last_beacon_crc = ~0; + mwl8k_vif->last_beacon_int = ~0; /* Set the mac address. */ mwl8k_cmd_set_mac_addr(hw, vif, vif->addr); @@ -5096,19 +5169,27 @@ mwl8k_bss_info_changed_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct ieee80211_bss_conf *info, u32 changed) { + struct mwl8k_priv *priv = hw->priv; + struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif); + struct sk_buff *skb; + bool update_beacon; + u32 crc; int rc; if (mwl8k_fw_lock(hw)) return; - if (changed & BSS_CHANGED_ERP_PREAMBLE) { + if ((changed & BSS_CHANGED_ERP_PREAMBLE) && + priv->last_short_preamble != vif->bss_conf.use_short_preamble) { rc = mwl8k_set_radio_preamble(hw, vif->bss_conf.use_short_preamble); if (rc) goto out; + priv->last_short_preamble = vif->bss_conf.use_short_preamble; } - if (changed & BSS_CHANGED_BASIC_RATES) { + if ((changed & BSS_CHANGED_BASIC_RATES) && + priv->last_basic_rates != vif->bss_conf.basic_rates) { int idx; int rate; @@ -5127,18 +5208,33 @@ rate = mwl8k_rates_50[idx].hw_value; mwl8k_cmd_use_fixed_rate_ap(hw, rate, rate); + priv->last_basic_rates = vif->bss_conf.basic_rates; } - if (changed & (BSS_CHANGED_BEACON_INT | BSS_CHANGED_BEACON)) { - struct sk_buff *skb; + update_beacon = false; + + if ((changed & BSS_CHANGED_BEACON_INT) && + mwl8k_vif->last_beacon_int != vif->bss_conf.beacon_int) + update_beacon = true; skb = ieee80211_beacon_get(hw, vif); - if (skb != NULL) { - mwl8k_cmd_set_beacon(hw, vif, skb->data, skb->len); - kfree_skb(skb); + crc = 0; + + if (changed & BSS_CHANGED_BEACON) { + if (skb) { + crc = crc32_le(~0, skb->data, skb->len); + if (crc != mwl8k_vif->last_beacon_crc) + update_beacon = true; } } + if (skb && update_beacon) { + mwl8k_cmd_set_beacon(hw, vif, skb->data, skb->len); + mwl8k_vif->last_beacon_crc = crc; + mwl8k_vif->last_beacon_int = vif->bss_conf.beacon_int; + } + kfree_skb(skb); + if (changed & BSS_CHANGED_BEACON_ENABLED) mwl8k_cmd_bss_start(hw, vif, info->enable_beacon); @@ -6091,8 +6187,10 @@ * Ask mac80211 to not to trigger PS mode * based on PM bit of incoming frames. */ - if (priv->ap_fw) + if (priv->ap_fw) { ieee80211_hw_set(hw, AP_LINK_PS); + ieee80211_hw_set(hw, APVLAN_NEED_MCAST_TO_UCAST); + } hw->vif_data_size = sizeof(struct mwl8k_vif); hw->sta_data_size = sizeof(struct mwl8k_sta); @@ -6113,9 +6211,7 @@ /* TX reclaim and RX tasklets. */ tasklet_init(&priv->poll_tx_task, mwl8k_tx_poll, (unsigned long)hw); - tasklet_disable(&priv->poll_tx_task); tasklet_init(&priv->poll_rx_task, mwl8k_rx_poll, (unsigned long)hw); - tasklet_disable(&priv->poll_rx_task); /* Power management cookie */ priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma); diff -ruw linux-4.14.127/drivers/nvmem/Kconfig linux-4.14.127-fbx/drivers/nvmem/Kconfig --- linux-4.14.127/drivers/nvmem/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/nvmem/Kconfig 2019-02-15 14:29:40.702651142 +0100 @@ -13,6 +13,9 @@ if NVMEM +config NVMEM_IGNORE_RO + bool "ignore read-only flags" + config NVMEM_IMX_IIM tristate "i.MX IC Identification Module support" depends on ARCH_MXC || COMPILE_TEST diff -ruw linux-4.14.127/drivers/nvmem/core.c linux-4.14.127-fbx/drivers/nvmem/core.c --- linux-4.14.127/drivers/nvmem/core.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/nvmem/core.c 2019-07-22 10:44:48.002827590 +0200 @@ -477,8 +477,10 @@ config->name ? : "nvmem", config->name ? config->id : nvmem->id); +#ifndef CONFIG_NVMEM_IGNORE_RO nvmem->read_only = of_property_read_bool(np, "read-only") | config->read_only; +#endif if (config->root_only) nvmem->dev.groups = nvmem->read_only ? diff -ruw linux-4.14.127/drivers/of/Kconfig linux-4.14.127-fbx/drivers/of/Kconfig --- linux-4.14.127/drivers/of/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/of/Kconfig 2019-02-15 14:29:40.706651158 +0100 @@ -33,6 +33,11 @@ If unsure, say N here, but this option is safe to enable. +config OF_DTB_BUILTIN_LIST + string "Link given list of DTB files into kernel" + help + Specify filename without .dtb extension + config OF_FLATTREE bool select DTC @@ -112,4 +117,11 @@ config OF_NUMA bool +config OF_CONFIGFS + bool "Device Tree Overlay ConfigFS interface" + select CONFIGFS_FS + select OF_OVERLAY + help + Enable a simple user-space driven DT overlay interface. + endif # OF diff -ruw linux-4.14.127/drivers/of/Makefile linux-4.14.127-fbx/drivers/of/Makefile --- linux-4.14.127/drivers/of/Makefile 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/of/Makefile 2019-02-15 14:29:40.706651158 +0100 @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-y = base.o device.o platform.o property.o +obj-$(CONFIG_OF_CONFIGFS) += configfs.o obj-$(CONFIG_OF_DYNAMIC) += dynamic.o obj-$(CONFIG_OF_FLATTREE) += fdt.o obj-$(CONFIG_OF_EARLY_FLATTREE) += fdt_address.o diff -ruw linux-4.14.127/drivers/of/fdt.c linux-4.14.127-fbx/drivers/of/fdt.c --- linux-4.14.127/drivers/of/fdt.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/of/fdt.c 2019-02-15 14:29:40.710651175 +0100 @@ -30,6 +30,7 @@ #include /* for COMMAND_LINE_SIZE */ #include +#include #include "of_private.h" @@ -113,6 +114,39 @@ return 0; } +/* + * iterate list of built-in dtb to find a compatible match + */ +const void __init *of_fdt_find_compatible_dtb(const char *name) +{ + struct fdt_header { + __be32 magic; + __be32 totalsize; + }; + const struct fdt_header *blob, *best; + unsigned int best_score = ~0; + + best = NULL; + blob = (const struct fdt_header *)__dtb_start; + while ((void *)blob < (void *)__dtb_end && + (be32_to_cpu(blob->magic) == OF_DT_HEADER)) { + unsigned int score; + u32 size; + + score = of_fdt_is_compatible(blob, 0, name); + if (score > 0 && score < best_score) { + best = blob; + best_score = score; + } + + size = be32_to_cpu(blob->totalsize); + blob = (const struct fdt_header *) + PTR_ALIGN((void *)blob + size, STRUCT_ALIGNMENT); + } + + return best; +} + /** * of_fdt_is_big_endian - Return true if given node needs BE MMIO accesses * @blob: A device tree blob diff -ruw linux-4.14.127/drivers/of/of_net.c linux-4.14.127-fbx/drivers/of/of_net.c --- linux-4.14.127/drivers/of/of_net.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/of/of_net.c 2019-02-15 14:29:40.710651175 +0100 @@ -10,6 +10,7 @@ #include #include #include +#include /** * of_get_phy_mode - Get phy mode for given device_node @@ -68,6 +69,13 @@ const void *of_get_mac_address(struct device_node *np) { const void *addr; +#ifdef CONFIG_FBXSERIAL + struct property *pp; + + pp = of_find_property(np, "fbxserial-mac-address", NULL); + if (pp && pp->length == 4) + return fbxserialinfo_get_mac_addr(be32_to_cpu(*(u32*)pp->value)); +#endif addr = of_get_mac_addr(np, "mac-address"); if (addr) diff -ruw linux-4.14.127/drivers/of/of_reserved_mem.c linux-4.14.127-fbx/drivers/of/of_reserved_mem.c --- linux-4.14.127/drivers/of/of_reserved_mem.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/of/of_reserved_mem.c 2019-02-15 14:29:40.710651175 +0100 @@ -26,8 +26,8 @@ #include #define MAX_RESERVED_REGIONS 32 -static struct reserved_mem reserved_mem[MAX_RESERVED_REGIONS]; -static int reserved_mem_count; +struct reserved_mem reserved_mem[MAX_RESERVED_REGIONS]; +int reserved_mem_count; #if defined(CONFIG_HAVE_MEMBLOCK) #include @@ -397,3 +397,29 @@ rmem->ops->device_release(rmem, dev); } EXPORT_SYMBOL_GPL(of_reserved_mem_device_release); + +/** + * of_get_reserved_mem_by_idx() - acquire reserved_mem from memory-region + * @np: node pointer containing the "memory-region" + * @idx: index within memory-region + * + * This function allows drivers to acquire a reference to the reserved_mem + * struct which is referenced by their memory-region. + * + * Returns a reserved_mem reference, or NULL on error. + */ +struct reserved_mem *of_get_reserved_mem_by_idx(struct device_node *np, int idx) +{ + struct device_node *target; + struct reserved_mem *rmem; + + target = of_parse_phandle(np, "memory-region", idx); + if (!target) + return NULL; + + rmem = __find_rmem(target); + of_node_put(target); + + return rmem; +} +EXPORT_SYMBOL_GPL(of_get_reserved_mem_by_idx); diff -ruw linux-4.14.127/drivers/pci/dwc/pcie-armada8k.c linux-4.14.127-fbx/drivers/pci/dwc/pcie-armada8k.c --- linux-4.14.127/drivers/pci/dwc/pcie-armada8k.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/pci/dwc/pcie-armada8k.c 2019-02-15 14:29:40.790651491 +0100 @@ -25,12 +25,16 @@ #include #include #include +#include #include "pcie-designware.h" struct armada8k_pcie { struct dw_pcie *pci; struct clk *clk; + struct phy *phys[4]; + unsigned int phys_count; + struct gpio_descs *reset_gpios; }; #define PCIE_VENDOR_REGS_OFFSET 0x8000 @@ -67,6 +71,11 @@ #define AX_USER_DOMAIN_MASK 0x3 #define AX_USER_DOMAIN_SHIFT 4 +#define PCIE_LANE_EQ_CTRL01_REG 0x164 +#define PCIE_LANE_EQ_CTRL23_REG 0x168 +#define PCIE_LANE_EQ_SETTING 0x7700 +#define PCIE_LANE_EQ_MASK 0x7f00 + #define to_armada8k_pcie(x) dev_get_drvdata((x)->dev) static int armada8k_pcie_link_up(struct dw_pcie *pci) @@ -83,6 +92,54 @@ return 0; } +static void armada8k_pcie_reset_port(struct pcie_port *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct armada8k_pcie *pcie = to_armada8k_pcie(pci); + + /* + * Power up a PCIe port. PCIe requires the refclk to be + * stable for 100µs + * + * prior to releasing PERST. See table 2-4 in section 2.6.2 + * AC Specifications + * + * of the PCI Express Card Electromechanical Specification, 1.1. + */ + if (pcie->reset_gpios) { + struct gpio_descs *reset_gpios = pcie->reset_gpios; + u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000; + int i, values[reset_gpios->ndescs]; + + dev_info(pci->dev, "using %u gpio(s) to reset bus", + reset_gpios->ndescs); + + /* + * explicitely assert reset. + */ + for (i = 0; i < reset_gpios->ndescs; i++) + values[i] = 0; + + gpiod_set_array_value_cansleep(reset_gpios->ndescs, + reset_gpios->desc, + values); + + udelay(150); + + /* + * deassert reset. + */ + for (i = 0; i < reset_gpios->ndescs; i++) + values[i] = 1; + + gpiod_set_array_value_cansleep(reset_gpios->ndescs, + reset_gpios->desc, + values); + + msleep(reset_udelay / 1000); + } +} + static void armada8k_pcie_establish_link(struct armada8k_pcie *pcie) { struct dw_pcie *pci = pcie->pci; @@ -130,8 +187,13 @@ } /* Wait until the link becomes active again */ + if (dw_pcie_wait_for_link(pci)) { + dev_err(pci->dev, "Link not up after reconfiguration. " + "trying port reset\n"); + armada8k_pcie_reset_port(&pci->pp); if (dw_pcie_wait_for_link(pci)) - dev_err(pci->dev, "Link not up after reconfiguration\n"); + dev_err(pci->dev, "Link not up after reset.\n"); + } } static int armada8k_pcie_host_init(struct pcie_port *pp) @@ -140,6 +202,7 @@ struct armada8k_pcie *pcie = to_armada8k_pcie(pci); dw_pcie_setup_rc(pp); + armada8k_pcie_reset_port(pp); armada8k_pcie_establish_link(pcie); return 0; @@ -166,13 +229,51 @@ .host_init = armada8k_pcie_host_init, }; +#define REP_U16(x) (((x & 0xffff) << 16) | (x & 0xffff)) + +static void armada8k_pcie_configure_lane_eq(struct dw_pcie *pci, u32 lane_count) +{ + u32 val01 = 0, val23 = 0, mask01 = 0, mask23 = 0; + u32 reg; + + switch (lane_count) { + case 1: + mask01 = PCIE_LANE_EQ_MASK; + val01 = PCIE_LANE_EQ_SETTING; + break; + + case 2: + set_val01_mask01: + mask01 = REP_U16(PCIE_LANE_EQ_MASK); + val01 = REP_U16(PCIE_LANE_EQ_SETTING); + break; + case 4: + mask23 = REP_U16(PCIE_LANE_EQ_MASK); + val23 = REP_U16(PCIE_LANE_EQ_SETTING); + goto set_val01_mask01; + } + + if (val01) { + reg = dw_pcie_readl_dbi(pci, PCIE_LANE_EQ_CTRL01_REG); + reg &= ~mask01; + reg |= val01; + dw_pcie_writel_dbi(pci, PCIE_LANE_EQ_CTRL01_REG, reg); + } + if (val23) { + reg = dw_pcie_readl_dbi(pci, PCIE_LANE_EQ_CTRL23_REG); + reg &= ~mask23; + reg |= val23; + dw_pcie_writel_dbi(pci, PCIE_LANE_EQ_CTRL23_REG, reg); + } +} + static int armada8k_add_pcie_port(struct armada8k_pcie *pcie, struct platform_device *pdev) { struct dw_pcie *pci = pcie->pci; struct pcie_port *pp = &pci->pp; struct device *dev = &pdev->dev; - int ret; + int ret, i; pp->root_bus_nr = -1; pp->ops = &armada8k_pcie_host_ops; @@ -190,6 +291,19 @@ return ret; } + for (i = 0; i < pcie->phys_count; ++i) { + int error; + + error = phy_power_on(pcie->phys[i]); + if (error) { + dev_warn(pci->dev, "unable to power on phy on lane " + "%d\n", i); + return error; + } + } + + armada8k_pcie_configure_lane_eq(pci, pcie->phys_count); + ret = dw_pcie_host_init(pp); if (ret) { dev_err(dev, "failed to initialize host: %d\n", ret); @@ -203,6 +317,47 @@ .link_up = armada8k_pcie_link_up, }; +static int armada8k_pcie_get_phys(struct platform_device *pdev, + struct armada8k_pcie *pcie) +{ + int i; + int error; + + error = of_property_read_u32(pdev->dev.of_node, "num-lanes", + &pcie->phys_count); + if (error || !pcie->phys_count || pcie->phys_count > 4 || + pcie->phys_count == 3) { + dev_err(&pdev->dev, "bad/invalid num-lanes attribute.\n"); + return -EINVAL; + } + + dev_dbg(&pdev->dev, "pcie->phys_count = %d\n", pcie->phys_count); + + for (i = 0; i < pcie->phys_count; ++i) { + char lane_buf[32]; + + snprintf(lane_buf, sizeof (lane_buf), "lane%d", i); + + pcie->phys[i] = devm_of_phy_get(&pdev->dev, pdev->dev.of_node, + lane_buf); + if (IS_ERR(pcie->phys[i])) { + dev_err(&pdev->dev, "no phy for lane%d: %ld\n", i, + PTR_ERR(pcie->phys[i])); + return PTR_ERR(pcie->phys[i]); + } + + error = phy_set_mode(pcie->phys[i], PHY_MODE_PCIE); + if (error) { + dev_warn(&pdev->dev, "assigned phy cannot work in PCIe " + "mode: %d\n", error); + return error; + } + + dev_dbg(&pdev->dev, "got phy for lane%d\n", i); + } + return 0; +} + static int armada8k_pcie_probe(struct platform_device *pdev) { struct dw_pcie *pci; @@ -224,6 +379,16 @@ pcie->pci = pci; + /* get reset gpios */ + pcie->reset_gpios = devm_gpiod_get_array_optional(dev, + "reset", + GPIOD_OUT_LOW); + if (IS_ERR(pcie->reset_gpios)) { + ret = PTR_ERR(pcie->reset_gpios); + dev_err(dev, "failed to parse reset-gpios property: %d\n", ret); + return ret; + } + pcie->clk = devm_clk_get(dev, NULL); if (IS_ERR(pcie->clk)) return PTR_ERR(pcie->clk); @@ -243,6 +408,10 @@ platform_set_drvdata(pdev, pcie); + ret = armada8k_pcie_get_phys(pdev, pcie); + if (ret) + goto fail; + ret = armada8k_add_pcie_port(pcie, pdev); if (ret) goto fail; diff -ruw linux-4.14.127/drivers/pci/probe.c linux-4.14.127-fbx/drivers/pci/probe.c --- linux-4.14.127/drivers/pci/probe.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/pci/probe.c 2019-02-15 14:29:40.830651650 +0100 @@ -1078,8 +1078,7 @@ child = pci_add_new_bus(bus, dev, max+1); if (!child) goto out; - pci_bus_insert_busn_res(child, max+1, - bus->busn_res.end); + pci_bus_insert_busn_res(child, max+1, 0xff); } max++; buses = (buses & 0xff000000) @@ -2440,10 +2439,6 @@ if (bus->self && bus->self->is_hotplug_bridge && pci_hotplug_bus_size) { if (max - bus->busn_res.start < pci_hotplug_bus_size - 1) max = bus->busn_res.start + pci_hotplug_bus_size - 1; - - /* Do not allocate more buses than we have room left */ - if (max > bus->busn_res.end) - max = bus->busn_res.end; } /* diff -ruw linux-4.14.127/drivers/pci/quirks.c linux-4.14.127-fbx/drivers/pci/quirks.c --- linux-4.14.127/drivers/pci/quirks.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/pci/quirks.c 2019-07-22 10:44:48.010827623 +0200 @@ -2864,6 +2864,8 @@ } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PI7C9X20303SL, + quirk_hotplug_bridge); /* * This is a quirk for the Ricoh MMC controller found as a part of diff -ruw linux-4.14.127/drivers/phy/Kconfig linux-4.14.127-fbx/drivers/phy/Kconfig --- linux-4.14.127/drivers/phy/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/phy/Kconfig 2019-02-15 14:29:40.842651697 +0100 @@ -40,6 +40,10 @@ help This option enables support for APM X-Gene SoC multi-purpose PHY. +config XDSL_PHY_API + tristate "xDSL PHY API" + select GENERIC_PHY + source "drivers/phy/allwinner/Kconfig" source "drivers/phy/amlogic/Kconfig" source "drivers/phy/broadcom/Kconfig" diff -ruw linux-4.14.127/drivers/phy/Makefile linux-4.14.127-fbx/drivers/phy/Makefile --- linux-4.14.127/drivers/phy/Makefile 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/phy/Makefile 2019-02-15 14:29:40.842651697 +0100 @@ -7,6 +7,8 @@ obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o obj-$(CONFIG_PHY_XGENE) += phy-xgene.o obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o +obj-$(CONFIG_XDSL_PHY_API) += xdsl_phy_api.o + obj-$(CONFIG_ARCH_SUNXI) += allwinner/ obj-$(CONFIG_ARCH_MESON) += amlogic/ obj-$(CONFIG_LANTIQ) += lantiq/ diff -ruw linux-4.14.127/drivers/phy/broadcom/Kconfig linux-4.14.127-fbx/drivers/phy/broadcom/Kconfig --- linux-4.14.127/drivers/phy/broadcom/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/phy/broadcom/Kconfig 2019-02-15 14:29:40.846651713 +0100 @@ -17,6 +17,11 @@ help Enable this to support the Broadcom Kona USB 2.0 PHY. +config PHY_BRCM_USB_63138 + tristate "Broadcom 63138 USB 2.0/3.0 PHY Driver" + depends on ARCH_BCM_63XX || COMPILE_TEST + select GENERIC_PHY + config PHY_BCM_NS_USB2 tristate "Broadcom Northstar USB 2.0 PHY Driver" depends on ARCH_BCM_IPROC || COMPILE_TEST diff -ruw linux-4.14.127/drivers/phy/broadcom/Makefile linux-4.14.127-fbx/drivers/phy/broadcom/Makefile --- linux-4.14.127/drivers/phy/broadcom/Makefile 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/phy/broadcom/Makefile 2019-02-15 14:29:40.846651713 +0100 @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o +obj-$(CONFIG_PHY_BRCM_USB_63138) += phy-brcm-usb-63138.o obj-$(CONFIG_BCM_KONA_USB2_PHY) += phy-bcm-kona-usb2.o obj-$(CONFIG_PHY_BCM_NS_USB2) += phy-bcm-ns-usb2.o obj-$(CONFIG_PHY_BCM_NS_USB3) += phy-bcm-ns-usb3.o diff -ruw linux-4.14.127/drivers/phy/marvell/Kconfig linux-4.14.127-fbx/drivers/phy/marvell/Kconfig --- linux-4.14.127/drivers/phy/marvell/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/phy/marvell/Kconfig 2019-02-15 14:29:40.846651713 +0100 @@ -59,3 +59,11 @@ The PHY driver will be used by Marvell udc/ehci/otg driver. To compile this driver as a module, choose M here. + +config PHY_UTMI_CP110 + bool "Marvell CP110 UTMI PHY Driver" + depends on ARCH_MVEBU + depends on OF + help + Enable this to support Marvell USB2.0 PHY driver for Marvell + CP110-based SoCs (A7K and A8K). diff -ruw linux-4.14.127/drivers/phy/marvell/Makefile linux-4.14.127-fbx/drivers/phy/marvell/Makefile --- linux-4.14.127/drivers/phy/marvell/Makefile 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/phy/marvell/Makefile 2019-02-15 14:29:40.846651713 +0100 @@ -6,3 +6,4 @@ obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o obj-$(CONFIG_PHY_PXA_28NM_HSIC) += phy-pxa-28nm-hsic.o obj-$(CONFIG_PHY_PXA_28NM_USB2) += phy-pxa-28nm-usb2.o +obj-$(CONFIG_PHY_UTMI_CP110) += phy-utmi-cp110.o diff -ruw linux-4.14.127/drivers/phy/marvell/phy-mvebu-cp110-comphy.c linux-4.14.127-fbx/drivers/phy/marvell/phy-mvebu-cp110-comphy.c --- linux-4.14.127/drivers/phy/marvell/phy-mvebu-cp110-comphy.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/phy/marvell/phy-mvebu-cp110-comphy.c 2019-07-22 10:44:48.010827623 +0200 @@ -15,6 +15,7 @@ #include #include #include +#include /* Relative to priv->base */ #define MVEBU_COMPHY_SERDES_CFG0(n) (0x0 + (n) * 0x1000) @@ -31,6 +32,7 @@ #define MVEBU_COMPHY_SERDES_CFG1_RF_RESET BIT(6) #define MVEBU_COMPHY_SERDES_CFG2(n) (0x8 + (n) * 0x1000) #define MVEBU_COMPHY_SERDES_CFG2_DFE_EN BIT(4) +#define MVEBU_COMPHY_SERDES_CFG2_SSC_EN BIT(7) #define MVEBU_COMPHY_SERDES_STATUS0(n) (0x18 + (n) * 0x1000) #define MVEBU_COMPHY_SERDES_STATUS0_TX_PLL_RDY BIT(2) #define MVEBU_COMPHY_SERDES_STATUS0_RX_PLL_RDY BIT(3) @@ -48,7 +50,9 @@ #define MVEBU_COMPHY_COEF_DFE_CTRL BIT(15) #define MVEBU_COMPHY_GEN1_S0(n) (0x834 + (n) * 0x1000) #define MVEBU_COMPHY_GEN1_S0_TX_AMP(n) ((n) << 1) +#define MVEBU_COMPHY_GEN1_S0_TX_AMP_ADJ BIT(6) #define MVEBU_COMPHY_GEN1_S0_TX_EMPH(n) ((n) << 7) +#define MVEBU_COMPHY_GEN1_S0_TX_EMPH_EN BIT(11) #define MVEBU_COMPHY_GEN1_S1(n) (0x838 + (n) * 0x1000) #define MVEBU_COMPHY_GEN1_S1_RX_MUL_PI(n) ((n) << 0) #define MVEBU_COMPHY_GEN1_S1_RX_MUL_PF(n) ((n) << 3) @@ -56,21 +60,66 @@ #define MVEBU_COMPHY_GEN1_S1_RX_MUL_FF(n) ((n) << 8) #define MVEBU_COMPHY_GEN1_S1_RX_DFE_EN BIT(10) #define MVEBU_COMPHY_GEN1_S1_RX_DIV(n) ((n) << 11) +#define MVEBU_COMPHY_GEN2_S0(n) (0x83c + (n) * 0x1000) +#define MVEBU_COMPHY_GEN2_S0_TX_AMP(n) ((n) << 1) +#define MVEBU_COMPHY_GEN2_S0_TX_AMP_ADJ BIT(6) +#define MVEBU_COMPHY_GEN2_S0_TX_EMPH(n) ((n) << 7) +#define MVEBU_COMPHY_GEN2_S0_TX_EMPH_EN BIT(11) +#define MVEBU_COMPHY_GEN2_S1(n) (0x840 + (n) * 0x1000) +#define MVEBU_COMPHY_GEN2_S1_RX_MUL_PI(n) ((n) << 0) +#define MVEBU_COMPHY_GEN2_S1_RX_MUL_PF(n) ((n) << 3) +#define MVEBU_COMPHY_GEN2_S1_RX_MUL_FI(n) ((n) << 6) +#define MVEBU_COMPHY_GEN2_S1_RX_MUL_FF(n) ((n) << 8) +#define MVEBU_COMPHY_GEN2_S1_RX_DFE_EN BIT(10) +#define MVEBU_COMPHY_GEN2_S1_RX_DIV(n) ((n) << 11) +#define MVEBU_COMPHY_GEN3_S0(n) (0x844 + (n) * 0x1000) +#define MVEBU_COMPHY_GEN3_S0_TX_AMP(n) ((n) << 1) +#define MVEBU_COMPHY_GEN3_S0_TX_AMP_ADJ BIT(6) +#define MVEBU_COMPHY_GEN3_S0_TX_EMPH(n) ((n) << 7) +#define MVEBU_COMPHY_GEN3_S0_TX_EMPH_EN BIT(11) +#define MVEBU_COMPHY_GEN3_S0_TX_SLEW_RATE_SEL(n) ((n) << 12) +#define MVEBU_COMPHY_GEN3_S0_TX_SLEW_CTRL_EN BIT(15) +#define MVEBU_COMPHY_GEN3_S1(n) (0x848 + (n) * 0x1000) +#define MVEBU_COMPHY_GEN3_S1_RX_MUL_PI(n) ((n) << 0) +#define MVEBU_COMPHY_GEN3_S1_RX_MUL_PF(n) ((n) << 3) +#define MVEBU_COMPHY_GEN3_S1_RX_MUL_FI(n) ((n) << 6) +#define MVEBU_COMPHY_GEN3_S1_RX_MUL_FF(n) ((n) << 8) +#define MVEBU_COMPHY_GEN3_S1_RX_DFE_EN BIT(10) +#define MVEBU_COMPHY_GEN3_S1_RX_DIV(n) ((n) << 11) +#define MVEBU_COMPHY_GEN3_S1_SMPL_INPX2_EN BIT(13) #define MVEBU_COMPHY_GEN1_S2(n) (0x8f4 + (n) * 0x1000) #define MVEBU_COMPHY_GEN1_S2_TX_EMPH(n) ((n) << 0) #define MVEBU_COMPHY_GEN1_S2_TX_EMPH_EN BIT(4) #define MVEBU_COMPHY_LOOPBACK(n) (0x88c + (n) * 0x1000) #define MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(n) ((n) << 1) +#define MVEBU_COMPHY_SYNC_PATTERN(n) (0x890 + (n) * 0x1000) +#define MVEBU_COMPHY_SYNC_PATTERN_RXD_INV BIT(11) +#define MVEBU_COMPHY_SYNC_PATTERN_TXD_INV BIT(10) +#define MVEBU_COMPHY_INTERFACE(n) (0x894 + (n) * 0x1000) +#define MVEBU_COMPHY_INTERFACE_GEN_MAX(n) ((n) << 10) +#define MVEBU_COMPHY_INTERFACE_DET_BYPASS BIT(12) +#define MVEBU_COMPHY_INTERFACE_LINK_TRAIN BIT(14) #define MVEBU_COMPHY_VDD_CAL0(n) (0x908 + (n) * 0x1000) #define MVEBU_COMPHY_VDD_CAL0_CONT_MODE BIT(15) #define MVEBU_COMPHY_EXT_SELV(n) (0x914 + (n) * 0x1000) #define MVEBU_COMPHY_EXT_SELV_RX_SAMPL(n) ((n) << 5) +#define MVEBU_COMPHY_PCIE_REG0(n) (0x920 + (n) * 0x1000) +#define MVEBU_COMPHY_PCIE_REG0_IDLE_SYNC BIT(12) +#define MVEBU_COMPHY_PCIE_REG0_SEL_BITS(n) ((n) << 13) +#define MVEBU_COMPHY_LANE_ALIGN(n) (0x924 + (n) * 0x1000) +#define MVEBU_COMPHY_LANE_ALIGN_BIT BIT(12) #define MVEBU_COMPHY_MISC_CTRL0(n) (0x93c + (n) * 0x1000) +#define MVEBU_COMPHY_MISC_CTRL0_CLK100M_125M BIT(4) #define MVEBU_COMPHY_MISC_CTRL0_ICP_FORCE BIT(5) +#define MVEBU_COMPHY_MISC_CTRL0_TXDCLK_2X BIT(6) +#define MVEBU_COMPHY_MISC_CTRL0_CLK500M_EN BIT(7) #define MVEBU_COMPHY_MISC_CTRL0_REFCLK_SEL BIT(10) #define MVEBU_COMPHY_RX_CTRL1(n) (0x940 + (n) * 0x1000) #define MVEBU_COMPHY_RX_CTRL1_RXCLK2X_SEL BIT(11) #define MVEBU_COMPHY_RX_CTRL1_CLK8T_EN BIT(12) +#define MVEBU_COMPHY_PWR_CTR(n) (0x948 + (n) * 0x1000) +#define MVEBU_COMPHY_PWR_CTR_RST_DFE BIT(0) +#define MVEBU_COMPHY_PWR_CTR_SOFT_RST BIT(10) #define MVEBU_COMPHY_SPEED_DIV(n) (0x954 + (n) * 0x1000) #define MVEBU_COMPHY_SPEED_DIV_TX_FORCE BIT(7) #define MVEBU_SP_CALIB(n) (0x96c + (n) * 0x1000) @@ -80,7 +129,21 @@ #define MVEBU_COMPHY_TX_SLEW_RATE_EMPH(n) ((n) << 5) #define MVEBU_COMPHY_TX_SLEW_RATE_SLC(n) ((n) << 10) #define MVEBU_COMPHY_DLT_CTRL(n) (0x984 + (n) * 0x1000) +#define MVEBU_COMPHY_DLT_CTRL_DTL_DET_EN BIT(0) +#define MVEBU_COMPHY_DLT_CTRL_DTL_PLOOP_EN BIT(1) #define MVEBU_COMPHY_DLT_CTRL_DTL_FLOOP_EN BIT(2) +#define MVEBU_COMPHY_DLT_CTRL_DTL_CLAMP_SEL(n) ((n) << 4) +#define MVEBU_COMPHY_DLT_CTRL_DTL_INPCLK_DIV_FORCE BIT(10) +#define MVEBU_COMPHY_DLT_CTRL_DTL_CLK_MODE(n) ((n) << 12) +#define MVEBU_COMPHY_DLT_CTRL_DTL_CLK_MODE_FORCE BIT(14) +#define MVEBU_COMPHY_PHASE_CTRL(n) (0x988 + (n) * 0x1000) +#define MVEBU_COMPHY_PHASE_CTRL_OS_PH_OFF(n) ((n) << 0) +#define MVEBU_COMPHY_PHASE_CTRL_OS_PH_OFF_FORCE BIT(7) +#define MVEBU_COMPHY_PHASE_CTRL_OS_PH_OFF_VALID BIT(8) +#define MVEBU_COMPHY_TX_TRAIN_CTRL(n) (0xa6c + (n) * 0x1000) +#define MVEBU_COMPHY_TX_TRAIN_CTRL_G1 BIT(0) +#define MVEBU_COMPHY_TX_TRAIN_CTRL_GN1 BIT(1) +#define MVEBU_COMPHY_TX_TRAIN_CTRL_G0 BIT(2) #define MVEBU_COMPHY_FRAME_DETECT0(n) (0xa14 + (n) * 0x1000) #define MVEBU_COMPHY_FRAME_DETECT0_PATN(n) ((n) << 7) #define MVEBU_COMPHY_FRAME_DETECT3(n) (0xa20 + (n) * 0x1000) @@ -89,30 +152,121 @@ #define MVEBU_COMPHY_DME_ETH_MODE BIT(7) #define MVEBU_COMPHY_TRAINING0(n) (0xa68 + (n) * 0x1000) #define MVEBU_COMPHY_TRAINING0_P2P_HOLD BIT(15) +#define MVEBU_COMPHY_TRAINING4(n) (0xa78 + (n) * 0x1000) +#define MVEBU_COMPHY_TRAINING4_TIMER(n) ((n) << 0) #define MVEBU_COMPHY_TRAINING5(n) (0xaa4 + (n) * 0x1000) #define MVEBU_COMPHY_TRAINING5_RX_TIMER(n) ((n) << 0) +#define MVEBU_COMPHY_TRAINING5_START_SQ_EN BIT(11) +#define MVEBU_COMPHY_TRAINING5_FRM_DET_EN BIT(12) +#define MVEBU_COMPHY_TRAINING5_FRM_LOCK_EN BIT(13) +#define MVEBU_COMPHY_TRAINING5_WAIT_TIME_EN BIT(14) #define MVEBU_COMPHY_TX_TRAIN_PRESET(n) (0xb1c + (n) * 0x1000) +#define MVEBU_COMPHY_TX_TRAIN_CHK_INIT BIT(4) +#define MVEBU_COMPHY_TX_TRAIN_COEF_FM_PIN_PCIE3 BIT(7) #define MVEBU_COMPHY_TX_TRAIN_PRESET_16B_AUTO_EN BIT(8) #define MVEBU_COMPHY_TX_TRAIN_PRESET_PRBS11 BIT(9) +#define MVEBU_COMPHY_CDR_CONTROL(n) (0xc18 + (n) * 0x1000) +#define MVEBU_COMPHY_CDR_CONTROL_RX_MAX_DFE_ADAPT_1(n) ((n) << 12) +#define MVEBU_COMPHY_CDR_CONTROL_MAX_DFE_ADAPT_0(n) ((n) << 9) +#define MVEBU_COMPHY_CDR_CONTROL_MAX_DFE_ADAPT_1(n) ((n) << 6) +#define MVEBU_COMPHY_TX_TRAINING11(n) (0xc38 + (n) * 0x1000) +#define MVEBU_COMPHY_TX_TRAINING11_CHECK_MODE BIT(6) +#define MVEBU_COMPHY_TX_TRAINING11_PRESET_NUM(n) ((n) << 10) +#define MVEBU_COMPHY_TX_TRAINING11_PRESET_EN BIT(15) #define MVEBU_COMPHY_GEN1_S3(n) (0xc40 + (n) * 0x1000) +#define MVEBU_COMPHY_GEN1_S3_FFE_CAP_SEL(n) ((n) << 0) +#define MVEBU_COMPHY_GEN1_S3_FFE_RES_SEL(n) ((n) << 4) +#define MVEBU_COMPHY_GEN1_S3_SETTING_FORCE BIT(7) #define MVEBU_COMPHY_GEN1_S3_FBCK_SEL BIT(9) +#define MVEBU_COMPHY_GEN1_S3_FFE_DEG_RES_LVL(n) ((n) << 12) +#define MVEBU_COMPHY_GEN1_S3_FFE_LOAD_RES_LVL(n) ((n) << 14) #define MVEBU_COMPHY_GEN1_S4(n) (0xc44 + (n) * 0x1000) #define MVEBU_COMPHY_GEN1_S4_DFE_RES(n) ((n) << 8) +#define MVEBU_COMPHY_GEN2_S4(n) (0xc4c + (n) * 0x1000) +#define MVEBU_COMPHY_GEN2_S4_DFE_RES(n) ((n) << 8) +#define MVEBU_COMPHY_GEN3_S3(n) (0xc50 + (n) * 0x1000) +#define MVEBU_COMPHY_GEN3_S3_FFE_CAP_SEL(n) ((n) << 0) +#define MVEBU_COMPHY_GEN3_S3_FFE_RES_SEL(n) ((n) << 4) +#define MVEBU_COMPHY_GEN3_S3_SETTING_FORCE BIT(7) +#define MVEBU_COMPHY_GEN3_S3_FBCK_SEL BIT(9) +#define MVEBU_COMPHY_GEN3_S3_FFE_DEG_RES_LVL(n) ((n) << 12) +#define MVEBU_COMPHY_GEN3_S3_FFE_LOAD_RES_LVL(n) ((n) << 14) +#define MVEBU_COMPHY_GEN3_S4(n) (0xc54 + (n) * 0x1000) +#define MVEBU_COMPHY_GEN3_S4_DFE_RES(n) ((n) << 8) #define MVEBU_COMPHY_TX_PRESET(n) (0xc68 + (n) * 0x1000) #define MVEBU_COMPHY_TX_PRESET_INDEX(n) ((n) << 0) +#define MVEBU_COMPHY_DFE_CTRL(n) (0xc70 + (n) * 0x1000) +#define MVEBU_COMPHY_DFE_CTRL_TX_MAX_DFE_ADAPT(n) ((n) << 14) +#define MVEBU_COMPHY_DFE_CTRL_28(n) (0xc9c + (n) * 0x1000) +#define MVEBU_COMPHY_DFE_CTRL_28_PIPE4 BIT(7) #define MVEBU_COMPHY_GEN1_S5(n) (0xd38 + (n) * 0x1000) #define MVEBU_COMPHY_GEN1_S5_ICP(n) ((n) << 0) +#define MVEBU_COMPHY_GEN3_S5(n) (0xd48 + (n) * 0x1000) +#define MVEBU_COMPHY_GEN3_S5_ICP(n) ((n) << 0) +#define MVEBU_COMPHY_LANE_CFG0(n) (0xe00 + (n) * 0x1000) +#define MVEBU_COMPHY_LANE_CFG0_PRD_TXEEMPH0 BIT(0) +#define MVEBU_COMPHY_LANE_STATUS0(n) (0xe0c + (n) * 0x1000) +#define MVEBU_COMPHY_LANE_STATUS0_PCLK_EN BIT(0) +#define MVEBU_COMPHY_LANE_CFG4(n) (0xe20 + (n) * 0x1000) +#define MVEBU_COMPHY_LANE_CFG4_DFE_CTRL(n) ((n) << 0) +#define MVEBU_COMPHY_LANE_CFG4_DFE_EN_SEL BIT(3) +#define MVEBU_COMPHY_LANE_CFG4_DFE_OVER BIT(6) +#define MVEBU_COMPHY_LANE_CFG4_DFE_SSC BIT(7) +#define MVEBU_COMPHY_EQ_CONFIG0(n) (0xe9c + (n) * 0x1000) +#define MVEBU_COMPHY_EQ_CONFIG0_RC_MODE BIT(12) +#define MVEBU_COMPHY_LANE_EQ_CFG1(n) (0xea0 + (n) * 0x1000) +#define MVEBU_COMPHY_LANE_EQ_CFG1_UPDATE_POLARITY BIT(12) +#define MVEBU_COMPHY_LANE_EQ_REMOTE_CFG(n) (0xef8 + (n) * 0x1000) +#define MVEBU_COMPHY_LANE_EQ_REMOTE_CFG_DIRN_OVERRIDE BIT(0) +#define MVEBU_COMPHY_LANE_EQ_REMOTE_CFG_ONLY_MODE BIT(1) +#define MVEBU_COMPHY_LANE_EQ_REMOTE_CFG_PRESET_VECTOR(n) ((n) << 2) +#define MVEBU_COMPHY_PIPE_RST_CLK_CTRL(n) (0xf04 + (n) * 0x1000) +#define MVEBU_COMPHY_PIPE_RST_CLK_CTRL_RST BIT(0) +#define MVEBU_COMPHY_PIPE_RST_CLK_CTRL_FIXED_PCLK BIT(2) +#define MVEBU_COMPHY_PIPE_RST_CLK_CTRL_PIPE_WIDTH BIT(3) +#define MVEBU_COMPHY_PIPE_RST_CLK_CTRL_FREQ_SEL BIT(9) +#define MVEBU_COMPHY_MODE_CTRL(n) (0xf08 + (n) * 0x1000) +#define MVEBU_COMPHY_MODE_CTRL_MODE_MARGIN BIT(2) +#define MVEBU_COMPHY_PIPE_CLK_SRC_LO(n) (0xf0c + (n) * 0x1000) +#define MVEBU_COMPHY_PIPE_CLK_SRC_LO_PERIOD_SEL BIT(1) +#define MVEBU_COMPHY_PIPE_CLK_SRC_LO_PERIOD_SCALE(n) ((n) << 2) +#define MVEBU_COMPHY_PIPE_CLK_SRC_LO_PLL_RDY_DL(n) ((n) << 5) +#define MVEBU_COMPHY_PIPE_CLK_SRC_HI(n) (0xf10 + (n) * 0x1000) +#define MVEBU_COMPHY_PIPE_CLK_SRC_HI_LANE_START BIT(0) +#define MVEBU_COMPHY_PIPE_CLK_SRC_HI_LANE_BREAK BIT(1) +#define MVEBU_COMPHY_PIPE_CLK_SRC_HI_LANE_MASTER BIT(2) +#define MVEBU_COMPHY_PIPE_CLK_SRC_HI_MODE_PIPE BIT(7) +#define MVEBU_COMPHY_PIPE_PM_CTRL(n) (0xf40 + (n) * 0x1000) +#define MVEBU_COMPHY_PIPE_PM_CTRL_RDLOZ_WAIT(n) ((n) << 0) /* Relative to priv->regmap */ #define MVEBU_COMPHY_CONF1(n) (0x1000 + (n) * 0x28) #define MVEBU_COMPHY_CONF1_PWRUP BIT(1) #define MVEBU_COMPHY_CONF1_USB_PCIE BIT(2) /* 0: Ethernet/SATA */ +#define MVEBU_COMPHY_CONF1_POR BIT(14) +#define MVEBU_COMPHY_CONF1_CORE_RESET BIT(13) +#define MVEBU_COMPHY_CONF1_PHY_MODE_USB BIT(15) /* 1: USB */ #define MVEBU_COMPHY_CONF6(n) (0x1014 + (n) * 0x28) #define MVEBU_COMPHY_CONF6_40B BIT(18) #define MVEBU_COMPHY_SELECTOR 0x1140 #define MVEBU_COMPHY_SELECTOR_PHY(n) ((n) * 0x4) #define MVEBU_COMPHY_PIPE_SELECTOR 0x1144 #define MVEBU_COMPHY_PIPE_SELECTOR_PIPE(n) ((n) * 0x4) +#define MVEBU_COMPHY_SD_CTRL1 (0x1148) +#define MVEBU_COMPHY_SD_CTRL1_PHY0_3_MASK 0xffff +#define MVEBU_COMPHY_SD_CTRL1_PHY0_1_MASK 0x00ff +#define MVEBU_COMPHY_SD_CTRL1_PCIE_X2_EN BIT(25) +#define MVEBU_COMPHY_SD_CTRL1_PCIE_X4_EN BIT(24) + +/* Relative to priv->cp_mgmt_regmap */ +#define DEVICE_SAR0 0x200 +#define DEV_SAR0_PCIE1_CLK_CP0 BIT(3) +#define DEV_SAR0_PCIE0_CLK_CP0 BIT(2) +#define DEV_SAR0_PCIE1_CLK_CP1 BIT(1) +#define DEV_SAR0_PCIE0_CLK_CP1 BIT(0) +#define DEVICE_SAR1 0x204 +#define DFX_DEV_GEN_CTRL12 0x280 +#define DFX_DEV_GEN_CTRL12_CLK_SRC(n) ((n) << 7) #define MVEBU_COMPHY_LANES 6 #define MVEBU_COMPHY_PORTS 3 @@ -132,29 +286,105 @@ .mux = _mux, \ } +/* + * default values for 10GKR comphys amplitudes/emphasises. Those work + * on the A8K DB board, but most likely won't be suitable for other + * boards. + * + * The Marvell A8K DB board has a fairly long trace length from the + * CPU to the SFP cage, and a connector in between, therefore it needs + * fairly bosted up amplitude and emphasis settings in order to get a + * descent eye diagram. + * + * On other designs with shorter traces lengths this will most likely + * result in a fairly large overshoot of the signal and bad signal + * integrity. + */ +#define DEFAULT_GEN1_S0_AMP 0x1c +#define DEFAULT_GEN1_S0_EMPH 0xe +#define DEFAULT_GEN1_S2_EMPH 0x0 + +#define KR_DEFAULT_FFE_CAP_SEL 0xe +#define KR_DEFAULT_FFE_RES_SEL 0x4 +#define KR_DEFAULT_DFE_RES 0x1 +#define KR_DEFAULT_PHASE_OFFSET 0x60 + +/* + * default values for SATA comphys amplitudes/emphasises and DFE + * resolutions. Those work on the A8K DB board, but most likely won't + * be suitable for other boards. + */ +#define SATA_DEFAULT_GEN3_S0_AMP 0x1e +#define SATA_DEFAULT_GEN3_S0_EMPH 0x06 +#define SATA_DEFAULT_GEN3_S4_DFE_RES 0x2 +#define SATA_DEFAULT_PHASE_OFFSET 0x61 + static const struct mvebu_comhy_conf mvebu_comphy_cp110_modes[] = { /* lane 0 */ MVEBU_COMPHY_CONF(0, 1, PHY_MODE_SGMII, 0x1), + MVEBU_COMPHY_CONF(0, 1, PHY_MODE_HS_SGMII, 0x1), + MVEBU_COMPHY_CONF(0, 1, PHY_MODE_SATA, 0x4), /* lane 1 */ MVEBU_COMPHY_CONF(1, 2, PHY_MODE_SGMII, 0x1), + MVEBU_COMPHY_CONF(1, 2, PHY_MODE_HS_SGMII, 0x1), + MVEBU_COMPHY_CONF(1, 0, PHY_MODE_SATA, 0x4), /* lane 2 */ MVEBU_COMPHY_CONF(2, 0, PHY_MODE_SGMII, 0x1), + MVEBU_COMPHY_CONF(2, 0, PHY_MODE_HS_SGMII, 0x1), MVEBU_COMPHY_CONF(2, 0, PHY_MODE_10GKR, 0x1), + MVEBU_COMPHY_CONF(2, 0, PHY_MODE_SATA, 0x4), /* lane 3 */ MVEBU_COMPHY_CONF(3, 1, PHY_MODE_SGMII, 0x2), + MVEBU_COMPHY_CONF(3, 1, PHY_MODE_HS_SGMII, 0x2), + MVEBU_COMPHY_CONF(3, 1, PHY_MODE_SATA, 0x4), /* lane 4 */ MVEBU_COMPHY_CONF(4, 0, PHY_MODE_SGMII, 0x2), + MVEBU_COMPHY_CONF(4, 0, PHY_MODE_HS_SGMII, 0x2), MVEBU_COMPHY_CONF(4, 0, PHY_MODE_10GKR, 0x2), MVEBU_COMPHY_CONF(4, 1, PHY_MODE_SGMII, 0x1), + MVEBU_COMPHY_CONF(4, 1, PHY_MODE_HS_SGMII, 0x1), /* lane 5 */ MVEBU_COMPHY_CONF(5, 2, PHY_MODE_SGMII, 0x1), + MVEBU_COMPHY_CONF(5, 2, PHY_MODE_HS_SGMII, 0x1), + MVEBU_COMPHY_CONF(5, 1, PHY_MODE_SATA, 0x4), +}; + +static const struct mvebu_comhy_conf mvebu_comphy_cp110_pipe_modes[] = { + /* lane 0 */ + MVEBU_COMPHY_CONF(0, 0, PHY_MODE_PCIE, 0x4), + + /* lane 1 */ + MVEBU_COMPHY_CONF(1, 0, PHY_MODE_USB_HOST, 0x1), + MVEBU_COMPHY_CONF(1, 0, PHY_MODE_USB_DEVICE, 0x2), + MVEBU_COMPHY_CONF(1, 0, PHY_MODE_PCIE, 0x4), + + /* lane 2 */ + MVEBU_COMPHY_CONF(2, 0, PHY_MODE_USB_HOST, 0x1), + MVEBU_COMPHY_CONF(2, 0, PHY_MODE_PCIE, 0x4), + + /* lane 3 */ + MVEBU_COMPHY_CONF(3, 1, PHY_MODE_USB_HOST, 0x1), + MVEBU_COMPHY_CONF(3, 0, PHY_MODE_PCIE, 0x4), + + /* lane 4 */ + MVEBU_COMPHY_CONF(4, 1, PHY_MODE_USB_HOST, 0x1), + MVEBU_COMPHY_CONF(4, 0, PHY_MODE_USB_DEVICE, 0x2), + MVEBU_COMPHY_CONF(4, 1, PHY_MODE_PCIE, 0x4), + + /* lane 5 */ + MVEBU_COMPHY_CONF(5, 2, PHY_MODE_PCIE, 0x4), }; struct mvebu_comphy_priv { void __iomem *base; struct regmap *regmap; + struct regmap *sar_regmap; + struct regmap *cp_mgmt_regmap; struct device *dev; int modes[MVEBU_COMPHY_LANES]; + + struct clk *gop_clk; + struct clk *mg_clk; }; struct mvebu_comphy_lane { @@ -162,6 +392,23 @@ unsigned id; enum phy_mode mode; int port; + + u32 kr_gen1_s0_amplitude; + u32 kr_gen1_s0_emphasis; + u32 kr_gen1_s2_emphasis; + + u32 kr_ffe_cap_sel; + u32 kr_ffe_res_sel; + u32 kr_dfe_res; + u32 kr_phase_offset; + + bool rx_swap_polarity; + bool tx_swap_polarity; + + u32 sata_gen3_s0_amplitude; + u32 sata_gen3_s0_emphasis; + u32 sata_gen3_s4_dfe_res; + u32 sata_phase_offset; }; static int mvebu_comphy_get_mux(int lane, int port, enum phy_mode mode) @@ -185,6 +432,27 @@ return mvebu_comphy_cp110_modes[i].mux; } +static int mvebu_comphy_get_pipe_mux(int lane, int port, enum phy_mode mode) +{ + int i, n = ARRAY_SIZE(mvebu_comphy_cp110_pipe_modes); + + /* Unused PHY mux value is 0x0 */ + if (mode == PHY_MODE_INVALID) + return 0; + + for (i = 0; i < n; i++) { + if (mvebu_comphy_cp110_pipe_modes[i].lane == lane && + mvebu_comphy_cp110_pipe_modes[i].port == port && + mvebu_comphy_cp110_pipe_modes[i].mode == mode) + break; + } + + if (i == n) + return -EINVAL; + + return mvebu_comphy_cp110_pipe_modes[i].mux; +} + static void mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane, enum phy_mode mode) { @@ -207,6 +475,10 @@ if (mode == PHY_MODE_10GKR) val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xe) | MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0xe); + else if (mode == PHY_MODE_HS_SGMII) + val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0x8) | + MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0x8) | + MVEBU_COMPHY_SERDES_CFG0_HALF_BUS; else if (mode == PHY_MODE_SGMII) val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0x6) | MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0x6) | @@ -255,6 +527,260 @@ writel(val, priv->base + MVEBU_COMPHY_LOOPBACK(lane->id)); } +static void mvebu_comphy_sata_init_reset(struct mvebu_comphy_lane *lane) +{ + struct mvebu_comphy_priv *priv = lane->priv; + u32 val; + + /* RFU configurations - hard reset comphy */ + regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val); + val &= ~MVEBU_COMPHY_CONF1_USB_PCIE; + val &= ~MVEBU_COMPHY_CONF1_POR; + val &= ~MVEBU_COMPHY_CONF1_CORE_RESET; + val |= MVEBU_COMPHY_CONF1_PWRUP; + regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val); + + /* Set data width 40Bit - SATA mode only */ + regmap_read(priv->regmap, MVEBU_COMPHY_CONF6(lane->id), &val); + val |= MVEBU_COMPHY_CONF6_40B; + regmap_write(priv->regmap, MVEBU_COMPHY_CONF6(lane->id), val); + +#if 0 + /* + * reset serdes, not part of Marvell LSP. + */ + val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); + val &= ~(MVEBU_COMPHY_SERDES_CFG1_RESET | + MVEBU_COMPHY_SERDES_CFG1_CORE_RESET | + MVEBU_COMPHY_SERDES_CFG1_RF_RESET); + writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); +#endif + /* de-assert reset */ + val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); + val |= MVEBU_COMPHY_SERDES_CFG1_RESET | + MVEBU_COMPHY_SERDES_CFG1_CORE_RESET; + writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); + + /* wait until clocks are ready */ + mdelay(10); + + /* Set reference clock to comes from group 1 - chose 25Mhz */ + val = readl(priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id)); + val &= ~MVEBU_COMPHY_MISC_CTRL0_REFCLK_SEL; + writel(val,priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id)); + + /* power and pll selection */ + val = readl(priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id)); + val &= ~(MVEBU_COMPHY_PWRPLL_CTRL_RFREQ(0x1f) | + MVEBU_COMPHY_PWRPLL_PHY_MODE(0x7)); + /* Reference frequency select set 1 (for SATA = 25Mhz) */ + /* PHY mode select (set SATA = 0x0 */ + val |= MVEBU_COMPHY_PWRPLL_CTRL_RFREQ(0x1) | + MVEBU_COMPHY_PWRPLL_PHY_MODE(0x0); + writel(val, priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id)); + + /* Set max PHY generation setting - 6Gbps */ + val = readl(priv->base + MVEBU_COMPHY_INTERFACE(lane->id)); + val &= ~MVEBU_COMPHY_INTERFACE_GEN_MAX(0x3); + val |= MVEBU_COMPHY_INTERFACE_GEN_MAX(0x2); + writel(val, priv->base + MVEBU_COMPHY_INTERFACE(lane->id)); + + /* Set select data width 40Bit (SEL_BITS[2:0]) */ + val = readl(priv->base + MVEBU_COMPHY_LOOPBACK(lane->id)); + val &= ~MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(0x7); + val |= MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(0x2); + writel(val, priv->base + MVEBU_COMPHY_LOOPBACK(lane->id)); +} + +static void mvebu_comphy_usb3_init_reset(struct mvebu_comphy_lane *lane) +{ + struct mvebu_comphy_priv *priv = lane->priv; + u32 val; + + /* RFU configurations - hard reset comphy */ + regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val); + val &= ~MVEBU_COMPHY_CONF1_POR; + val &= ~MVEBU_COMPHY_CONF1_CORE_RESET; + val |= MVEBU_COMPHY_CONF1_PWRUP; + val |= MVEBU_COMPHY_CONF1_PHY_MODE_USB; + val |= MVEBU_COMPHY_CONF1_USB_PCIE; + regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val); + + /* release from hard reset */ + regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val); + val |= MVEBU_COMPHY_CONF1_POR; + val |= MVEBU_COMPHY_CONF1_CORE_RESET; + regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val); + + /* wait until clocks are ready */ + mdelay(1); + + /* Set PIPE soft reset */ + val = readl(priv->base + MVEBU_COMPHY_PIPE_RST_CLK_CTRL(lane->id)); + val |= MVEBU_COMPHY_PIPE_RST_CLK_CTRL_RST; + val &= ~MVEBU_COMPHY_PIPE_RST_CLK_CTRL_FIXED_PCLK; + val &= ~MVEBU_COMPHY_PIPE_RST_CLK_CTRL_PIPE_WIDTH; + val &= ~MVEBU_COMPHY_PIPE_RST_CLK_CTRL_FREQ_SEL; + writel(val, priv->base + MVEBU_COMPHY_PIPE_RST_CLK_CTRL(lane->id)); + + /* Set PLL ready delay for 0x2 */ + val = readl(priv->base + MVEBU_COMPHY_PIPE_CLK_SRC_LO(lane->id)); + val &= ~MVEBU_COMPHY_PIPE_CLK_SRC_LO_PLL_RDY_DL(0x7); + val |= MVEBU_COMPHY_PIPE_CLK_SRC_LO_PLL_RDY_DL(0x2); + writel(val, priv->base + MVEBU_COMPHY_PIPE_CLK_SRC_LO(lane->id)); + + /* Set reference clock to come from group 1 - 25Mhz */ + val = readl(priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id)); + val &= ~MVEBU_COMPHY_MISC_CTRL0_REFCLK_SEL; + writel(val, priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id)); + + /* power and pll selection */ + val = readl(priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id)); + val &= ~(MVEBU_COMPHY_PWRPLL_CTRL_RFREQ(0x1f) | + MVEBU_COMPHY_PWRPLL_PHY_MODE(0x7)); + val |= MVEBU_COMPHY_PWRPLL_CTRL_RFREQ(0x2) | + MVEBU_COMPHY_PWRPLL_PHY_MODE(0x5); + writel(val, priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id)); + + + /* Set the amount of time spent in the LoZ state - set for 0x7 */ + val = readl(priv->base + MVEBU_COMPHY_PIPE_PM_CTRL(lane->id)); + val &= ~MVEBU_COMPHY_PIPE_PM_CTRL_RDLOZ_WAIT(0xff); + val |= MVEBU_COMPHY_PIPE_PM_CTRL_RDLOZ_WAIT(0x7); + writel(val, priv->base + MVEBU_COMPHY_PIPE_PM_CTRL(lane->id)); + + /* Set max PHY generation setting - 5Gbps */ + val = readl(priv->base + MVEBU_COMPHY_INTERFACE(lane->id)); + val &= ~MVEBU_COMPHY_INTERFACE_GEN_MAX(0x3); + val |= MVEBU_COMPHY_INTERFACE_GEN_MAX(0x1); + writel(val, priv->base + MVEBU_COMPHY_INTERFACE(lane->id)); + + /* Set select data width 20Bit (SEL_BITS[2:0]) */ + val = readl(priv->base + MVEBU_COMPHY_LOOPBACK(lane->id)); + val &= ~MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(0x7); + val |= MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(0x1); + writel(val, priv->base + MVEBU_COMPHY_LOOPBACK(lane->id)); +} + +static void mvebu_comphy_pcie_init_reset(struct mvebu_comphy_lane *lane, + int pcie_clk_config, int pcie_width) +{ + struct mvebu_comphy_priv *priv = lane->priv; + u32 val; + + /* RFU configurations - hard reset comphy */ + regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val); + val &= ~MVEBU_COMPHY_CONF1_POR; + val &= ~MVEBU_COMPHY_CONF1_CORE_RESET; + val &= ~MVEBU_COMPHY_CONF1_PHY_MODE_USB; + val |= MVEBU_COMPHY_CONF1_PWRUP; + val |= MVEBU_COMPHY_CONF1_USB_PCIE; + regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val); + + /* release from hard reset */ + regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val); + val |= MVEBU_COMPHY_CONF1_POR; + val |= MVEBU_COMPHY_CONF1_CORE_RESET; + regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val); + + /* wait until clocks are ready */ + mdelay(1); + + /* Start comphy Configuration */ + val = readl(priv->base + MVEBU_COMPHY_PIPE_RST_CLK_CTRL(lane->id)); + val |= MVEBU_COMPHY_PIPE_RST_CLK_CTRL_RST; + val |= MVEBU_COMPHY_PIPE_RST_CLK_CTRL_FIXED_PCLK; + val &= ~MVEBU_COMPHY_PIPE_RST_CLK_CTRL_PIPE_WIDTH; + val &= ~MVEBU_COMPHY_PIPE_RST_CLK_CTRL_FREQ_SEL; + writel(val, priv->base + MVEBU_COMPHY_PIPE_RST_CLK_CTRL(lane->id)); + + /* Set PLL ready delay for 0x2 */ + val = readl(priv->base + MVEBU_COMPHY_PIPE_CLK_SRC_LO(lane->id)); + val &= ~MVEBU_COMPHY_PIPE_CLK_SRC_LO_PLL_RDY_DL(0x7); + val |= MVEBU_COMPHY_PIPE_CLK_SRC_LO_PLL_RDY_DL(0x2); + if (pcie_width > 1) { + val |= MVEBU_COMPHY_PIPE_CLK_SRC_LO_PERIOD_SEL; + val &= ~MVEBU_COMPHY_PIPE_CLK_SRC_LO_PERIOD_SCALE(0x3); + val |= MVEBU_COMPHY_PIPE_CLK_SRC_LO_PERIOD_SCALE(0x1); + } + writel(val, priv->base + MVEBU_COMPHY_PIPE_CLK_SRC_LO(lane->id)); + + /* Set PIPE mode interface to PCIe3 - 0x1 & set lane order */ + val = readl(priv->base + MVEBU_COMPHY_PIPE_CLK_SRC_HI(lane->id)); + val |= MVEBU_COMPHY_PIPE_CLK_SRC_HI_MODE_PIPE; + if (pcie_width > 1) { + if (lane->id == 0) { + val |= MVEBU_COMPHY_PIPE_CLK_SRC_HI_LANE_START; + val |= MVEBU_COMPHY_PIPE_CLK_SRC_HI_LANE_MASTER; + } else { + val &= ~MVEBU_COMPHY_PIPE_CLK_SRC_HI_LANE_START; + val &= ~MVEBU_COMPHY_PIPE_CLK_SRC_HI_LANE_MASTER; + } + if (lane->id == pcie_width - 1) + val |= MVEBU_COMPHY_PIPE_CLK_SRC_HI_LANE_BREAK; + else + val &= ~MVEBU_COMPHY_PIPE_CLK_SRC_HI_LANE_BREAK; + } + writel(val, priv->base + MVEBU_COMPHY_PIPE_CLK_SRC_HI(lane->id)); + + /* Config update polarity equalization */ + val = readl(priv->base + MVEBU_COMPHY_LANE_EQ_CFG1(lane->id)); + val |= MVEBU_COMPHY_LANE_EQ_CFG1_UPDATE_POLARITY; + writel(val, priv->base + MVEBU_COMPHY_LANE_EQ_CFG1(lane->id)); + + /* Set PIPE version 4 to mode enable */ + val = readl(priv->base + MVEBU_COMPHY_DFE_CTRL_28(lane->id)); + val |= MVEBU_COMPHY_DFE_CTRL_28_PIPE4; + writel(val, priv->base + MVEBU_COMPHY_DFE_CTRL_28(lane->id)); + + val = readl(priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id)); + val &= ~MVEBU_COMPHY_MISC_CTRL0_TXDCLK_2X; + val |= MVEBU_COMPHY_MISC_CTRL0_CLK500M_EN; + val |= MVEBU_COMPHY_MISC_CTRL0_ICP_FORCE; + if (pcie_clk_config) { + val &= ~MVEBU_COMPHY_MISC_CTRL0_REFCLK_SEL; + val |= MVEBU_COMPHY_MISC_CTRL0_CLK100M_125M; + } else { + val |= MVEBU_COMPHY_MISC_CTRL0_REFCLK_SEL; + } + writel(val, priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id)); + + val = readl(priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id)); + val &= ~MVEBU_COMPHY_PWRPLL_CTRL_RFREQ(0x1f); + val &= ~MVEBU_COMPHY_PWRPLL_PHY_MODE(0x7); + if (pcie_clk_config) + val |= MVEBU_COMPHY_PWRPLL_CTRL_RFREQ(0x2); + else + val |= MVEBU_COMPHY_PWRPLL_CTRL_RFREQ(0x0); + val |= MVEBU_COMPHY_PWRPLL_PHY_MODE(0x3); + writel(val, priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id)); + + if (pcie_width > 1) { + /* reference clock alignment */ + val = readl(priv->base + MVEBU_COMPHY_LANE_ALIGN(lane->id)); + val &= ~MVEBU_COMPHY_LANE_ALIGN_BIT; + writel(val, priv->base + MVEBU_COMPHY_LANE_ALIGN(lane->id)); + } + + /* + * Set the amount of time spent in the LoZ state - set for 0x7 + * only if the PCIe clock is output + */ + if (pcie_clk_config) { + val = readl(priv->base + MVEBU_COMPHY_PIPE_PM_CTRL(lane->id)); + val &= ~MVEBU_COMPHY_PIPE_PM_CTRL_RDLOZ_WAIT(0xff); + val |= MVEBU_COMPHY_PIPE_PM_CTRL_RDLOZ_WAIT(0x7); + writel(val, priv->base + MVEBU_COMPHY_PIPE_PM_CTRL(lane->id)); + } + + val = readl(priv->base + MVEBU_COMPHY_INTERFACE(lane->id)); + val &= ~MVEBU_COMPHY_INTERFACE_GEN_MAX(0x3); + val |= MVEBU_COMPHY_INTERFACE_GEN_MAX(0x2); + val |= MVEBU_COMPHY_INTERFACE_DET_BYPASS; + val |= MVEBU_COMPHY_INTERFACE_LINK_TRAIN; + writel(val, priv->base + MVEBU_COMPHY_INTERFACE(lane->id)); +} + static int mvebu_comphy_init_plls(struct mvebu_comphy_lane *lane, enum phy_mode mode) { @@ -297,13 +823,13 @@ return 0; } -static int mvebu_comphy_set_mode_sgmii(struct phy *phy) +static int mvebu_comphy_set_mode_sgmii(struct phy *phy, enum phy_mode mode) { struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); struct mvebu_comphy_priv *priv = lane->priv; u32 val; - mvebu_comphy_ethernet_init_reset(lane, PHY_MODE_SGMII); + mvebu_comphy_ethernet_init_reset(lane, mode); val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); val &= ~MVEBU_COMPHY_RX_CTRL1_CLK8T_EN; @@ -321,7 +847,9 @@ val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); val &= ~MVEBU_COMPHY_GEN1_S0_TX_EMPH(0xf); - val |= MVEBU_COMPHY_GEN1_S0_TX_EMPH(0x1); + /* set it back to hardware default value to fix unstable bcm + * link on fbx proto */ + val |= MVEBU_COMPHY_GEN1_S0_TX_EMPH(0x9); writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); return mvebu_comphy_init_plls(lane, PHY_MODE_SGMII); @@ -344,6 +872,17 @@ val |= MVEBU_COMPHY_DLT_CTRL_DTL_FLOOP_EN; writel(val, priv->base + MVEBU_COMPHY_DLT_CTRL(lane->id)); + printk("10gkr rx settings: 0x%x 0x%x 0x%x 0x%x\n", + lane->kr_ffe_cap_sel, lane->kr_ffe_res_sel, + lane->kr_dfe_res, lane->kr_phase_offset); + val = readl(priv->base + MVEBU_COMPHY_GEN1_S3(lane->id)); + val |= MVEBU_COMPHY_GEN1_S3_SETTING_FORCE; + val &= ~MVEBU_COMPHY_GEN1_S3_FFE_CAP_SEL(0xf); + val &= ~MVEBU_COMPHY_GEN1_S3_FFE_RES_SEL(0x7); + val |= MVEBU_COMPHY_GEN1_S3_FFE_CAP_SEL(lane->kr_ffe_cap_sel); + val |= MVEBU_COMPHY_GEN1_S3_FFE_RES_SEL(lane->kr_ffe_res_sel); + writel(val, priv->base + MVEBU_COMPHY_GEN1_S3(lane->id)); + /* Speed divider */ val = readl(priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id)); val |= MVEBU_COMPHY_SPEED_DIV_TX_FORCE; @@ -361,12 +900,13 @@ val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); val &= ~(MVEBU_COMPHY_GEN1_S0_TX_AMP(0x1f) | MVEBU_COMPHY_GEN1_S0_TX_EMPH(0xf)); - val |= MVEBU_COMPHY_GEN1_S0_TX_AMP(0x1c) | - MVEBU_COMPHY_GEN1_S0_TX_EMPH(0xe); + val |= MVEBU_COMPHY_GEN1_S0_TX_AMP(lane->kr_gen1_s0_amplitude) | + MVEBU_COMPHY_GEN1_S0_TX_EMPH(lane->kr_gen1_s0_emphasis); writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); val = readl(priv->base + MVEBU_COMPHY_GEN1_S2(lane->id)); val &= ~MVEBU_COMPHY_GEN1_S2_TX_EMPH(0xf); + val |= MVEBU_COMPHY_GEN1_S2_TX_EMPH(lane->kr_gen1_s2_emphasis); val |= MVEBU_COMPHY_GEN1_S2_TX_EMPH_EN; writel(val, priv->base + MVEBU_COMPHY_GEN1_S2(lane->id)); @@ -375,6 +915,25 @@ MVEBU_COMPHY_TX_SLEW_RATE_SLC(0x3f); writel(val, priv->base + MVEBU_COMPHY_TX_SLEW_RATE(lane->id)); + /* phase offset */ + val = readl(priv->base + MVEBU_COMPHY_PHASE_CTRL(lane->id)); + val &= ~MVEBU_COMPHY_PHASE_CTRL_OS_PH_OFF(0x7f); + val |= MVEBU_COMPHY_PHASE_CTRL_OS_PH_OFF(lane->kr_phase_offset); + val |= MVEBU_COMPHY_PHASE_CTRL_OS_PH_OFF_FORCE; + val &= ~MVEBU_COMPHY_PHASE_CTRL_OS_PH_OFF_VALID; + writel(val, priv->base + MVEBU_COMPHY_PHASE_CTRL(lane->id)); + + /* + * phase offset sampled on rising edge of OS_PH_OFF_VALID. + */ + val = readl(priv->base + MVEBU_COMPHY_PHASE_CTRL(lane->id)); + val |= MVEBU_COMPHY_PHASE_CTRL_OS_PH_OFF_VALID; + writel(val, priv->base + MVEBU_COMPHY_PHASE_CTRL(lane->id)); + + val = readl(priv->base + MVEBU_COMPHY_PHASE_CTRL(lane->id)); + val &= ~MVEBU_COMPHY_PHASE_CTRL_OS_PH_OFF_VALID; + writel(val, priv->base + MVEBU_COMPHY_PHASE_CTRL(lane->id)); + /* Impedance calibration */ val = readl(priv->base + MVEBU_COMPHY_IMP_CAL(lane->id)); val &= ~MVEBU_COMPHY_IMP_CAL_TX_EXT(0x1f); @@ -404,7 +963,7 @@ val = readl(priv->base + MVEBU_COMPHY_GEN1_S4(lane->id)); val &= ~MVEBU_COMPHY_GEN1_S4_DFE_RES(0x3); - val |= MVEBU_COMPHY_GEN1_S4_DFE_RES(0x1); + val |= MVEBU_COMPHY_GEN1_S4_DFE_RES(lane->kr_dfe_res); writel(val, priv->base + MVEBU_COMPHY_GEN1_S4(lane->id)); val = readl(priv->base + MVEBU_COMPHY_GEN1_S3(lane->id)); @@ -466,19 +1025,593 @@ return mvebu_comphy_init_plls(lane, PHY_MODE_10GKR); } +static int mvebu_comphy_set_mode_sata(struct phy *phy) +{ + struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); + struct mvebu_comphy_priv *priv = lane->priv; + u32 val; + + mvebu_comphy_sata_init_reset(lane); + + /* G1 Settings */ + val = readl(priv->base + MVEBU_COMPHY_GEN1_S1(lane->id)); + val &= ~(MVEBU_COMPHY_GEN1_S1_RX_MUL_PI(0x7) | + MVEBU_COMPHY_GEN1_S1_RX_MUL_PF(0x7) | + MVEBU_COMPHY_GEN1_S1_RX_MUL_FI(0x3) | + MVEBU_COMPHY_GEN1_S1_RX_MUL_FF(0x3) | + MVEBU_COMPHY_GEN1_S1_RX_DIV(0x3)); + val |= MVEBU_COMPHY_GEN1_S1_RX_MUL_PI(0x0) | + MVEBU_COMPHY_GEN1_S1_RX_MUL_PF(0x1) | + MVEBU_COMPHY_GEN1_S1_RX_MUL_FI(0x0) | + MVEBU_COMPHY_GEN1_S1_RX_MUL_FF(0x3) | + MVEBU_COMPHY_GEN1_S1_RX_DIV(0x1); + writel(val, priv->base + MVEBU_COMPHY_GEN1_S1(lane->id)); + + val = readl(priv->base + MVEBU_COMPHY_GEN1_S3(lane->id)); + val &= ~(MVEBU_COMPHY_GEN1_S3_FFE_CAP_SEL(0xf) | + MVEBU_COMPHY_GEN1_S3_FFE_RES_SEL(0x7) | + MVEBU_COMPHY_GEN1_S3_FFE_DEG_RES_LVL(0x3) | + MVEBU_COMPHY_GEN1_S3_FFE_LOAD_RES_LVL(0x3)); + val |= MVEBU_COMPHY_GEN1_S3_SETTING_FORCE | + MVEBU_COMPHY_GEN1_S3_FFE_CAP_SEL(0xf) | + MVEBU_COMPHY_GEN1_S3_FFE_RES_SEL(0x2) | + MVEBU_COMPHY_GEN1_S3_FFE_DEG_RES_LVL(0x1) | + MVEBU_COMPHY_GEN1_S3_FFE_LOAD_RES_LVL(0x1); + writel(val, priv->base + MVEBU_COMPHY_GEN1_S3(lane->id)); + + /* G2 Settings */ + val = readl(priv->base + MVEBU_COMPHY_GEN2_S1(lane->id)); + val &= ~(MVEBU_COMPHY_GEN2_S1_RX_MUL_PI(0x7) | + MVEBU_COMPHY_GEN2_S1_RX_MUL_PF(0x7) | + MVEBU_COMPHY_GEN2_S1_RX_MUL_FI(0x3) | + MVEBU_COMPHY_GEN2_S1_RX_MUL_FF(0x3) | + MVEBU_COMPHY_GEN2_S1_RX_DIV(0x3)); + val |= MVEBU_COMPHY_GEN2_S1_RX_MUL_PI(0x0) | + MVEBU_COMPHY_GEN2_S1_RX_MUL_PF(0x1) | + MVEBU_COMPHY_GEN2_S1_RX_MUL_FI(0x0) | + MVEBU_COMPHY_GEN2_S1_RX_MUL_FF(0x3) | + MVEBU_COMPHY_GEN2_S1_RX_DIV(0x1); + writel(val, priv->base + MVEBU_COMPHY_GEN2_S1(lane->id)); + + /* G3 Settings */ + val = readl(priv->base + MVEBU_COMPHY_GEN3_S1(lane->id)); + val &= ~(MVEBU_COMPHY_GEN3_S1_RX_MUL_PI(0x7) | + MVEBU_COMPHY_GEN3_S1_RX_MUL_PF(0x7) | + MVEBU_COMPHY_GEN3_S1_RX_MUL_FI(0x3) | + MVEBU_COMPHY_GEN3_S1_RX_MUL_FF(0x3) | + MVEBU_COMPHY_GEN2_S1_RX_DIV(0x3) | + MVEBU_COMPHY_GEN3_S1_SMPL_INPX2_EN); + val |= MVEBU_COMPHY_GEN3_S1_RX_MUL_PI(0x2) | + MVEBU_COMPHY_GEN3_S1_RX_MUL_PF(0x2) | + MVEBU_COMPHY_GEN3_S1_RX_MUL_FI(0x3) | + MVEBU_COMPHY_GEN3_S1_RX_MUL_FF(0x3) | + MVEBU_COMPHY_GEN3_S1_RX_DIV(0x2) | + MVEBU_COMPHY_GEN3_S1_RX_DFE_EN; + writel(val, priv->base + MVEBU_COMPHY_GEN3_S1(lane->id)); + + /* DTL Control */ + val = readl(priv->base + MVEBU_COMPHY_DLT_CTRL(lane->id)); + val &= ~(MVEBU_COMPHY_DLT_CTRL_DTL_CLAMP_SEL(0x7) | + MVEBU_COMPHY_DLT_CTRL_DTL_CLK_MODE(0x3)); + val |= MVEBU_COMPHY_DLT_CTRL_DTL_DET_EN | + MVEBU_COMPHY_DLT_CTRL_DTL_PLOOP_EN | + MVEBU_COMPHY_DLT_CTRL_DTL_FLOOP_EN | + MVEBU_COMPHY_DLT_CTRL_DTL_CLAMP_SEL(0x1) | + MVEBU_COMPHY_DLT_CTRL_DTL_INPCLK_DIV_FORCE | + MVEBU_COMPHY_DLT_CTRL_DTL_CLK_MODE(0x1) | + MVEBU_COMPHY_DLT_CTRL_DTL_CLK_MODE_FORCE; + writel(val, priv->base + MVEBU_COMPHY_DLT_CTRL(lane->id)); + + /* Trigger sampler enable pulses */ + val = readl(priv->base + MVEBU_SP_CALIB(lane->id)); + val |= MVEBU_SP_CALIB_SAMPLER_EN; + writel(val, priv->base + MVEBU_SP_CALIB(lane->id)); + val = readl(priv->base + MVEBU_SP_CALIB(lane->id)); + val &= ~MVEBU_SP_CALIB_SAMPLER_EN; + writel(val, priv->base + MVEBU_SP_CALIB(lane->id)); + + /* VDD Calibration Control 3 */ + val = readl(priv->base + MVEBU_COMPHY_EXT_SELV(lane->id)); + val &= ~MVEBU_COMPHY_EXT_SELV_RX_SAMPL(0x1f); + val |= MVEBU_COMPHY_EXT_SELV_RX_SAMPL(0x10); + writel(val, priv->base + MVEBU_COMPHY_EXT_SELV(lane->id)); + + /* DFE Resolution Control */ + val = readl(priv->base + MVEBU_COMPHY_DFE_RES(lane->id)); + val |= MVEBU_COMPHY_DFE_RES_FORCE_GEN_TBL; + writel(val, priv->base + MVEBU_COMPHY_DFE_RES(lane->id)); + + /* DFE F3-F5 Coefficient Control */ + val = readl(priv->base + MVEBU_COMPHY_COEF(lane->id)); + val &= ~(MVEBU_COMPHY_COEF_DFE_EN | MVEBU_COMPHY_COEF_DFE_CTRL); + writel(val, priv->base + MVEBU_COMPHY_COEF(lane->id)); + + /* G3 Setting 3 */ + val = readl(priv->base + MVEBU_COMPHY_GEN3_S3(lane->id)); + val &= ~(MVEBU_COMPHY_GEN3_S3_FFE_CAP_SEL(0xf) | + MVEBU_COMPHY_GEN3_S3_FFE_RES_SEL(0x7) | + MVEBU_COMPHY_GEN3_S3_FFE_DEG_RES_LVL(0x3) | + MVEBU_COMPHY_GEN3_S3_FFE_LOAD_RES_LVL(0x3)); + val |= MVEBU_COMPHY_GEN3_S3_SETTING_FORCE | + MVEBU_COMPHY_GEN3_S3_FFE_CAP_SEL(0xf) | + MVEBU_COMPHY_GEN3_S3_FFE_RES_SEL(0x4) | + MVEBU_COMPHY_GEN3_S3_FFE_DEG_RES_LVL(0x1) | + MVEBU_COMPHY_GEN3_S3_FFE_LOAD_RES_LVL(0x3); + writel(val, priv->base + MVEBU_COMPHY_GEN3_S3(lane->id)); + + /* G3 Setting 4 */ + val = readl(priv->base + MVEBU_COMPHY_GEN3_S4(lane->id)); + val &= ~MVEBU_COMPHY_GEN3_S4_DFE_RES(0x3); + val |= MVEBU_COMPHY_GEN3_S4_DFE_RES(lane->sata_gen3_s4_dfe_res); + writel(val, priv->base + MVEBU_COMPHY_GEN3_S4(lane->id)); + + /* Offset Phase Control */ + val = readl(priv->base + MVEBU_COMPHY_PHASE_CTRL(lane->id)); + val &= ~MVEBU_COMPHY_PHASE_CTRL_OS_PH_OFF(0x7f); + val |= MVEBU_COMPHY_PHASE_CTRL_OS_PH_OFF(lane->sata_phase_offset); + val |= MVEBU_COMPHY_PHASE_CTRL_OS_PH_OFF_FORCE; + val &= ~MVEBU_COMPHY_PHASE_CTRL_OS_PH_OFF_VALID; + writel(val, priv->base + MVEBU_COMPHY_PHASE_CTRL(lane->id)); + + val = readl(priv->base + MVEBU_COMPHY_PHASE_CTRL(lane->id)); + val |= MVEBU_COMPHY_PHASE_CTRL_OS_PH_OFF_VALID; + writel(val, priv->base + MVEBU_COMPHY_PHASE_CTRL(lane->id)); + + val = readl(priv->base + MVEBU_COMPHY_PHASE_CTRL(lane->id)); + val &= ~MVEBU_COMPHY_PHASE_CTRL_OS_PH_OFF_VALID; + writel(val, priv->base + MVEBU_COMPHY_PHASE_CTRL(lane->id)); + + /* Set G1 TX amplitude and TX post emphasis value */ + val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); + val &= ~(MVEBU_COMPHY_GEN1_S0_TX_AMP(0x1f) | + MVEBU_COMPHY_GEN1_S0_TX_EMPH(0xf)); + val |= MVEBU_COMPHY_GEN1_S0_TX_AMP(0x8) | + MVEBU_COMPHY_GEN1_S0_TX_EMPH(0x1) | + MVEBU_COMPHY_GEN1_S0_TX_AMP_ADJ | + MVEBU_COMPHY_GEN1_S0_TX_EMPH_EN; + writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); + + /* Set G2 TX amplitude and TX post emphasis value */ + val = readl(priv->base + MVEBU_COMPHY_GEN2_S0(lane->id)); + val &= ~(MVEBU_COMPHY_GEN2_S0_TX_AMP(0x1f) | + MVEBU_COMPHY_GEN2_S0_TX_EMPH(0xf)); + val |= MVEBU_COMPHY_GEN2_S0_TX_AMP(0xa) | + MVEBU_COMPHY_GEN2_S0_TX_EMPH(0x2) | + MVEBU_COMPHY_GEN2_S0_TX_AMP_ADJ | + MVEBU_COMPHY_GEN2_S0_TX_EMPH_EN; + writel(val, priv->base + MVEBU_COMPHY_GEN2_S0(lane->id)); + + /* Set G3 TX amplitude and TX post emphasis value */ + val = readl(priv->base + MVEBU_COMPHY_GEN3_S0(lane->id)); + val &= ~(MVEBU_COMPHY_GEN3_S0_TX_AMP(0x1f) | + MVEBU_COMPHY_GEN3_S0_TX_EMPH(0xf) | + MVEBU_COMPHY_GEN3_S0_TX_SLEW_RATE_SEL(0x7) | + MVEBU_COMPHY_GEN3_S0_TX_SLEW_CTRL_EN); + val |= MVEBU_COMPHY_GEN3_S0_TX_AMP(lane->sata_gen3_s0_amplitude) | + MVEBU_COMPHY_GEN3_S0_TX_EMPH(lane->sata_gen3_s0_emphasis) | + MVEBU_COMPHY_GEN3_S0_TX_SLEW_RATE_SEL(0x4) | + MVEBU_COMPHY_GEN3_S0_TX_AMP_ADJ | + MVEBU_COMPHY_GEN3_S0_TX_EMPH_EN; + writel(val, priv->base + MVEBU_COMPHY_GEN3_S0(lane->id)); + + /* SERDES External Configuration 2 register */ + val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id)); + val |= MVEBU_COMPHY_SERDES_CFG2_SSC_EN; + writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id)); + + /* DFE reset sequence */ + val = readl(priv->base + MVEBU_COMPHY_PWR_CTR(lane->id)); + val |= MVEBU_COMPHY_PWR_CTR_RST_DFE; + writel(val, priv->base + MVEBU_COMPHY_PWR_CTR(lane->id)); + val = readl(priv->base + MVEBU_COMPHY_PWR_CTR(lane->id)); + val &= ~MVEBU_COMPHY_PWR_CTR_RST_DFE; + writel(val, priv->base + MVEBU_COMPHY_PWR_CTR(lane->id)); + + /* SW reset for interrupt logic */ + val = readl(priv->base + MVEBU_COMPHY_PWR_CTR(lane->id)); + val |= MVEBU_COMPHY_PWR_CTR_SOFT_RST; + writel(val, priv->base + MVEBU_COMPHY_PWR_CTR(lane->id)); + val = readl(priv->base + MVEBU_COMPHY_PWR_CTR(lane->id)); + val &= ~MVEBU_COMPHY_PWR_CTR_SOFT_RST; + writel(val, priv->base + MVEBU_COMPHY_PWR_CTR(lane->id)); + + /* wait for PLL ready */ +#if 0 + readl_poll_timeout(priv->base + MVEBU_COMPHY_SERDES_STATUS0(lane->id), + val, + val & (MVEBU_COMPHY_SERDES_STATUS0_RX_PLL_RDY | + MVEBU_COMPHY_SERDES_STATUS0_TX_PLL_RDY), + 1000, 150000); + if (!(val & (MVEBU_COMPHY_SERDES_STATUS0_RX_PLL_RDY | + MVEBU_COMPHY_SERDES_STATUS0_TX_PLL_RDY))) + return -ETIMEDOUT; +#endif + + return 0; +} + +static int mvebu_comphy_set_mode_usb3(struct phy *phy) +{ + struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); + struct mvebu_comphy_priv *priv = lane->priv; + u32 val; + + mvebu_comphy_usb3_init_reset(lane); + + /* select de-emphasize 3.5db */ + val = readl(priv->base + MVEBU_COMPHY_LANE_CFG0(lane->id)); + val |= MVEBU_COMPHY_LANE_CFG0_PRD_TXEEMPH0; + writel(val, priv->base + MVEBU_COMPHY_LANE_CFG0(lane->id)); + + /* override tx margining from the MAC */ + val = readl(priv->base + MVEBU_COMPHY_MODE_CTRL(lane->id)); + val |= MVEBU_COMPHY_MODE_CTRL_MODE_MARGIN; + writel(val, priv->base + MVEBU_COMPHY_MODE_CTRL(lane->id)); + + /* Start analog paramters from ETP(HW) */ + val = readl(priv->base + MVEBU_COMPHY_LANE_CFG4(lane->id)); + val &= ~MVEBU_COMPHY_LANE_CFG4_DFE_CTRL(0x7); + val |= MVEBU_COMPHY_LANE_CFG4_DFE_CTRL(0x1); + val |= MVEBU_COMPHY_LANE_CFG4_DFE_OVER; + val |= MVEBU_COMPHY_LANE_CFG4_DFE_SSC; + writel(val, priv->base + MVEBU_COMPHY_LANE_CFG4(lane->id)); + + /* Release from PIPE soft reset */ + val = readl(priv->base + MVEBU_COMPHY_PIPE_RST_CLK_CTRL(lane->id)); + val &= ~MVEBU_COMPHY_PIPE_RST_CLK_CTRL_RST; + writel(val, priv->base + MVEBU_COMPHY_PIPE_RST_CLK_CTRL(lane->id)); + + /* wait for PLL ready */ + readl_poll_timeout(priv->base + MVEBU_COMPHY_LANE_STATUS0(lane->id), + val, + val & MVEBU_COMPHY_LANE_STATUS0_PCLK_EN, + 1000, 150000); + if (!(val & MVEBU_COMPHY_LANE_STATUS0_PCLK_EN)) + return -ETIMEDOUT; + + return 0; +} + +static int mvebu_comphy_pcie_get_width(struct mvebu_comphy_lane *lane) +{ + int i; + struct mvebu_comphy_priv *priv = lane->priv; + int ret; + + if (lane->id == 4 || lane->id == 5) { + return 1; + } + + for (ret = 0, i = 0; i < 4; ++i) { + if (priv->modes[i] == PHY_MODE_PCIE) + ++ret; + else + break; + } + + if (ret == 0 || ret == 3) + /* + * filter out invalid configurations. + */ + return -EINVAL; + + return ret; +} + +static int mvebu_comphy_set_mode_pcie(struct phy *phy) +{ + struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); + struct mvebu_comphy_priv *priv = lane->priv; + int pcie_clk_config; + int pcie_width; + u32 val; + int start_lane; + int end_lane; + int i; + + /* + * first get PCIe clk configuration from sample at reset + * register. + * values for pcie_clk_config: + * - 0: external PCIe clock generation + * - 1: internal PCIe clock generation + * + * NOTE: on A8K, only the master CP holds the proper pcie + * clock configuration. the PCIE1 bit control the clock + * configuration for both lane 4 and lane 5. + * + * FIXME: we should use the CP1 configuration values when + * initialising the CP1 PCIe interfaces. + */ + regmap_read(priv->sar_regmap, DEVICE_SAR0, &val); + if (lane->id == 4 || lane->id == 5) { + pcie_clk_config = !!(val & DEV_SAR0_PCIE1_CLK_CP0); + } else { + pcie_clk_config = !!(val & DEV_SAR0_PCIE0_CLK_CP0); + } + + pcie_width = mvebu_comphy_pcie_get_width(lane); + if (pcie_width < 0) + return pcie_width; + + /* + * PCIe width configuration on lane 0 + */ + if (lane->id == 0) { + regmap_read(priv->regmap, MVEBU_COMPHY_SD_CTRL1, &val); + switch (pcie_width) { + case 1: + val &= ~MVEBU_COMPHY_SD_CTRL1_PCIE_X2_EN; + val &= ~MVEBU_COMPHY_SD_CTRL1_PCIE_X4_EN; + break; + case 2: + val |= MVEBU_COMPHY_SD_CTRL1_PCIE_X2_EN; + val &= ~MVEBU_COMPHY_SD_CTRL1_PCIE_X4_EN; + break; + case 4: + val &= ~MVEBU_COMPHY_SD_CTRL1_PCIE_X2_EN; + val |= MVEBU_COMPHY_SD_CTRL1_PCIE_X4_EN; + break; + } + regmap_write(priv->regmap, MVEBU_COMPHY_SD_CTRL1, val); + } + + /* + * if PCIe clock is output and clock source from SerDes lane + * 5, need to configure the clock-source MUX. By default, the + * clock source is from lane 4 + */ + if (pcie_clk_config && lane->id == 5) { + regmap_read(priv->cp_mgmt_regmap, DFX_DEV_GEN_CTRL12, &val); + val &= ~DFX_DEV_GEN_CTRL12_CLK_SRC(0x7); + val |= DFX_DEV_GEN_CTRL12_CLK_SRC(0x3); + regmap_write(priv->cp_mgmt_regmap, DFX_DEV_GEN_CTRL12, val); + } + + mvebu_comphy_pcie_init_reset(lane, pcie_clk_config, pcie_width); + + val = readl(priv->base + MVEBU_COMPHY_PCIE_REG0(lane->id)); + val |= MVEBU_COMPHY_PCIE_REG0_IDLE_SYNC; + val &= ~MVEBU_COMPHY_PCIE_REG0_SEL_BITS(0x3); + val |= MVEBU_COMPHY_PCIE_REG0_SEL_BITS(0x2); + writel(val, priv->base + MVEBU_COMPHY_PCIE_REG0(lane->id)); + + + val = readl(priv->base + MVEBU_COMPHY_TX_TRAIN_CTRL(lane->id)); + val |= MVEBU_COMPHY_TX_TRAIN_CTRL_G1; + val |= MVEBU_COMPHY_TX_TRAIN_CTRL_GN1; + val &= ~MVEBU_COMPHY_TX_TRAIN_CTRL_G0; + writel(val, priv->base + MVEBU_COMPHY_TX_TRAIN_CTRL(lane->id)); + + val = readl(priv->base + MVEBU_COMPHY_TX_TRAIN_PRESET(lane->id)); + val &= ~MVEBU_COMPHY_TX_TRAIN_CHK_INIT; + val |= MVEBU_COMPHY_TX_TRAIN_COEF_FM_PIN_PCIE3; + writel(val, priv->base + MVEBU_COMPHY_TX_TRAIN_PRESET(lane->id)); + + /* Set Preset sweep configurations */ + val = readl(priv->base + MVEBU_COMPHY_TX_TRAINING11(lane->id)); + val |= MVEBU_COMPHY_TX_TRAINING11_CHECK_MODE; + val |= MVEBU_COMPHY_TX_TRAINING11_PRESET_NUM(0x7); + val |= MVEBU_COMPHY_TX_TRAINING11_PRESET_EN; + writel(val, priv->base + MVEBU_COMPHY_TX_TRAINING11(lane->id)); + + /* Tx train start configuration */ + val = readl(priv->base + MVEBU_COMPHY_TRAINING5(lane->id)); + val |= MVEBU_COMPHY_TRAINING5_START_SQ_EN; + val &= ~MVEBU_COMPHY_TRAINING5_FRM_DET_EN; + val &= ~MVEBU_COMPHY_TRAINING5_FRM_LOCK_EN; + val |= MVEBU_COMPHY_TRAINING5_WAIT_TIME_EN; + writel(val, priv->base + MVEBU_COMPHY_TRAINING5(lane->id)); + + /* Enable Tx train P2P */ + val = readl(priv->base + MVEBU_COMPHY_TRAINING0(lane->id)); + val |= MVEBU_COMPHY_TRAINING0_P2P_HOLD; + writel(val, priv->base + MVEBU_COMPHY_TRAINING0(lane->id)); + + + /* Configure Tx train timeout */ + val = readl(priv->base + MVEBU_COMPHY_TRAINING4(lane->id)); + val &= ~MVEBU_COMPHY_TRAINING4_TIMER(0x3ff); + val |= MVEBU_COMPHY_TRAINING4_TIMER(0x17); + writel(val, priv->base + MVEBU_COMPHY_TRAINING4(lane->id)); + + /* Disable G0/G1/GN1 adaptation */ + val = readl(priv->base + MVEBU_COMPHY_TX_TRAIN_CTRL(lane->id)); + val &= ~MVEBU_COMPHY_TX_TRAIN_CTRL_G1; + val &= ~MVEBU_COMPHY_TX_TRAIN_CTRL_GN1; + val &= ~MVEBU_COMPHY_TX_TRAIN_CTRL_G0; + writel(val, priv->base + MVEBU_COMPHY_TX_TRAIN_CTRL(lane->id)); + + /* Disable DTL frequency loop */ + val = readl(priv->base + MVEBU_COMPHY_DLT_CTRL(lane->id)); + val &= ~MVEBU_COMPHY_DLT_CTRL_DTL_FLOOP_EN; + writel(val, priv->base + MVEBU_COMPHY_DLT_CTRL(lane->id)); + + /* Configure G3 DFE */ + val = readl(priv->base + MVEBU_COMPHY_GEN3_S4(lane->id)); + val &= ~MVEBU_COMPHY_GEN3_S4_DFE_RES(0x3); + val |= MVEBU_COMPHY_GEN3_S4_DFE_RES(0x3); + writel(val, priv->base + MVEBU_COMPHY_GEN3_S4(lane->id)); + + /* Use TX/RX training result for DFE */ + val = readl(priv->base + MVEBU_COMPHY_DFE_RES(lane->id)); + val &= ~MVEBU_COMPHY_DFE_RES_FORCE_GEN_TBL; + writel(val, priv->base + MVEBU_COMPHY_DFE_RES(lane->id)); + + /* Configure initial and final coefficient value for receiver */ + val = readl(priv->base + MVEBU_COMPHY_GEN3_S1(lane->id)); + val &= ~(MVEBU_COMPHY_GEN3_S1_RX_MUL_PI(0x7) | + MVEBU_COMPHY_GEN3_S1_RX_MUL_PF(0x7) | + MVEBU_COMPHY_GEN3_S1_SMPL_INPX2_EN); + val |= MVEBU_COMPHY_GEN3_S1_RX_MUL_PI(0x1) | + MVEBU_COMPHY_GEN3_S1_RX_MUL_PF(0x1); + writel(val, priv->base + MVEBU_COMPHY_GEN3_S1(lane->id)); + + /* Trigger sampler enable pulse */ + val = readl(priv->base + MVEBU_SP_CALIB(lane->id)); + val |= MVEBU_SP_CALIB_SAMPLER_EN; + writel(val, priv->base + MVEBU_SP_CALIB(lane->id)); + udelay(5); + val = readl(priv->base + MVEBU_SP_CALIB(lane->id)); + val &= ~MVEBU_SP_CALIB_SAMPLER_EN; + writel(val, priv->base + MVEBU_SP_CALIB(lane->id)); + + /* FFE resistor tuning for different bandwidth */ + /* G3 Setting 3 */ + val = readl(priv->base + MVEBU_COMPHY_GEN3_S3(lane->id)); + val &= ~(MVEBU_COMPHY_GEN3_S3_FFE_DEG_RES_LVL(0x3) | + MVEBU_COMPHY_GEN3_S3_FFE_LOAD_RES_LVL(0x3)); + val |= MVEBU_COMPHY_GEN3_S3_FFE_DEG_RES_LVL(0x1) | + MVEBU_COMPHY_GEN3_S3_FFE_LOAD_RES_LVL(0x3); + writel(val, priv->base + MVEBU_COMPHY_GEN3_S3(lane->id)); + + /* Pattern lock lost timeout disable */ + val = readl(priv->base + MVEBU_COMPHY_FRAME_DETECT3(lane->id)); + val &= ~MVEBU_COMPHY_FRAME_DETECT3_LOST_TIMEOUT_EN; + writel(val, priv->base + MVEBU_COMPHY_FRAME_DETECT3(lane->id)); + + /* Configure DFE adaptations */ + val = readl(priv->base + MVEBU_COMPHY_CDR_CONTROL(lane->id)); + val &= ~MVEBU_COMPHY_CDR_CONTROL_RX_MAX_DFE_ADAPT_1(0x3); + val &= ~MVEBU_COMPHY_CDR_CONTROL_MAX_DFE_ADAPT_1(0x7); + val &= ~MVEBU_COMPHY_CDR_CONTROL_MAX_DFE_ADAPT_0(0x7); + val |= MVEBU_COMPHY_CDR_CONTROL_RX_MAX_DFE_ADAPT_1(0x0); + val |= MVEBU_COMPHY_CDR_CONTROL_MAX_DFE_ADAPT_1(0x1); + val |= MVEBU_COMPHY_CDR_CONTROL_MAX_DFE_ADAPT_0(0x0); + writel(val, priv->base + MVEBU_COMPHY_CDR_CONTROL(lane->id)); + + val = readl(priv->base + MVEBU_COMPHY_DFE_CTRL(lane->id)); + val &= ~MVEBU_COMPHY_DFE_CTRL_TX_MAX_DFE_ADAPT(0x3); + writel(val, priv->base + MVEBU_COMPHY_DFE_CTRL(lane->id)); + + /* Generation 2 setting 1*/ + val = readl(priv->base + MVEBU_COMPHY_GEN2_S1(lane->id)); + val &= ~MVEBU_COMPHY_GEN2_S1_RX_MUL_PI(0x7); + val &= ~MVEBU_COMPHY_GEN2_S1_RX_MUL_PF(0x7); + val &= ~MVEBU_COMPHY_GEN2_S1_RX_MUL_FI(0x3); + val |= MVEBU_COMPHY_GEN2_S1_RX_MUL_PI(0x0); + val |= MVEBU_COMPHY_GEN2_S1_RX_MUL_PF(0x1); + val |= MVEBU_COMPHY_GEN2_S1_RX_MUL_FI(0x0); + writel(val, priv->base + MVEBU_COMPHY_GEN2_S1(lane->id)); + + /* DFE enable */ + val = readl(priv->base + MVEBU_COMPHY_GEN2_S4(lane->id)); + val &= ~MVEBU_COMPHY_GEN2_S4_DFE_RES(0x3); + val |= MVEBU_COMPHY_GEN2_S4_DFE_RES(0x3); + writel(val, priv->base + MVEBU_COMPHY_GEN2_S4(lane->id)); + + /* Configure DFE Resolution */ + val = readl(priv->base + MVEBU_COMPHY_LANE_CFG4(lane->id)); + val |= MVEBU_COMPHY_LANE_CFG4_DFE_EN_SEL; + writel(val, priv->base + MVEBU_COMPHY_LANE_CFG4(lane->id)); + + /* VDD calibration control */ + val = readl(priv->base + MVEBU_COMPHY_EXT_SELV(lane->id)); + val &= ~MVEBU_COMPHY_EXT_SELV_RX_SAMPL(0x1f); + val |= MVEBU_COMPHY_EXT_SELV_RX_SAMPL(0x16); + writel(val, priv->base + MVEBU_COMPHY_EXT_SELV(lane->id)); + + /* Set PLL Charge-pump Current Control */ + val = readl(priv->base + MVEBU_COMPHY_GEN3_S5(lane->id)); + val &= ~MVEBU_COMPHY_GEN3_S5_ICP(0xf); + val |= MVEBU_COMPHY_GEN3_S5_ICP(0x4); + writel(val, priv->base + MVEBU_COMPHY_GEN3_S5(lane->id)); + + /* Set lane equalization remote setting */ + val = readl(priv->base + MVEBU_COMPHY_LANE_EQ_REMOTE_CFG(lane->id)); + val |= MVEBU_COMPHY_LANE_EQ_REMOTE_CFG_DIRN_OVERRIDE; + val |= MVEBU_COMPHY_LANE_EQ_REMOTE_CFG_ONLY_MODE; + val &= ~MVEBU_COMPHY_LANE_EQ_REMOTE_CFG_PRESET_VECTOR(0xf); + val |= MVEBU_COMPHY_LANE_EQ_REMOTE_CFG_PRESET_VECTOR(0x2); + writel(val, priv->base + MVEBU_COMPHY_LANE_EQ_REMOTE_CFG(lane->id)); + + /* Set phy in root complex mode */ + val = readl(priv->base + MVEBU_COMPHY_EQ_CONFIG0(lane->id)); + val |= MVEBU_COMPHY_EQ_CONFIG0_RC_MODE; + writel(val, priv->base + MVEBU_COMPHY_EQ_CONFIG0(lane->id)); + + /* we're done for now if we are not in the last lane. */ + if (pcie_width > 1 && lane->id != (pcie_width - 1)) + return 0; + + if (pcie_width > 1) { + /* + * for x2 or x4: we need to release the pipe reset in + * one single write on all comphys. + */ + regmap_read(priv->regmap, MVEBU_COMPHY_SD_CTRL1, &val); + if (pcie_width == 2) + val &= ~MVEBU_COMPHY_SD_CTRL1_PHY0_1_MASK; + else + val &= ~MVEBU_COMPHY_SD_CTRL1_PHY0_3_MASK; + regmap_write(priv->regmap, MVEBU_COMPHY_SD_CTRL1, val); + + /* + * now all writes to comphy register block 0 will hit + * all PCIe PHYs. + */ + val = readl(priv->base + MVEBU_COMPHY_PIPE_RST_CLK_CTRL(0)); + val &= ~MVEBU_COMPHY_PIPE_RST_CLK_CTRL_RST; + writel(val, priv->base + MVEBU_COMPHY_PIPE_RST_CLK_CTRL(0)); + + /* + * restore writes to all individual phys. + */ + regmap_read(priv->regmap, MVEBU_COMPHY_SD_CTRL1, &val); + if (pcie_width == 2) + val |= 0x0010; + else + val |= 0x3210; + regmap_write(priv->regmap, MVEBU_COMPHY_SD_CTRL1, val); + + start_lane = 0; + end_lane = pcie_width - 1; + } else { + /* release pipe soft reset */ + val = readl(priv->base + + MVEBU_COMPHY_PIPE_RST_CLK_CTRL(lane->id)); + val &= ~MVEBU_COMPHY_PIPE_RST_CLK_CTRL_RST; + writel(val, priv->base + + MVEBU_COMPHY_PIPE_RST_CLK_CTRL(lane->id)); + start_lane = end_lane = lane->id; + } + + for (i = start_lane; i <= end_lane; ++i) { + readl_poll_timeout(priv->base + MVEBU_COMPHY_LANE_STATUS0(i), + val, + val & MVEBU_COMPHY_LANE_STATUS0_PCLK_EN, + 1000, 150000); + if (!(val & MVEBU_COMPHY_LANE_STATUS0_PCLK_EN)) { + printk("timedout waiting for lane pclk on lane %d\n", + lane->id); + return -ETIMEDOUT; + } + } + + return 0; +} + static int mvebu_comphy_power_on(struct phy *phy) { struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); struct mvebu_comphy_priv *priv = lane->priv; - int ret, mux; + int ret, mux, pipe_mux; u32 val; mux = mvebu_comphy_get_mux(lane->id, lane->port, lane->mode); - if (mux < 0) + pipe_mux = mvebu_comphy_get_pipe_mux(lane->id, lane->port, lane->mode); + + if (mux < 0 && pipe_mux < 0) return -ENOTSUPP; + if (mux < 0) + mux = 0; + if (pipe_mux < 0) + pipe_mux = 0; + regmap_read(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, &val); val &= ~(0xf << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane->id)); + val |= pipe_mux << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane->id); regmap_write(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, val); regmap_read(priv->regmap, MVEBU_COMPHY_SELECTOR, &val); @@ -487,12 +1620,23 @@ regmap_write(priv->regmap, MVEBU_COMPHY_SELECTOR, val); switch (lane->mode) { + case PHY_MODE_HS_SGMII: case PHY_MODE_SGMII: - ret = mvebu_comphy_set_mode_sgmii(phy); + ret = mvebu_comphy_set_mode_sgmii(phy, lane->mode); break; case PHY_MODE_10GKR: ret = mvebu_comphy_set_mode_10gkr(phy); break; + case PHY_MODE_SATA: + ret = mvebu_comphy_set_mode_sata(phy); + break; + case PHY_MODE_USB_HOST: + case PHY_MODE_USB_DEVICE: + ret = mvebu_comphy_set_mode_usb3(phy); + break; + case PHY_MODE_PCIE: + ret = mvebu_comphy_set_mode_pcie(phy); + break; default: return -ENOTSUPP; } @@ -502,6 +1646,20 @@ val |= MVEBU_COMPHY_SERDES_CFG1_RF_RESET; writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); + /* + * swap rx/tx N/P polarities if needed. + */ + val = readl(priv->base + MVEBU_COMPHY_SYNC_PATTERN(lane->id)); + if (lane->rx_swap_polarity) + val |= MVEBU_COMPHY_SYNC_PATTERN_RXD_INV; + else + val &= ~MVEBU_COMPHY_SYNC_PATTERN_RXD_INV; + if (lane->tx_swap_polarity) + val |= MVEBU_COMPHY_SYNC_PATTERN_TXD_INV; + else + val &= ~MVEBU_COMPHY_SYNC_PATTERN_TXD_INV; + writel(val, priv->base + MVEBU_COMPHY_SYNC_PATTERN(lane->id)); + return ret; } @@ -509,9 +1667,11 @@ { struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); - if (mvebu_comphy_get_mux(lane->id, lane->port, mode) < 0) + if (mvebu_comphy_get_mux(lane->id, lane->port, mode) < 0 && + mvebu_comphy_get_pipe_mux(lane->id, lane->port, mode) < 0) return -EINVAL; + lane->priv->modes[lane->id] = mode; lane->mode = mode; return 0; } @@ -528,6 +1688,11 @@ MVEBU_COMPHY_SERDES_CFG1_RF_RESET); writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); + regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val); + val &= ~MVEBU_COMPHY_CONF1_POR; + val &= ~MVEBU_COMPHY_CONF1_CORE_RESET; + regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val); + regmap_read(priv->regmap, MVEBU_COMPHY_SELECTOR, &val); val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id)); regmap_write(priv->regmap, MVEBU_COMPHY_SELECTOR, val); @@ -539,10 +1704,30 @@ return 0; } +static int mvebu_comphy_is_pll_locked(struct phy *phy) +{ + struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); + struct mvebu_comphy_priv *priv = lane->priv; + u32 val; + + /* wait for PLL ready */ + readl_poll_timeout(priv->base + MVEBU_COMPHY_SERDES_STATUS0(lane->id), + val, + val & (MVEBU_COMPHY_SERDES_STATUS0_RX_PLL_RDY | + MVEBU_COMPHY_SERDES_STATUS0_TX_PLL_RDY), + 1000, 150000); + if (!(val & (MVEBU_COMPHY_SERDES_STATUS0_RX_PLL_RDY | + MVEBU_COMPHY_SERDES_STATUS0_TX_PLL_RDY))) + return -ETIMEDOUT; + + return 0; +} + static const struct phy_ops mvebu_comphy_ops = { .power_on = mvebu_comphy_power_on, .power_off = mvebu_comphy_power_off, .set_mode = mvebu_comphy_set_mode, + .is_pll_locked = mvebu_comphy_is_pll_locked, .owner = THIS_MODULE, }; @@ -573,6 +1758,7 @@ struct phy_provider *provider; struct device_node *child; struct resource *res; + int ret; priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); if (!priv) @@ -584,15 +1770,43 @@ "marvell,system-controller"); if (IS_ERR(priv->regmap)) return PTR_ERR(priv->regmap); + + priv->sar_regmap = + syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "marvell,sar"); + if (IS_ERR(priv->sar_regmap)) + return PTR_ERR(priv->sar_regmap); + + priv->cp_mgmt_regmap = + syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "marvell,cp_mgmt"); + if (IS_ERR(priv->cp_mgmt_regmap)) + return PTR_ERR(priv->cp_mgmt_regmap); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); priv->base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(priv->base)) return PTR_ERR(priv->base); + priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk"); + if (IS_ERR(priv->gop_clk)) + return PTR_ERR(priv->gop_clk); + + priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk"); + if (IS_ERR(priv->mg_clk)) + return PTR_ERR(priv->mg_clk); + + ret = clk_prepare_enable(priv->gop_clk); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->mg_clk); + if (ret) + goto disable_gop_clk; + for_each_available_child_of_node(pdev->dev.of_node, child) { struct mvebu_comphy_lane *lane; struct phy *phy; - int ret; u32 val; ret = of_property_read_u32(child, "reg", &val); @@ -608,12 +1822,16 @@ } lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL); - if (!lane) - return -ENOMEM; + if (!lane) { + ret = -ENOMEM; + goto disable_mg_clk; + } phy = devm_phy_create(&pdev->dev, child, &mvebu_comphy_ops); - if (IS_ERR(phy)) - return PTR_ERR(phy); + if (IS_ERR(phy)) { + ret = PTR_ERR(phy); + goto disable_mg_clk; + } lane->priv = priv; lane->mode = PHY_MODE_INVALID; @@ -621,17 +1839,73 @@ lane->port = -1; phy_set_drvdata(phy, lane); + lane->kr_gen1_s0_amplitude = DEFAULT_GEN1_S0_AMP; + lane->kr_gen1_s0_emphasis = DEFAULT_GEN1_S0_EMPH; + lane->kr_gen1_s2_emphasis = DEFAULT_GEN1_S2_EMPH; + lane->kr_ffe_cap_sel = KR_DEFAULT_FFE_CAP_SEL; + lane->kr_ffe_res_sel = KR_DEFAULT_FFE_RES_SEL; + lane->kr_phase_offset = KR_DEFAULT_PHASE_OFFSET; + lane->kr_dfe_res = KR_DEFAULT_DFE_RES; + + /* + * fetch optional 10GKR amplitude and emphasis + * parameters from device tree for this comphy. + */ + of_property_read_u32(child, "kr-gen1-s0-amplitude", + &lane->kr_gen1_s0_amplitude); + of_property_read_u32(child, "kr-gen1-s0-emphasis", + &lane->kr_gen1_s0_emphasis); + of_property_read_u32(child, "kr-gen1-s2-emphasis", + &lane->kr_gen1_s2_emphasis); + of_property_read_u32(child, "kr-ffe-cap-sel", + &lane->kr_ffe_cap_sel); + of_property_read_u32(child, "kr-ffe-res-sel", + &lane->kr_ffe_res_sel); + of_property_read_u32(child, "kr-dfe-res", + &lane->kr_dfe_res); + of_property_read_u32(child, "kr-phase-offset", + &lane->kr_phase_offset); + + lane->sata_gen3_s0_amplitude = SATA_DEFAULT_GEN3_S0_AMP; + lane->sata_gen3_s0_emphasis = SATA_DEFAULT_GEN3_S0_EMPH; + lane->sata_gen3_s4_dfe_res = SATA_DEFAULT_GEN3_S4_DFE_RES; + lane->sata_phase_offset = SATA_DEFAULT_PHASE_OFFSET; + /* + * fetch optional SATA amplitude and emphasis + * parameter from device tree, for this comphy. + */ + of_property_read_u32(child, "sata-gen3-s0-amplitude", + &lane->sata_gen3_s0_amplitude); + of_property_read_u32(child, "sata-gen3-s0-emphasis", + &lane->sata_gen3_s0_emphasis); + of_property_read_u32(child, "sata-gen3-s4-dfe-res", + &lane->sata_gen3_s4_dfe_res); + of_property_read_u32(child, "sata-phase-offset", + &lane->sata_phase_offset); + + lane->rx_swap_polarity = of_property_read_bool(child, + "rx-swap-polarity"); + lane->tx_swap_polarity = of_property_read_bool(child, + "tx-swap-polarity"); + /* - * Once all modes are supported in this driver we should call - * mvebu_comphy_power_off(phy) here to avoid relying on the - * bootloader/firmware configuration. + * All modes are now supported in this driver so call + * mvebu_comphy_power_off(phy) here to avoid relying + * on the bootloader/firmware configuration. */ + mvebu_comphy_power_off(phy); } dev_set_drvdata(&pdev->dev, priv); provider = devm_of_phy_provider_register(&pdev->dev, mvebu_comphy_xlate); return PTR_ERR_OR_ZERO(provider); + +disable_mg_clk: + clk_disable_unprepare(priv->mg_clk); +disable_gop_clk: + clk_disable_unprepare(priv->gop_clk); + return ret; } static const struct of_device_id mvebu_comphy_of_match_table[] = { diff -ruw linux-4.14.127/drivers/phy/phy-core.c linux-4.14.127-fbx/drivers/phy/phy-core.c --- linux-4.14.127/drivers/phy/phy-core.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/phy/phy-core.c 2019-02-15 14:29:40.846651713 +0100 @@ -372,6 +372,21 @@ } EXPORT_SYMBOL_GPL(phy_reset); +int phy_is_pll_locked(struct phy *phy) +{ + int ret; + + if (!phy || !phy->ops->is_pll_locked) + return 0; + + mutex_lock(&phy->mutex); + ret = phy->ops->is_pll_locked(phy); + mutex_unlock(&phy->mutex); + + return ret; +} +EXPORT_SYMBOL_GPL(phy_is_pll_locked); + /** * _of_phy_get() - lookup and obtain a reference to a phy by phandle * @np: device_node for which to get the phy diff -ruw linux-4.14.127/drivers/pinctrl/bcm/Kconfig linux-4.14.127-fbx/drivers/pinctrl/bcm/Kconfig --- linux-4.14.127/drivers/pinctrl/bcm/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/pinctrl/bcm/Kconfig 2019-02-15 14:29:40.858651761 +0100 @@ -22,6 +22,15 @@ select PINCONF select GPIOLIB_IRQCHIP +config PINCTRL_BCM63138 + bool "Broadcom 63138 pinmux driver" + depends on OF && (ARCH_BCM_63XX || COMPILE_TEST) + default ARCH_BCM_63XX + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GPIOLIB + config PINCTRL_IPROC_GPIO bool "Broadcom iProc GPIO (with PINCONF) driver" depends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST) diff -ruw linux-4.14.127/drivers/pinctrl/bcm/Makefile linux-4.14.127-fbx/drivers/pinctrl/bcm/Makefile --- linux-4.14.127/drivers/pinctrl/bcm/Makefile 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/pinctrl/bcm/Makefile 2019-02-15 14:29:40.858651761 +0100 @@ -3,6 +3,7 @@ obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o +obj-$(CONFIG_PINCTRL_BCM63138) += pinctrl-bcm63138.o obj-$(CONFIG_PINCTRL_IPROC_GPIO) += pinctrl-iproc-gpio.o obj-$(CONFIG_PINCTRL_CYGNUS_MUX) += pinctrl-cygnus-mux.o obj-$(CONFIG_PINCTRL_NSP_GPIO) += pinctrl-nsp-gpio.o diff -ruw linux-4.14.127/drivers/platform/Kconfig linux-4.14.127-fbx/drivers/platform/Kconfig --- linux-4.14.127/drivers/platform/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/platform/Kconfig 2019-02-15 14:29:40.930652046 +0100 @@ -8,3 +8,9 @@ source "drivers/platform/goldfish/Kconfig" source "drivers/platform/chrome/Kconfig" + +if X86_INTEL_CE +source "drivers/platform/intelce/Kconfig" +endif + +source "drivers/platform/fbxgw7r/Kconfig" diff -ruw linux-4.14.127/drivers/platform/Makefile linux-4.14.127-fbx/drivers/platform/Makefile --- linux-4.14.127/drivers/platform/Makefile 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/platform/Makefile 2019-02-15 14:29:40.930652046 +0100 @@ -8,3 +8,5 @@ obj-$(CONFIG_OLPC) += olpc/ obj-$(CONFIG_GOLDFISH) += goldfish/ obj-$(CONFIG_CHROME_PLATFORMS) += chrome/ +obj-$(CONFIG_X86_INTEL_CE) += intelce/ +obj-$(CONFIG_FBXGW7R_PLATFORM) += fbxgw7r/ diff -ruw linux-4.14.127/drivers/soc/bcm/Kconfig linux-4.14.127-fbx/drivers/soc/bcm/Kconfig --- linux-4.14.127/drivers/soc/bcm/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/soc/bcm/Kconfig 2019-02-15 14:29:41.530654424 +0100 @@ -20,4 +20,23 @@ If unsure, say N. +config SOC_BCM63XX + bool "Broadcom 63xx SoC drivers" + depends on ARCH_BCM_63XX || COMPILE_TEST + select RESET_CONTROLLER + help + Enables drivers for the Broadcom 63XX series of chips. + This option alone enables only some support code, while the drivers + can be enabled individually within this menu. + + If unsure, say N. + +config SOC_BCM63XX_RDP_NEED_ENET + depends on SOC_BCM63XX + bool + +config SOC_BCM63XX_RDP_NEED_DSL + depends on SOC_BCM63XX + bool + endmenu diff -ruw linux-4.14.127/drivers/soc/bcm/Makefile linux-4.14.127-fbx/drivers/soc/bcm/Makefile --- linux-4.14.127/drivers/soc/bcm/Makefile 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/soc/bcm/Makefile 2019-02-15 14:29:41.530654424 +0100 @@ -1,2 +1,3 @@ obj-$(CONFIG_RASPBERRYPI_POWER) += raspberrypi-power.o obj-$(CONFIG_SOC_BRCMSTB) += brcmstb/ +obj-$(CONFIG_SOC_BCM63XX) += bcm63xx/ diff -ruw linux-4.14.127/drivers/spi/Kconfig linux-4.14.127-fbx/drivers/spi/Kconfig --- linux-4.14.127/drivers/spi/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/spi/Kconfig 2019-02-15 14:29:41.546654488 +0100 @@ -515,6 +515,12 @@ help This selects a driver for the PPC4xx SPI Controller. +config SPI_TDM_ORION + tristate "Orion TDM SPI master" + depends on PLAT_ORION + help + This enables using the TDM SPI master controller on the Orion chips. + config SPI_PXA2XX tristate "PXA2xx SSP SPI master" depends on (ARCH_PXA || ARCH_MMP || PCI || ACPI) diff -ruw linux-4.14.127/drivers/spi/Makefile linux-4.14.127-fbx/drivers/spi/Makefile --- linux-4.14.127/drivers/spi/Makefile 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/spi/Makefile 2019-02-15 14:29:41.546654488 +0100 @@ -72,6 +72,7 @@ obj-$(CONFIG_SPI_ORION) += spi-orion.o obj-$(CONFIG_SPI_PIC32) += spi-pic32.o obj-$(CONFIG_SPI_PIC32_SQI) += spi-pic32-sqi.o +obj-$(CONFIG_SPI_TDM_ORION) += orion_tdm_spi.o obj-$(CONFIG_SPI_PL022) += spi-pl022.o obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o spi-pxa2xx-platform-objs := spi-pxa2xx.o spi-pxa2xx-dma.o diff -ruw linux-4.14.127/drivers/spi/spi-orion.c linux-4.14.127-fbx/drivers/spi/spi-orion.c --- linux-4.14.127/drivers/spi/spi-orion.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/spi/spi-orion.c 2019-02-15 14:29:41.558654535 +0100 @@ -50,6 +50,9 @@ /* Register for the "Direct Mode" */ #define SPI_DIRECT_WRITE_CONFIG_REG 0x20 +/* per-CS register parameters */ +#define SPI_CSN_TIMING_PARM_REGS(n) (0x30 + 4 * (n)) + #define ORION_SPI_TMISO_SAMPLE_MASK (0x3 << 6) #define ORION_SPI_TMISO_SAMPLE_1 (1 << 6) #define ORION_SPI_TMISO_SAMPLE_2 (2 << 6) @@ -661,6 +664,25 @@ goto out_rel_clk; } + /* + * on A8K (using a380 compatible) and A380, there are per-CS + * timing parameters registers, which may be used and left + * active by the bootloader. + * + * This drivers uses the global timing parameter register(s) + * and interface configuration register, and could silently + * fallback to previously configured per-CS timing parameters, + * unless those registers are cleared beforehand. + */ + if (of_device_is_compatible(pdev->dev.of_node, + "marvell,armada-380-spi")) { + int cs; + + for (cs = 0; cs < 8; ++cs) + writel(0x0, spi->base + SPI_CSN_TIMING_PARM_REGS(cs)); + + } + /* Scan all SPI devices of this controller for direct mapped devices */ for_each_available_child_of_node(pdev->dev.of_node, np) { u32 cs; diff -ruw linux-4.14.127/drivers/usb/host/Kconfig linux-4.14.127-fbx/drivers/usb/host/Kconfig --- linux-4.14.127/drivers/usb/host/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/usb/host/Kconfig 2019-02-15 14:29:42.446658055 +0100 @@ -54,13 +54,13 @@ If unsure, say N. config USB_XHCI_MVEBU - tristate "xHCI support for Marvell Armada 375/38x" + tristate "xHCI support for Marvell Armada 375/38x/70x0/80x0" select USB_XHCI_PLATFORM depends on HAS_IOMEM depends on ARCH_MVEBU || COMPILE_TEST ---help--- Say 'Y' to enable the support for the xHCI host controller - found in Marvell Armada 375/38x ARM SOCs. + found in Marvell Armada 375/38x/70x0/80x0 ARM SOCs. config USB_XHCI_RCAR tristate "xHCI support for Renesas R-Car SoCs" diff -ruw linux-4.14.127/drivers/usb/host/xhci-mvebu.c linux-4.14.127-fbx/drivers/usb/host/xhci-mvebu.c --- linux-4.14.127/drivers/usb/host/xhci-mvebu.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/usb/host/xhci-mvebu.c 2019-02-15 14:29:42.474658166 +0100 @@ -11,10 +11,13 @@ #include #include #include +#include +#include #include #include +#include "xhci-plat.h" #include "xhci-mvebu.h" #define USB3_MAX_WINDOWS 4 @@ -75,3 +78,51 @@ return 0; } + +static int xhci_mvebu_configure_phy(struct xhci_plat_priv *priv, + struct device *dev, const char *phy_name, + int phy_mode) +{ + struct phy *phy; + int error; + + phy = devm_of_phy_get(dev, dev->of_node, phy_name); + if (IS_ERR(phy)) + return PTR_ERR(phy); + + error = phy_set_mode(phy, phy_mode); + if (error) { + dev_err(dev, "unable to set mode of '%s' phy: %d\n", phy_name, + error); + return error; + } + + error = phy_power_on(phy); + if (error) { + dev_err(dev, "unable to power on '%s' phy: %d\n", phy_name, + error); + return error; + } + return 0; +} + +/* + * on A8K only, configure COMPHY (USB3) and UTMI (USB2) phys. + */ +int xhci_mvebu_init_phys(struct usb_hcd *hcd) +{ + struct xhci_plat_priv *priv = hcd_to_xhci_priv(hcd); + struct xhci_hcd *xhci = hcd_to_xhci(hcd);; + int err; + + if (hcd == xhci->shared_hcd) + err = xhci_mvebu_configure_phy(priv, hcd->self.controller, + "usb3", PHY_MODE_USB_HOST); + else + err = xhci_mvebu_configure_phy(priv, hcd->self.controller, + "usb2", UTMI_PHY_USB2_HOST); + + if (err == -EPROBE_DEFER) + return -EPROBE_DEFER; + return 0; +} diff -ruw linux-4.14.127/drivers/usb/host/xhci-mvebu.h linux-4.14.127-fbx/drivers/usb/host/xhci-mvebu.h --- linux-4.14.127/drivers/usb/host/xhci-mvebu.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/usb/host/xhci-mvebu.h 2019-02-15 14:29:42.474658166 +0100 @@ -15,10 +15,15 @@ #if IS_ENABLED(CONFIG_USB_XHCI_MVEBU) int xhci_mvebu_mbus_init_quirk(struct usb_hcd *hcd); +int xhci_mvebu_init_phys(struct usb_hcd *hcd); #else static inline int xhci_mvebu_mbus_init_quirk(struct usb_hcd *hcd) { return 0; } +static inline int xhci_mvebu_init_phys(struct usb_hcd *hcd) +{ + return 0; +} #endif #endif /* __LINUX_XHCI_MVEBU_H */ diff -ruw linux-4.14.127/drivers/usb/host/xhci-plat.c linux-4.14.127-fbx/drivers/usb/host/xhci-plat.c --- linux-4.14.127/drivers/usb/host/xhci-plat.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/usb/host/xhci-plat.c 2019-05-10 11:02:37.544383996 +0200 @@ -99,6 +99,10 @@ .init_quirk = xhci_mvebu_mbus_init_quirk, }; +static const struct xhci_plat_priv xhci_plat_marvell_armada8k = { + .init_quirk = xhci_mvebu_init_phys, +}; + static const struct xhci_plat_priv xhci_plat_renesas_rcar_gen2 = { .firmware_name = XHCI_RCAR_FIRMWARE_NAME_V1, .init_quirk = xhci_rcar_init_quirk, @@ -124,6 +128,9 @@ .compatible = "marvell,armada-380-xhci", .data = &xhci_plat_marvell_armada, }, { + .compatible = "marvell,armada-8k-xhci", + .data = &xhci_plat_marvell_armada8k, + }, { .compatible = "renesas,xhci-r8a7790", .data = &xhci_plat_renesas_rcar_gen2, }, { diff -ruw linux-4.14.127/drivers/usb/storage/usb.c linux-4.14.127-fbx/drivers/usb/storage/usb.c --- linux-4.14.127/drivers/usb/storage/usb.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/usb/storage/usb.c 2019-02-15 14:29:42.546658451 +0100 @@ -83,7 +83,7 @@ MODULE_DESCRIPTION("USB Mass Storage driver for Linux"); MODULE_LICENSE("GPL"); -static unsigned int delay_use = 1; +static unsigned int delay_use = 5; module_param(delay_use, uint, S_IRUGO | S_IWUSR); MODULE_PARM_DESC(delay_use, "seconds to delay before using a new device"); diff -ruw linux-4.14.127/drivers/video/Kconfig linux-4.14.127-fbx/drivers/video/Kconfig --- linux-4.14.127/drivers/video/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/video/Kconfig 2019-02-15 14:29:42.562658514 +0100 @@ -45,5 +45,4 @@ endif - endmenu diff -ruw linux-4.14.127/drivers/video/fbdev/Kconfig linux-4.14.127-fbx/drivers/video/fbdev/Kconfig --- linux-4.14.127/drivers/video/fbdev/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/video/fbdev/Kconfig 2019-02-15 14:29:42.570658546 +0100 @@ -2496,3 +2496,13 @@ This driver is also available as a module. The module will be called sm712fb. If you want to compile it as a module, say M here and read . + +config FB_SSD1327 + tristate "SSD1327 OLED driver" + depends on FB + select FB_SYS_FILLRECT + select FB_SYS_COPYAREA + select FB_SYS_IMAGEBLIT + select FB_SYS_FOPS + select FB_BACKLIGHT + select SPI diff -ruw linux-4.14.127/drivers/video/fbdev/Makefile linux-4.14.127-fbx/drivers/video/fbdev/Makefile --- linux-4.14.127/drivers/video/fbdev/Makefile 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/drivers/video/fbdev/Makefile 2019-02-15 14:29:42.570658546 +0100 @@ -147,6 +147,7 @@ obj-$(CONFIG_FB_MXS) += mxsfb.o obj-$(CONFIG_FB_SSD1307) += ssd1307fb.o obj-$(CONFIG_FB_SIMPLE) += simplefb.o +obj-$(CONFIG_FB_SSD1327) += ssd1327.o # the test framebuffer is last obj-$(CONFIG_FB_VIRTUAL) += vfb.o diff -ruw linux-4.14.127/fs/Kconfig linux-4.14.127-fbx/fs/Kconfig --- linux-4.14.127/fs/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/fs/Kconfig 2019-02-15 14:29:43.494662208 +0100 @@ -126,6 +126,7 @@ source "fs/fat/Kconfig" source "fs/ntfs/Kconfig" +source "fs/exfat/Kconfig" endmenu endif # BLOCK diff -ruw linux-4.14.127/fs/Makefile linux-4.14.127-fbx/fs/Makefile --- linux-4.14.127/fs/Makefile 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/fs/Makefile 2019-02-15 14:29:43.494662208 +0100 @@ -129,3 +129,4 @@ obj-$(CONFIG_CEPH_FS) += ceph/ obj-$(CONFIG_PSTORE) += pstore/ obj-$(CONFIG_EFIVAR_FS) += efivarfs/ +obj-$(CONFIG_EXFAT_FS) += exfat/ diff -ruw linux-4.14.127/fs/exec.c linux-4.14.127-fbx/fs/exec.c --- linux-4.14.127/fs/exec.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/fs/exec.c 2019-05-10 11:02:37.632384355 +0200 @@ -1706,6 +1706,23 @@ return PTR_ERR(filename); /* + * handle current->exec_mode: + * - if unlimited, then nothing to do. + * - if once, then set it to denied and continue (next execve + * after this one will fail). + * - if denied, then effectively fail the execve call with EPERM. + */ + switch (current->exec_mode) { + case EXEC_MODE_UNLIMITED: + break; + case EXEC_MODE_ONCE: + current->exec_mode = EXEC_MODE_DENIED; + break; + case EXEC_MODE_DENIED: + return -EPERM; + } + + /* * We move the actual failure in case of RLIMIT_NPROC excess from * set*uid() to execve() because too many poorly written programs * don't check setuid() return code. Here we additionally recheck diff -ruw linux-4.14.127/fs/proc/array.c linux-4.14.127-fbx/fs/proc/array.c --- linux-4.14.127/fs/proc/array.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/fs/proc/array.c 2019-02-15 14:29:43.942663984 +0100 @@ -155,6 +155,21 @@ return umask; } +static const char *const task_exec_mode_array[] = { + "0 (Denied)", + "1 (Once)", + "2 (Unlimited)", +}; + +static inline const char *get_task_exec_mode(struct task_struct *tsk) +{ + unsigned int exec_mode = tsk->exec_mode; + + if (exec_mode > EXEC_MODE_UNLIMITED) + return "? (Invalid)"; + return task_exec_mode_array[exec_mode]; +} + static inline void task_state(struct seq_file *m, struct pid_namespace *ns, struct pid *pid, struct task_struct *p) { @@ -383,6 +398,12 @@ seq_putc(m, '\n'); } +static inline void task_exec_mode(struct seq_file *m, + struct task_struct *p) +{ + seq_printf(m, "Exec mode: %s\n", get_task_exec_mode(p)); +} + static void task_cpus_allowed(struct seq_file *m, struct task_struct *task) { seq_printf(m, "Cpus_allowed:\t%*pb\n", @@ -409,6 +430,7 @@ task_cpus_allowed(m, task); cpuset_task_status_allowed(m, task); task_context_switch_counts(m, task); + task_exec_mode(m, task); return 0; } diff -ruw linux-4.14.127/fs/xfs/xfs_buf.c linux-4.14.127-fbx/fs/xfs/xfs_buf.c --- linux-4.14.127/fs/xfs/xfs_buf.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/fs/xfs/xfs_buf.c 2019-02-15 14:29:44.026664317 +0100 @@ -441,6 +441,37 @@ return error; } +#ifdef CONFIG_MIPS +static void cache_flush_buf_page(xfs_buf_t *bp, int page_id) +{ + struct page *page; + void *vmaddr, *addr; + + if (!xfs_buf_is_vmapped(bp)) + return; + + page = bp->b_pages[page_id]; + vmaddr = bp->b_addr - bp->b_offset + (page_id * PAGE_CACHE_SIZE); + addr = page_address(page); + + if (pages_do_alias((unsigned long)addr, (unsigned long)vmaddr)) { + local_flush_data_cache_page(vmaddr); + local_flush_data_cache_page(addr); + } +} + +static void cache_flush_buf(xfs_buf_t *bp) +{ + unsigned int i; + + for (i = 0; i < bp->b_page_count; i++) + cache_flush_buf_page(bp, i); +} +#else +static inline void cache_flush_buf_page(xfs_buf_t *bp, int page_id) { } +static inline void cache_flush_buf(xfs_buf_t *bp) { } +#endif + /* * Map buffer into kernel address-space if necessary. */ @@ -480,6 +511,7 @@ if (!bp->b_addr) return -ENOMEM; bp->b_addr += bp->b_offset; + cache_flush_buf(bp); } return 0; @@ -1291,6 +1323,7 @@ if (nbytes > size) nbytes = size; + cache_flush_buf_page(bp, page_index); rbytes = bio_add_page(bio, bp->b_pages[page_index], nbytes, offset); if (rbytes < nbytes) diff -ruw linux-4.14.127/include/asm-generic/vmlinux.lds.h linux-4.14.127-fbx/include/asm-generic/vmlinux.lds.h --- linux-4.14.127/include/asm-generic/vmlinux.lds.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/asm-generic/vmlinux.lds.h 2019-05-10 11:02:37.712384680 +0200 @@ -209,7 +209,7 @@ #define KERNEL_DTB() \ STRUCT_ALIGN(); \ VMLINUX_SYMBOL(__dtb_start) = .; \ - KEEP(*(.dtb.init.rodata)) \ + KEEP(*(.dtb.rodata)) \ VMLINUX_SYMBOL(__dtb_end) = .; /* @@ -286,6 +286,7 @@ . = ALIGN((align)); \ .rodata : AT(ADDR(.rodata) - LOAD_OFFSET) { \ VMLINUX_SYMBOL(__start_rodata) = .; \ + KERNEL_DTB() \ *(.rodata) *(.rodata.*) \ RO_AFTER_INIT_DATA /* Read only after init */ \ KEEP(*(__vermagic)) /* Kernel version magic */ \ @@ -568,7 +569,6 @@ IOMMU_OF_TABLES() \ CPU_METHOD_OF_TABLES() \ CPUIDLE_METHOD_OF_TABLES() \ - KERNEL_DTB() \ IRQCHIP_OF_MATCH_TABLE() \ ACPI_PROBE_TABLE(irqchip) \ ACPI_PROBE_TABLE(timer) \ diff -ruw linux-4.14.127/include/linux/firmware.h linux-4.14.127-fbx/include/linux/firmware.h --- linux-4.14.127/include/linux/firmware.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/linux/firmware.h 2019-02-15 14:29:44.442665966 +0100 @@ -42,6 +42,8 @@ #if defined(CONFIG_FW_LOADER) || (defined(CONFIG_FW_LOADER_MODULE) && defined(MODULE)) int request_firmware(const struct firmware **fw, const char *name, struct device *device); +int request_firmware_nowarn(const struct firmware **fw, const char *name, + struct device *device); int request_firmware_nowait( struct module *module, bool uevent, const char *name, struct device *device, gfp_t gfp, void *context, @@ -59,6 +61,12 @@ { return -EINVAL; } +static inline int request_firmware_nowarn(const struct firmware **fw, + const char *name, + struct device *device) +{ + return -EINVAL; +} static inline int request_firmware_nowait( struct module *module, bool uevent, const char *name, struct device *device, gfp_t gfp, void *context, diff -ruw linux-4.14.127/include/linux/genhd.h linux-4.14.127-fbx/include/linux/genhd.h --- linux-4.14.127/include/linux/genhd.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/linux/genhd.h 2019-02-15 14:29:44.490666156 +0100 @@ -88,6 +88,7 @@ unsigned long ticks[2]; unsigned long io_ticks; unsigned long time_in_queue; + unsigned long io_errors[2]; }; #define PARTITION_META_INFO_VOLNAMELTH 64 @@ -576,6 +577,7 @@ #define ADDPART_FLAG_NONE 0 #define ADDPART_FLAG_RAID 1 #define ADDPART_FLAG_WHOLEDISK 2 +#define ADDPART_FLAG_RO 4 extern int blk_alloc_devt(struct hd_struct *part, dev_t *devt); extern void blk_free_devt(dev_t devt); diff -ruw linux-4.14.127/include/linux/if_vlan.h linux-4.14.127-fbx/include/linux/if_vlan.h --- linux-4.14.127/include/linux/if_vlan.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/linux/if_vlan.h 2019-02-15 14:29:44.502666204 +0100 @@ -17,6 +17,7 @@ #include #include #include +#include #define VLAN_HLEN 4 /* The additional bytes required by VLAN * (in addition to the Ethernet header) @@ -110,6 +111,7 @@ extern struct net_device *__vlan_find_dev_deep_rcu(struct net_device *real_dev, __be16 vlan_proto, u16 vlan_id); extern struct net_device *vlan_dev_real_dev(const struct net_device *dev); +extern struct net_device *vlan_dev_upper_dev(const struct net_device *dev); extern u16 vlan_dev_vlan_id(const struct net_device *dev); extern __be16 vlan_dev_vlan_proto(const struct net_device *dev); @@ -177,7 +179,7 @@ mp = vlan_dev_priv(dev)->egress_priority_map[(skprio & 0xF)]; while (mp) { - if (mp->priority == skprio) { + if (mp->priority == (skprio & TC_H_MIN_MASK)) { return mp->vlan_qos; /* This should already be shifted * to mask correctly with the * VLAN's TCI */ @@ -216,6 +218,12 @@ { BUG(); return NULL; +} + +static inline struct net_device *vlan_dev_upper_dev(const struct net_device *dev) +{ + BUG(); + return NULL; } static inline u16 vlan_dev_vlan_id(const struct net_device *dev) diff -ruw linux-4.14.127/include/linux/in.h linux-4.14.127-fbx/include/linux/in.h --- linux-4.14.127/include/linux/in.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/linux/in.h 2019-02-15 14:29:44.506666220 +0100 @@ -34,6 +34,9 @@ return 0; case IPPROTO_AH: /* SPI */ return 4; + case IPPROTO_IPV6: + /* third byte of ipv6 destination address */ + return 36; default: return -EINVAL; } diff -ruw linux-4.14.127/include/linux/init_task.h linux-4.14.127-fbx/include/linux/init_task.h --- linux-4.14.127/include/linux/init_task.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/linux/init_task.h 2019-02-15 14:29:44.506666220 +0100 @@ -230,6 +230,7 @@ .stack = init_stack, \ .usage = ATOMIC_INIT(2), \ .flags = PF_KTHREAD, \ + .exec_mode = EXEC_MODE_UNLIMITED, \ .prio = MAX_PRIO-20, \ .static_prio = MAX_PRIO-20, \ .normal_prio = MAX_PRIO-20, \ diff -ruw linux-4.14.127/include/linux/miscdevice.h linux-4.14.127-fbx/include/linux/miscdevice.h --- linux-4.14.127/include/linux/miscdevice.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/linux/miscdevice.h 2019-02-15 14:29:44.546666378 +0100 @@ -21,6 +21,7 @@ #define APOLLO_MOUSE_MINOR 7 /* unused */ #define PC110PAD_MINOR 9 /* unused */ /*#define ADB_MOUSE_MINOR 10 FIXME OBSOLETE */ +#define TALDEV_MINOR 74 /* Marvell TAL device */ #define WATCHDOG_MINOR 130 /* Watchdog timer */ #define TEMP_MINOR 131 /* Temperature Sensor */ #define APM_MINOR_DEV 134 diff -ruw linux-4.14.127/include/linux/mtd/mtd.h linux-4.14.127-fbx/include/linux/mtd/mtd.h --- linux-4.14.127/include/linux/mtd/mtd.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/linux/mtd/mtd.h 2019-02-15 14:29:44.558666426 +0100 @@ -267,6 +267,12 @@ */ unsigned int bitflip_threshold; + /* NAND related attributes */ + const char *nand_type; + const char *nand_manufacturer; + const char *onfi_model; + uint8_t onfi_ecc_bits; + // Kernel-only stuff starts here. const char *name; int index; diff -ruw linux-4.14.127/include/linux/mtd/spi-nor.h linux-4.14.127-fbx/include/linux/mtd/spi-nor.h --- linux-4.14.127/include/linux/mtd/spi-nor.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/linux/mtd/spi-nor.h 2019-02-15 14:29:44.562666442 +0100 @@ -54,9 +54,11 @@ #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */ #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */ #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ +#define SPINOR_OP_EWRSR 0x50 /* SST: Enable write to status reg */ #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */ #define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */ #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */ +#define SPINOR_OP_RDID_ALT 0x90 /* Read ID (alt) */ #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */ #define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */ #define SPINOR_OP_RDCR 0x35 /* Read configuration register */ @@ -282,6 +284,9 @@ u32 flags; u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE]; + int four_bytes_enabled; + const void *flash_info; + int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops); void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops); int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len); @@ -292,6 +297,8 @@ ssize_t (*write)(struct spi_nor *nor, loff_t to, size_t len, const u_char *write_buf); int (*erase)(struct spi_nor *nor, loff_t offs); + int (*read_alt_id)(struct spi_nor *nor, u8 cmd, u8 *val, int len); + int (*read_atmel_id)(struct spi_nor *nor, u8 cmd, u8 *val, int len); int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len); int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len); @@ -389,4 +396,6 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, const struct spi_nor_hwcaps *hwcaps); +void spi_nor_reset(struct spi_nor *nor); + #endif diff -ruw linux-4.14.127/include/linux/netdevice.h linux-4.14.127-fbx/include/linux/netdevice.h --- linux-4.14.127/include/linux/netdevice.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/linux/netdevice.h 2019-05-10 11:02:37.732384761 +0200 @@ -67,6 +67,20 @@ struct bpf_prog; struct xdp_buff; +#ifdef CONFIG_NETRXTHREAD + +#define RXTHREAD_MAX_PKTS 512 +struct krxd { + struct sk_buff_head pkt_queue; + unsigned int stats_pkts; + unsigned int stats_dropped; + wait_queue_head_t wq; + struct task_struct *task; +}; + +extern struct krxd gkrxd[CONFIG_NETRXTHREAD_RX_QUEUE]; +#endif + void netdev_set_default_ethtool_ops(struct net_device *dev, const struct ethtool_ops *ops); @@ -1388,6 +1402,8 @@ IFF_PHONY_HEADROOM = 1<<26, IFF_MACSEC = 1<<27, IFF_L3MDEV_RX_HANDLER = 1<<28, + IFF_FBXBRIDGE = 1<<29, + IFF_FBXBRIDGE_PORT = 1<<30, }; #define IFF_802_1Q_VLAN IFF_802_1Q_VLAN @@ -1418,6 +1434,8 @@ #define IFF_RXFH_CONFIGURED IFF_RXFH_CONFIGURED #define IFF_MACSEC IFF_MACSEC #define IFF_L3MDEV_RX_HANDLER IFF_L3MDEV_RX_HANDLER +#define IFF_FBXBRIDGE IFF_FBXBRIDGE +#define IFF_FBXBRIDGE_PORT IFF_FBXBRIDGE_PORT /** * struct net_device - The DEVICE structure. @@ -1873,6 +1891,7 @@ #endif struct device dev; + const struct attribute_group *sysfs_groups[4]; const struct attribute_group *sysfs_rx_queue_group; diff -ruw linux-4.14.127/include/linux/netfilter/nf_conntrack_ftp.h linux-4.14.127-fbx/include/linux/netfilter/nf_conntrack_ftp.h --- linux-4.14.127/include/linux/netfilter/nf_conntrack_ftp.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/linux/netfilter/nf_conntrack_ftp.h 2019-02-15 14:29:44.566666457 +0100 @@ -18,6 +18,11 @@ u_int16_t seq_aft_nl_num[IP_CT_DIR_MAX]; /* pickup sequence tracking, useful for conntrackd */ u_int16_t flags[IP_CT_DIR_MAX]; +#if defined(CONFIG_FREEBOX_BRIDGE) || defined(CONFIG_FREEBOX_BRIDGE_MODULE) + unsigned int is_fbxbridge; + unsigned long fbxbridge_remote; + unsigned long fbxbridge_wan; +#endif }; struct nf_conntrack_expect; diff -ruw linux-4.14.127/include/linux/netfilter/nf_conntrack_tcp.h linux-4.14.127-fbx/include/linux/netfilter/nf_conntrack_tcp.h --- linux-4.14.127/include/linux/netfilter/nf_conntrack_tcp.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/linux/netfilter/nf_conntrack_tcp.h 2019-02-15 14:29:44.566666457 +0100 @@ -28,6 +28,7 @@ /* For SYN packets while we may be out-of-sync */ u_int8_t last_wscale; /* Last window scaling factor seen */ u_int8_t last_flags; /* Last flags set */ + u_int32_t no_window_track; }; #endif /* _NF_CONNTRACK_TCP_H */ diff -ruw linux-4.14.127/include/linux/of_fdt.h linux-4.14.127-fbx/include/linux/of_fdt.h --- linux-4.14.127/include/linux/of_fdt.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/linux/of_fdt.h 2019-02-15 14:29:44.574666489 +0100 @@ -99,6 +99,7 @@ extern void early_get_first_memblock_info(void *, phys_addr_t *); extern u64 of_flat_dt_translate_address(unsigned long node); extern void of_fdt_limit_memory(int limit); +const void *of_fdt_find_compatible_dtb(const char *name); #else /* CONFIG_OF_FLATTREE */ static inline int early_init_dt_scan_chosen_stdout(void) { return -ENODEV; } static inline void early_init_fdt_scan_reserved_mem(void) {} diff -ruw linux-4.14.127/include/linux/of_reserved_mem.h linux-4.14.127-fbx/include/linux/of_reserved_mem.h --- linux-4.14.127/include/linux/of_reserved_mem.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/linux/of_reserved_mem.h 2019-02-15 14:29:44.574666489 +0100 @@ -26,6 +26,10 @@ typedef int (*reservedmem_of_init_fn)(struct reserved_mem *rmem); +#define MAX_RESERVED_REGIONS 32 +extern struct reserved_mem reserved_mem[MAX_RESERVED_REGIONS]; +extern int reserved_mem_count; + #define RESERVEDMEM_OF_DECLARE(name, compat, init) \ _OF_DECLARE(reservedmem, name, compat, init, reservedmem_of_init_fn) @@ -35,6 +39,8 @@ struct device_node *np, int idx); void of_reserved_mem_device_release(struct device *dev); +struct reserved_mem *of_get_reserved_mem_by_idx(struct device_node *np, int idx); + int early_init_dt_alloc_reserved_memory_arch(phys_addr_t size, phys_addr_t align, phys_addr_t start, @@ -53,6 +59,12 @@ } static inline void of_reserved_mem_device_release(struct device *pdev) { } +static inline struct reserved_mem *of_get_reserved_mem_by_idx(struct device_node *np, + int idx) +{ + return NULL; +} + static inline void fdt_init_reserved_mem(void) { } static inline void fdt_reserved_mem_save_node(unsigned long node, const char *uname, phys_addr_t base, phys_addr_t size) { } diff -ruw linux-4.14.127/include/linux/pci_ids.h linux-4.14.127-fbx/include/linux/pci_ids.h --- linux-4.14.127/include/linux/pci_ids.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/linux/pci_ids.h 2019-02-15 14:29:44.582666521 +0100 @@ -3064,4 +3064,7 @@ #define PCI_VENDOR_ID_NCUBE 0x10ff +#define PCI_VENDOR_ID_PERICOM 0x12d8 +#define PCI_DEVICE_ID_PI7C9X20303SL 0xa303 + #endif /* _LINUX_PCI_IDS_H */ diff -ruw linux-4.14.127/include/linux/phy/phy.h linux-4.14.127-fbx/include/linux/phy/phy.h --- linux-4.14.127/include/linux/phy/phy.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/linux/phy/phy.h 2019-02-15 14:29:44.582666521 +0100 @@ -28,7 +28,10 @@ PHY_MODE_USB_DEVICE, PHY_MODE_USB_OTG, PHY_MODE_SGMII, + PHY_MODE_HS_SGMII, PHY_MODE_10GKR, + PHY_MODE_SATA, + PHY_MODE_PCIE, }; /** @@ -39,6 +42,7 @@ * @power_off: powering off the phy * @set_mode: set the mode of the phy * @reset: resetting the phy + * @is_pll_locked: check phy's PLL status (locked/unlocked) * @owner: the module owner containing the ops */ struct phy_ops { @@ -48,6 +52,7 @@ int (*power_off)(struct phy *phy); int (*set_mode)(struct phy *phy, enum phy_mode mode); int (*reset)(struct phy *phy); + int (*is_pll_locked)(struct phy *phy); struct module *owner; }; @@ -141,6 +146,7 @@ int phy_power_off(struct phy *phy); int phy_set_mode(struct phy *phy, enum phy_mode mode); int phy_reset(struct phy *phy); +int phy_is_pll_locked(struct phy *phy); static inline int phy_get_bus_width(struct phy *phy) { return phy->attrs.bus_width; @@ -259,6 +265,13 @@ { if (!phy) return 0; + return -ENOSYS; +} + +static inline int phy_is_pll_locked(struct phy *phy) +{ + if (!phy) + return 0; return -ENOSYS; } diff -ruw linux-4.14.127/include/linux/ppp_channel.h linux-4.14.127-fbx/include/linux/ppp_channel.h --- linux-4.14.127/include/linux/ppp_channel.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/linux/ppp_channel.h 2019-02-15 14:29:44.602666600 +0100 @@ -49,6 +49,9 @@ /* Called by the channel when it can send some more data. */ extern void ppp_output_wakeup(struct ppp_channel *); +/* Called by the channel when it want to prevent further transmit on it */ +extern void ppp_output_stop(struct ppp_channel *); + /* Called by the channel to process a received PPP packet. The packet should have just the 2-byte PPP protocol header. */ extern void ppp_input(struct ppp_channel *, struct sk_buff *); diff -ruw linux-4.14.127/include/linux/regmap.h linux-4.14.127-fbx/include/linux/regmap.h --- linux-4.14.127/include/linux/regmap.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/linux/regmap.h 2019-02-15 14:29:44.610666632 +0100 @@ -1002,6 +1002,7 @@ int regmap_irq_get_virq(struct regmap_irq_chip_data *data, int irq); struct irq_domain *regmap_irq_get_domain(struct regmap_irq_chip_data *data); +void __iomem *regmap_get_mmio_base_address(struct regmap *map); #else /* diff -ruw linux-4.14.127/include/linux/sched.h linux-4.14.127-fbx/include/linux/sched.h --- linux-4.14.127/include/linux/sched.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/linux/sched.h 2019-02-15 14:29:44.618666663 +0100 @@ -556,6 +556,12 @@ struct wake_q_node *next; }; +enum task_exec_mode { + EXEC_MODE_DENIED, + EXEC_MODE_ONCE, + EXEC_MODE_UNLIMITED, +}; + struct task_struct { #ifdef CONFIG_THREAD_INFO_IN_TASK /* @@ -578,6 +584,7 @@ /* Per task flags (PF_*), defined further below: */ unsigned int flags; unsigned int ptrace; + enum task_exec_mode exec_mode; #ifdef CONFIG_SMP struct llist_node wake_entry; diff -ruw linux-4.14.127/include/linux/skbuff.h linux-4.14.127-fbx/include/linux/skbuff.h --- linux-4.14.127/include/linux/skbuff.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/linux/skbuff.h 2019-07-22 10:44:48.230828526 +0200 @@ -582,6 +582,13 @@ typedef unsigned char *sk_buff_data_t; #endif +enum { + FFN_STATE_INIT = 0, + FFN_STATE_FORWARDABLE, + FFN_STATE_FAST_FORWARDED, + FFN_STATE_INCOMPATIBLE, +}; + /** * struct sk_buff - socket buffer * @next: Next buffer in list @@ -700,14 +707,23 @@ #if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE) unsigned long _nfct; #endif +#if defined(CONFIG_IP_FFN) || defined(CONFIG_IPV6_FFN) + int ffn_state; + int ffn_orig_tos; +#endif #if IS_ENABLED(CONFIG_BRIDGE_NETFILTER) struct nf_bridge_info *nf_bridge; #endif + unsigned int len, data_len; __u16 mac_len, hdr_len; +#ifdef CONFIG_NETRXTHREAD + int rxthread_prio; +#endif + /* Following fields are _not_ copied in __copy_skb_header() * Note that queue_mapping is here mostly to fill a hole. */ @@ -2477,6 +2493,10 @@ * get_rps_cpus() for example only access one 64 bytes aligned block : * NET_IP_ALIGN(2) + ethernet_header(14) + IP_header(20/40) + ports(8) */ +#ifdef CONFIG_NETSKBPAD +#define NET_SKB_PAD CONFIG_NETSKBPAD +#endif + #ifndef NET_SKB_PAD #define NET_SKB_PAD max(32, L1_CACHE_BYTES) #endif diff -ruw linux-4.14.127/include/linux/tcp.h linux-4.14.127-fbx/include/linux/tcp.h --- linux-4.14.127/include/linux/tcp.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/linux/tcp.h 2019-07-22 10:44:48.234828542 +0200 @@ -218,7 +218,7 @@ unused:3; u8 nonagle : 4,/* Disable Nagle algorithm? */ thin_lto : 1,/* Use linear timeouts for thin streams */ - unused1 : 1, + linear_rto : 1, repair : 1, frto : 1;/* F-RTO (RFC5682) activated in CA_Loss */ u8 repair_queue; diff -ruw linux-4.14.127/include/net/cfg80211.h linux-4.14.127-fbx/include/net/cfg80211.h --- linux-4.14.127/include/net/cfg80211.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/net/cfg80211.h 2019-02-15 14:29:44.686666933 +0100 @@ -119,6 +119,7 @@ (IEEE80211_CHAN_NO_HT40PLUS | IEEE80211_CHAN_NO_HT40MINUS) #define IEEE80211_DFS_MIN_CAC_TIME_MS 60000 +#define IEEE80211_DFS_WEATHER_MIN_CAC_TIME_MS 600000 #define IEEE80211_DFS_MIN_NOP_TIME_MS (30 * 60 * 1000) /** diff -ruw linux-4.14.127/include/net/ip.h linux-4.14.127-fbx/include/net/ip.h --- linux-4.14.127/include/net/ip.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/net/ip.h 2019-05-10 11:02:37.752384843 +0200 @@ -572,6 +572,20 @@ #endif /* + * Functions provided by ip_ffn.c + */ + +enum { + IP_FFN_FINISH_OUT, + IP_FFN_LOCAL_IN, +}; + +extern void ip_ffn_init(void); +extern int ip_ffn_process(struct sk_buff *skb); +extern void ip_ffn_add(struct sk_buff *skb, int when); +extern void ip_ffn_flush_all(void); + +/* * Functions provided by ip_forward.c */ diff -ruw linux-4.14.127/include/net/ip6_route.h linux-4.14.127-fbx/include/net/ip6_route.h --- linux-4.14.127/include/net/ip6_route.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/net/ip6_route.h 2019-05-10 11:02:37.752384843 +0200 @@ -165,6 +165,9 @@ void rt6_remove_prefsrc(struct inet6_ifaddr *ifp); void rt6_clean_tohost(struct net *net, struct in6_addr *gateway); +void rt6_uncached_list_add(struct rt6_info *rt); +void rt6_uncached_list_del(struct rt6_info *rt); + static inline const struct rt6_info *skb_rt6_info(const struct sk_buff *skb) { const struct dst_entry *dst = skb_dst(skb); diff -ruw linux-4.14.127/include/net/ip6_tunnel.h linux-4.14.127-fbx/include/net/ip6_tunnel.h --- linux-4.14.127/include/net/ip6_tunnel.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/net/ip6_tunnel.h 2019-02-15 14:29:44.694666965 +0100 @@ -18,6 +18,18 @@ /* determine capability on a per-packet basis */ #define IP6_TNL_F_CAP_PER_PACKET 0x40000 +/* IPv6 tunnel FMR */ +struct __ip6_tnl_fmr { + struct __ip6_tnl_fmr *next; /* next fmr in list */ + struct in6_addr ip6_prefix; + struct in_addr ip4_prefix; + + __u8 ip6_prefix_len; + __u8 ip4_prefix_len; + __u8 ea_len; + __u8 offset; +}; + struct __ip6_tnl_parm { char name[IFNAMSIZ]; /* name of tunnel device */ int link; /* ifindex of underlying L2 interface */ @@ -29,6 +41,7 @@ __u32 flags; /* tunnel flags */ struct in6_addr laddr; /* local tunnel end-point address */ struct in6_addr raddr; /* remote tunnel end-point address */ + struct __ip6_tnl_fmr *fmrs; /* FMRs */ __be16 i_flags; __be16 o_flags; diff -ruw linux-4.14.127/include/net/ipv6.h linux-4.14.127-fbx/include/net/ipv6.h --- linux-4.14.127/include/net/ipv6.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/net/ipv6.h 2019-07-22 10:44:48.234828542 +0200 @@ -876,6 +876,7 @@ int ip6_output(struct net *net, struct sock *sk, struct sk_buff *skb); int ip6_forward(struct sk_buff *skb); int ip6_input(struct sk_buff *skb); +int ip6_input_finish(struct net *net, struct sock *sk, struct sk_buff *skb); int ip6_mc_input(struct sk_buff *skb); int __ip6_local_out(struct net *net, struct sock *sk, struct sk_buff *skb); @@ -1003,4 +1004,19 @@ const struct in6_addr *addr); int ipv6_sock_mc_drop(struct sock *sk, int ifindex, const struct in6_addr *addr); + +/* + * Functions provided by ipv6_ffn.c + */ + +enum { + IPV6_FFN_FINISH_OUT, + IPV6_FFN_LOCAL_IN, +}; + +extern void ipv6_ffn_init(void); +extern int ipv6_ffn_process(struct sk_buff *skb); +extern void ipv6_ffn_add(struct sk_buff *skb, int when); +extern void ipv6_ffn_flush_all(void); + #endif /* _NET_IPV6_H */ diff -ruw linux-4.14.127/include/net/mac80211.h linux-4.14.127-fbx/include/net/mac80211.h --- linux-4.14.127/include/net/mac80211.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/net/mac80211.h 2019-02-15 14:29:44.698666981 +0100 @@ -2099,6 +2099,8 @@ IEEE80211_HW_REPORTS_LOW_ACK, IEEE80211_HW_SUPPORTS_TX_FRAG, + IEEE80211_HW_APVLAN_NEED_MCAST_TO_UCAST, + /* keep last, obviously */ NUM_IEEE80211_HW_FLAGS }; @@ -3467,6 +3469,8 @@ struct sk_buff *skb); int (*start)(struct ieee80211_hw *hw); void (*stop)(struct ieee80211_hw *hw); + int (*set_powered)(struct ieee80211_hw *hw); + int (*get_powered)(struct ieee80211_hw *hw, bool *up, bool *busy); #ifdef CONFIG_PM int (*suspend)(struct ieee80211_hw *hw, struct cfg80211_wowlan *wowlan); int (*resume)(struct ieee80211_hw *hw); diff -ruw linux-4.14.127/include/net/netfilter/nf_conntrack.h linux-4.14.127-fbx/include/net/netfilter/nf_conntrack.h --- linux-4.14.127/include/net/netfilter/nf_conntrack.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/net/netfilter/nf_conntrack.h 2019-07-22 10:44:48.238828559 +0200 @@ -93,6 +93,9 @@ u_int32_t secmark; #endif + union nf_conntrack_man_proto nat_src_proto_min; + union nf_conntrack_man_proto nat_src_proto_max; + /* Extensions */ struct nf_ct_ext *ext; diff -ruw linux-4.14.127/include/net/route.h linux-4.14.127-fbx/include/net/route.h --- linux-4.14.127/include/net/route.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/net/route.h 2019-05-10 11:02:37.752384843 +0200 @@ -228,6 +228,9 @@ void fib_add_ifaddr(struct in_ifaddr *); void fib_del_ifaddr(struct in_ifaddr *, struct in_ifaddr *); +void rt_add_uncached_list(struct rtable *rt); +void rt_del_uncached_list(struct rtable *rt); + static inline void ip_rt_put(struct rtable *rt) { /* dst_release() accepts a NULL parameter. diff -ruw linux-4.14.127/include/net/sock.h linux-4.14.127-fbx/include/net/sock.h --- linux-4.14.127/include/net/sock.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/net/sock.h 2019-05-10 11:02:37.756384859 +0200 @@ -177,6 +177,7 @@ unsigned char skc_reuseport:1; unsigned char skc_ipv6only:1; unsigned char skc_net_refcnt:1; + unsigned char skc_reuse_conflict; int skc_bound_dev_if; union { struct hlist_node skc_bind_node; @@ -341,6 +342,7 @@ #define sk_reuseport __sk_common.skc_reuseport #define sk_ipv6only __sk_common.skc_ipv6only #define sk_net_refcnt __sk_common.skc_net_refcnt +#define sk_reuse_conflict __sk_common.skc_reuse_conflict #define sk_bound_dev_if __sk_common.skc_bound_dev_if #define sk_bind_node __sk_common.skc_bind_node #define sk_prot __sk_common.skc_prot @@ -781,6 +783,7 @@ SOCK_FILTER_LOCKED, /* Filter cannot be changed anymore */ SOCK_SELECT_ERR_QUEUE, /* Wake select on error queue */ SOCK_RCU_FREE, /* wait rcu grace period in sk_destruct() */ + SOCK_UDP_DUP_UNICAST, }; #define SK_FLAGS_TIMESTAMP ((1UL << SOCK_TIMESTAMP) | (1UL << SOCK_TIMESTAMPING_RX_SOFTWARE)) diff -ruw linux-4.14.127/include/uapi/asm-generic/socket.h linux-4.14.127-fbx/include/uapi/asm-generic/socket.h --- linux-4.14.127/include/uapi/asm-generic/socket.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/uapi/asm-generic/socket.h 2019-02-15 14:29:44.758667219 +0100 @@ -107,4 +107,6 @@ #define SO_ZEROCOPY 60 +#define SO_UDP_DUP_UNICAST 61 + #endif /* __ASM_GENERIC_SOCKET_H */ diff -ruw linux-4.14.127/include/uapi/linux/if_ether.h linux-4.14.127-fbx/include/uapi/linux/if_ether.h --- linux-4.14.127/include/uapi/linux/if_ether.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/uapi/linux/if_ether.h 2019-05-10 11:02:37.760384876 +0200 @@ -23,6 +23,7 @@ #define _UAPI_LINUX_IF_ETHER_H #include +#include /* * IEEE 802.3 Ethernet magic constants. The frame sizes omit the preamble diff -ruw linux-4.14.127/include/uapi/linux/if_tun.h linux-4.14.127-fbx/include/uapi/linux/if_tun.h --- linux-4.14.127/include/uapi/linux/if_tun.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/uapi/linux/if_tun.h 2019-02-15 14:29:44.782667314 +0100 @@ -58,6 +58,32 @@ #define TUNSETVNETBE _IOW('T', 222, int) #define TUNGETVNETBE _IOR('T', 223, int) + +struct smalltun_rule { + __u8 proto; + __be16 src_port_start; + __be16 src_port_end; + __be16 dst_port_start; + __be16 dst_port_end; +}; + +struct smalltun_fp { + __be32 inner_src; + __be32 inner_dst; + + __u32 af; + __u8 outer_src[16]; + __u8 outer_dst[16]; + __be16 outer_src_port; + __be16 outer_dst_port; + + struct smalltun_rule rules[8]; + __u32 rule_count; +}; + +#define TUNSMALLTUNSETFP _IOW('T', 224, struct smalltun_fp) +#define TUNSMALLTUNDELFP _IOW('T', 225, struct smalltun_fp) + /* TUNSETIFF ifr flags */ #define IFF_TUN 0x0001 #define IFF_TAP 0x0002 diff -ruw linux-4.14.127/include/uapi/linux/if_tunnel.h linux-4.14.127-fbx/include/uapi/linux/if_tunnel.h --- linux-4.14.127/include/uapi/linux/if_tunnel.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/uapi/linux/if_tunnel.h 2019-02-15 14:29:44.782667314 +0100 @@ -77,10 +77,23 @@ IFLA_IPTUN_ENCAP_DPORT, IFLA_IPTUN_COLLECT_METADATA, IFLA_IPTUN_FWMARK, + IFLA_IPTUN_FMRS, __IFLA_IPTUN_MAX, }; #define IFLA_IPTUN_MAX (__IFLA_IPTUN_MAX - 1) +enum { + IFLA_IPTUN_FMR_UNSPEC, + IFLA_IPTUN_FMR_IP6_PREFIX, + IFLA_IPTUN_FMR_IP4_PREFIX, + IFLA_IPTUN_FMR_IP6_PREFIX_LEN, + IFLA_IPTUN_FMR_IP4_PREFIX_LEN, + IFLA_IPTUN_FMR_EA_LEN, + IFLA_IPTUN_FMR_OFFSET, + __IFLA_IPTUN_FMR_MAX, +}; +#define IFLA_IPTUN_FMR_MAX (__IFLA_IPTUN_FMR_MAX - 1) + enum tunnel_encap_types { TUNNEL_ENCAP_NONE, TUNNEL_ENCAP_FOU, diff -ruw linux-4.14.127/include/uapi/linux/libc-compat.h linux-4.14.127-fbx/include/uapi/linux/libc-compat.h --- linux-4.14.127/include/uapi/linux/libc-compat.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/uapi/linux/libc-compat.h 2019-02-15 14:29:44.790667345 +0100 @@ -49,11 +49,11 @@ #ifndef _UAPI_LIBC_COMPAT_H #define _UAPI_LIBC_COMPAT_H -/* We have included glibc headers... */ -#if defined(__GLIBC__) +/* We have included libc headers... */ +#if !defined(__KERNEL__) -/* Coordinate with glibc net/if.h header. */ -#if defined(_NET_IF_H) && defined(__USE_MISC) +/* Coordinate with libc net/if.h header. */ +#if defined(_NET_IF_H) && (!defined(__GLIBC__) || defined(__USE_MISC)) /* GLIBC headers included first so don't define anything * that would already be defined. */ @@ -65,9 +65,11 @@ /* Everything up to IFF_DYNAMIC, matches net/if.h until glibc 2.23 */ #define __UAPI_DEF_IF_NET_DEVICE_FLAGS 0 /* For the future if glibc adds IFF_LOWER_UP, IFF_DORMANT and IFF_ECHO */ +#ifndef IFF_ECHO #ifndef __UAPI_DEF_IF_NET_DEVICE_FLAGS_LOWER_UP_DORMANT_ECHO #define __UAPI_DEF_IF_NET_DEVICE_FLAGS_LOWER_UP_DORMANT_ECHO 1 #endif /* __UAPI_DEF_IF_NET_DEVICE_FLAGS_LOWER_UP_DORMANT_ECHO */ +#endif /* IFF_ECHO */ #else /* _NET_IF_H */ @@ -86,6 +88,14 @@ #endif /* _NET_IF_H */ +/* musl defines the ethhdr struct itself in its netinet/if_ether.h. + * Glibc just includes the kernel header and uses a different guard. */ +#if defined(_NETINET_IF_ETHER_H) +#define __UAPI_DEF_ETHHDR 0 +#else +#define __UAPI_DEF_ETHHDR 1 +#endif + /* Coordinate with glibc netinet/in.h header. */ #if defined(_NETINET_IN_H) @@ -194,6 +204,9 @@ #define __UAPI_DEF_IF_NET_DEVICE_FLAGS_LOWER_UP_DORMANT_ECHO 1 #endif +/* Definitions for if_ether.h */ +#define __UAPI_DEF_ETHHDR 1 + /* Definitions for in.h */ #ifndef __UAPI_DEF_IN_ADDR #define __UAPI_DEF_IN_ADDR 1 @@ -262,6 +275,6 @@ #define __UAPI_DEF_XATTR 1 #endif -#endif /* __GLIBC__ */ +#endif /* __KERNEL__ */ #endif /* _UAPI_LIBC_COMPAT_H */ diff -ruw linux-4.14.127/include/uapi/linux/sockios.h linux-4.14.127-fbx/include/uapi/linux/sockios.h --- linux-4.14.127/include/uapi/linux/sockios.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/uapi/linux/sockios.h 2019-02-15 14:29:44.818667456 +0100 @@ -132,6 +132,14 @@ #define SIOCSHWTSTAMP 0x89b0 /* set and get config */ #define SIOCGHWTSTAMP 0x89b1 /* get config */ +/* fbxbridge call */ +#define SIOCGFBXBRIDGE 0x89c0 /* fbxbridge support */ +#define SIOCSFBXBRIDGE 0x89c1 /* Set fbxbridge options */ + +/* fbxdiverter call */ +#define SIOCGFBXDIVERT 0x89d0 /* fbxdiverter support */ +#define SIOCSFBXDIVERT 0x89d1 /* Set fbxdiverter options */ + /* Device private ioctl calls */ /* diff -ruw linux-4.14.127/include/uapi/linux/swab.h linux-4.14.127-fbx/include/uapi/linux/swab.h --- linux-4.14.127/include/uapi/linux/swab.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/uapi/linux/swab.h 2019-02-15 14:29:44.818667456 +0100 @@ -3,7 +3,7 @@ #define _UAPI_LINUX_SWAB_H #include -#include +#include #include /* diff -ruw linux-4.14.127/include/uapi/linux/tcp.h linux-4.14.127-fbx/include/uapi/linux/tcp.h --- linux-4.14.127/include/uapi/linux/tcp.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/uapi/linux/tcp.h 2019-02-15 14:29:44.822667472 +0100 @@ -121,6 +121,8 @@ #define TCP_ULP 31 /* Attach a ULP to a TCP connection */ #define TCP_MD5SIG_EXT 32 /* TCP MD5 Signature with extensions */ +#define TCP_LINEAR_RTO 128 /* force use of linear timeouts */ + struct tcp_repair_opt { __u32 opt_code; __u32 opt_val; diff -ruw linux-4.14.127/include/uapi/linux/tty.h linux-4.14.127-fbx/include/uapi/linux/tty.h --- linux-4.14.127/include/uapi/linux/tty.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/include/uapi/linux/tty.h 2019-02-15 14:29:44.822667472 +0100 @@ -38,5 +38,6 @@ #define N_NCI 25 /* NFC NCI UART */ #define N_SPEAKUP 26 /* Speakup communication with synths */ #define N_NULL 27 /* Null ldisc used for error handling */ +#define N_REMOTI 28 /* RemoTI over UART */ #endif /* _UAPI_LINUX_TTY_H */ diff -ruw linux-4.14.127/init/Kconfig linux-4.14.127-fbx/init/Kconfig --- linux-4.14.127/init/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/init/Kconfig 2019-02-15 14:29:44.846667567 +0100 @@ -577,6 +577,15 @@ 13 => 8 KB for each CPU 12 => 4 KB for each CPU +config FBX_DECRYPT_INITRD + bool "Decrypt initrd at boot" + depends on BLK_DEV_RAM + default n + +config FBX_DECRYPT_INITRD_KEY + string "Decryption key" + depends on FBX_DECRYPT_INITRD + # # Architectures with an unreliable sched_clock() should select this: # diff -ruw linux-4.14.127/init/Makefile linux-4.14.127-fbx/init/Makefile --- linux-4.14.127/init/Makefile 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/init/Makefile 2019-02-15 14:29:44.846667567 +0100 @@ -16,6 +16,7 @@ ifneq ($(CONFIG_ARCH_INIT_TASK),y) obj-y += init_task.o endif +obj-$(CONFIG_FBX_DECRYPT_INITRD)+= fbx_decrypt_initrd.o rc4.o mounts-y := do_mounts.o mounts-$(CONFIG_BLK_DEV_RAM) += do_mounts_rd.o diff -ruw linux-4.14.127/init/initramfs.c linux-4.14.127-fbx/init/initramfs.c --- linux-4.14.127/init/initramfs.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/init/initramfs.c 2019-02-15 14:29:44.846667567 +0100 @@ -632,7 +632,18 @@ fd = sys_open("/initrd.image", O_WRONLY|O_CREAT, 0700); if (fd >= 0) { - ssize_t written = xwrite(fd, (char *)initrd_start, + ssize_t written; +#ifdef CONFIG_FBX_DECRYPT_INITRD + int err; + extern int fbx_decrypt_initrd(char *start, + u32 size); + + err = fbx_decrypt_initrd((char*)initrd_start, + initrd_end - initrd_start); + if (err) + printk(KERN_ERR "Decrypt failed: %i\n", err); +#endif + written = xwrite(fd, (char *)initrd_start, initrd_end - initrd_start); if (written != initrd_end - initrd_start) diff -ruw linux-4.14.127/kernel/fork.c linux-4.14.127-fbx/kernel/fork.c --- linux-4.14.127/kernel/fork.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/kernel/fork.c 2019-07-22 10:44:48.254828625 +0200 @@ -584,6 +584,11 @@ tsk->fail_nth = 0; #endif + /* + * inherit parent exec_mode. + */ + tsk->exec_mode = orig->exec_mode; + return tsk; free_stack: diff -ruw linux-4.14.127/kernel/sys.c linux-4.14.127-fbx/kernel/sys.c --- linux-4.14.127/kernel/sys.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/kernel/sys.c 2019-07-22 10:44:48.270828690 +0200 @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -2396,6 +2397,18 @@ case PR_GET_FP_MODE: error = GET_FP_MODE(me); break; + case PR_SET_EXEC_MODE: + if (arg2 != EXEC_MODE_UNLIMITED && + arg2 != EXEC_MODE_ONCE && + arg2 != EXEC_MODE_DENIED) + return -EINVAL; + + if (arg2 > current->exec_mode) + return -EPERM; + current->exec_mode = arg2; + return 0; + case PR_GET_EXEC_MODE: + return current->exec_mode; case PR_GET_SPECULATION_CTRL: if (arg3 || arg4 || arg5) return -EINVAL; diff -ruw linux-4.14.127/lib/Kconfig linux-4.14.127-fbx/lib/Kconfig --- linux-4.14.127/lib/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/lib/Kconfig 2019-02-15 14:29:44.986668122 +0100 @@ -586,4 +586,11 @@ config STRING_SELFTEST bool "Test string functions" +config ARCH_HAS_FBXSERIAL + bool + +config FBXSERIAL + bool "fbxserial" + select CRC32 + endmenu diff -ruw linux-4.14.127/lib/Kconfig.ubsan linux-4.14.127-fbx/lib/Kconfig.ubsan --- linux-4.14.127/lib/Kconfig.ubsan 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/lib/Kconfig.ubsan 2019-03-29 17:33:21.529534915 +0100 @@ -1,9 +1,6 @@ config ARCH_HAS_UBSAN_SANITIZE_ALL bool -config ARCH_WANTS_UBSAN_NO_NULL - def_bool n - config UBSAN bool "Undefined behaviour sanity checker" help @@ -38,11 +35,3 @@ This option enables detection of unaligned memory accesses. Enabling this option on architectures that support unaligned accesses may produce a lot of false positives. - -config UBSAN_NULL - bool "Enable checking of null pointers" - depends on UBSAN - default y if !ARCH_WANTS_UBSAN_NO_NULL - help - This option enables detection of memory accesses via a - null pointer. diff -ruw linux-4.14.127/lib/Makefile linux-4.14.127-fbx/lib/Makefile --- linux-4.14.127/lib/Makefile 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/lib/Makefile 2019-07-22 10:44:48.278828723 +0200 @@ -260,3 +260,5 @@ obj-$(CONFIG_SBITMAP) += sbitmap.o obj-$(CONFIG_PARMAN) += parman.o + +obj-$(CONFIG_FBXSERIAL) += fbxserial.o diff -ruw linux-4.14.127/net/8021q/vlan.c linux-4.14.127-fbx/net/8021q/vlan.c --- linux-4.14.127/net/8021q/vlan.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/8021q/vlan.c 2019-02-15 14:29:45.082668502 +0100 @@ -203,7 +203,7 @@ /* Attach a VLAN device to a mac address (ie Ethernet Card). * Returns 0 if the device was created or a negative error code otherwise. */ -static int register_vlan_device(struct net_device *real_dev, u16 vlan_id) +int register_vlan_device(struct net_device *real_dev, u16 vlan_id) { struct net_device *new_dev; struct vlan_dev_priv *vlan; diff -ruw linux-4.14.127/net/8021q/vlan_core.c linux-4.14.127-fbx/net/8021q/vlan_core.c --- linux-4.14.127/net/8021q/vlan_core.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/8021q/vlan_core.c 2019-02-15 14:29:45.082668502 +0100 @@ -98,6 +98,12 @@ } EXPORT_SYMBOL(__vlan_find_dev_deep_rcu); +struct net_device *vlan_dev_upper_dev(const struct net_device *dev) +{ + return vlan_dev_priv(dev)->real_dev; +} +EXPORT_SYMBOL(vlan_dev_upper_dev); + struct net_device *vlan_dev_real_dev(const struct net_device *dev) { struct net_device *ret = vlan_dev_priv(dev)->real_dev; diff -ruw linux-4.14.127/net/Kconfig linux-4.14.127-fbx/net/Kconfig --- linux-4.14.127/net/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/Kconfig 2019-02-15 14:29:45.086668518 +0100 @@ -53,6 +53,18 @@ menu "Networking options" +config NETSKBPAD + int "Size reserved by dev_alloc_skb" + default 32 + +config NETRXTHREAD + bool "Do rx network processing in kernel thread" + +config NETRXTHREAD_RX_QUEUE + int "Number of rx queues" + default 1 + depends on NETRXTHREAD + source "net/packet/Kconfig" source "net/unix/Kconfig" source "net/tls/Kconfig" @@ -206,6 +218,8 @@ source "net/tipc/Kconfig" source "net/atm/Kconfig" source "net/l2tp/Kconfig" +source "net/fbxatm/Kconfig" +source "net/fbxbridge/Kconfig" source "net/802/Kconfig" source "net/bridge/Kconfig" source "net/dsa/Kconfig" diff -ruw linux-4.14.127/net/Makefile linux-4.14.127-fbx/net/Makefile --- linux-4.14.127/net/Makefile 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/Makefile 2019-02-15 14:29:45.086668518 +0100 @@ -39,6 +39,12 @@ obj-$(CONFIG_STREAM_PARSER) += strparser/ obj-$(CONFIG_ATM) += atm/ obj-$(CONFIG_L2TP) += l2tp/ +ifneq ($(CONFIG_FBXATM),) +obj-y += fbxatm/ +endif +ifneq ($(CONFIG_FBXBRIDGE),) +obj-y += fbxbridge/ +endif obj-$(CONFIG_DECNET) += decnet/ obj-$(CONFIG_PHONET) += phonet/ ifneq ($(CONFIG_VLAN_8021Q),) diff -ruw linux-4.14.127/net/bridge/br_device.c linux-4.14.127-fbx/net/bridge/br_device.c --- linux-4.14.127/net/bridge/br_device.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/bridge/br_device.c 2019-02-15 14:29:45.130668692 +0100 @@ -199,6 +199,7 @@ return -EINVAL; dev->mtu = new_mtu; + br->forced_mtu = new_mtu; #if IS_ENABLED(CONFIG_BRIDGE_NETFILTER) /* remember the MTU in the rtable for PMTU */ diff -ruw linux-4.14.127/net/bridge/br_fdb.c linux-4.14.127-fbx/net/bridge/br_fdb.c --- linux-4.14.127/net/bridge/br_fdb.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/bridge/br_fdb.c 2019-02-15 14:29:45.130668692 +0100 @@ -545,6 +545,20 @@ return ret; } +bool br_fdb_update_only(struct net_bridge *br, + struct net_bridge_port *source, + const unsigned char *addr) +{ + struct net_bridge_fdb_entry *fdb; + + fdb = br_fdb_find_rcu(br, addr, 0); + if (!fdb) + return false; + + fdb->updated = jiffies; + return true; +} + void br_fdb_update(struct net_bridge *br, struct net_bridge_port *source, const unsigned char *addr, u16 vid, bool added_by_user) { diff -ruw linux-4.14.127/net/bridge/br_if.c linux-4.14.127-fbx/net/bridge/br_if.c --- linux-4.14.127/net/bridge/br_if.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/bridge/br_if.c 2019-07-22 10:44:48.302828821 +0200 @@ -426,12 +426,12 @@ int br_min_mtu(const struct net_bridge *br) { const struct net_bridge_port *p; - int mtu = 0; + int mtu = br->forced_mtu; ASSERT_RTNL(); if (list_empty(&br->port_list)) - mtu = ETH_DATA_LEN; + mtu = min(mtu, ETH_DATA_LEN); else { list_for_each_entry(p, &br->port_list, list) { if (!mtu || p->dev->mtu < mtu) diff -ruw linux-4.14.127/net/bridge/br_private.h linux-4.14.127-fbx/net/bridge/br_private.h --- linux-4.14.127/net/bridge/br_private.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/bridge/br_private.h 2019-02-15 14:29:45.134668708 +0100 @@ -396,6 +396,7 @@ #ifdef CONFIG_NET_SWITCHDEV int offload_fwd_mark; #endif + unsigned int forced_mtu; }; struct br_input_skb_cb { @@ -523,6 +524,9 @@ unsigned long off); int br_fdb_insert(struct net_bridge *br, struct net_bridge_port *source, const unsigned char *addr, u16 vid); +bool br_fdb_update_only(struct net_bridge *br, + struct net_bridge_port *source, + const unsigned char *addr); void br_fdb_update(struct net_bridge *br, struct net_bridge_port *source, const unsigned char *addr, u16 vid, bool added_by_user); diff -ruw linux-4.14.127/net/core/dev.c linux-4.14.127-fbx/net/core/dev.c --- linux-4.14.127/net/core/dev.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/core/dev.c 2019-07-22 10:44:48.306828838 +0200 @@ -145,6 +145,7 @@ #include #include #include +#include #include "net-sysfs.h" @@ -166,6 +167,10 @@ struct netdev_notifier_info *info); static struct napi_struct *napi_by_id(unsigned int napi_id); +#ifdef CONFIG_NETRXTHREAD +struct krxd gkrxd[CONFIG_NETRXTHREAD_RX_QUEUE]; +#endif + /* * The @dev_base_head list is protected by @dev_base_lock and the rtnl * semaphore. @@ -1186,8 +1191,6 @@ BUG_ON(!dev_net(dev)); net = dev_net(dev); - if (dev->flags & IFF_UP) - return -EBUSY; write_seqcount_begin(&devnet_rename_seq); @@ -4078,6 +4081,23 @@ return ret; } +/* Start Freebox added code */ +#if defined(CONFIG_FREEBOX_DIVERTER) || defined(CONFIG_FREEBOX_DIVERTER_MODULE) +int (*fbxdiverter_hook)(struct sk_buff *); + +static int handle_fbxdiverter(struct sk_buff *skb) +{ + /* try_module_get is missing here, so there is a race on + * fbxdiverter module deletion */ + if (!fbxdiverter_hook) + return 0; + return fbxdiverter_hook(skb); +} + +EXPORT_SYMBOL(fbxdiverter_hook); +#endif + + /** * netif_rx - post buffer to the network code * @skb: buffer to post @@ -4343,26 +4363,104 @@ return 0; } +static int __netif_receive_skb_core_end(struct sk_buff *skb, bool pfmemalloc); + static int __netif_receive_skb_core(struct sk_buff *skb, bool pfmemalloc) { - struct packet_type *ptype, *pt_prev; - rx_handler_func_t *rx_handler; - struct net_device *orig_dev; - bool deliver_exact = false; - int ret = NET_RX_DROP; - __be16 type; +#ifdef CONFIG_NETRXTHREAD + unsigned int len; + struct krxd *krxd; +#endif net_timestamp_check(!netdev_tstamp_prequeue, skb); trace_netif_receive_skb(skb); - orig_dev = skb->dev; - skb_reset_network_header(skb); if (!skb_transport_header_was_set(skb)) skb_reset_transport_header(skb); skb_reset_mac_len(skb); +#if defined(CONFIG_FREEBOX_DIVERTER) || defined(CONFIG_FREEBOX_DIVERTER_MODULE) + if (handle_fbxdiverter(skb)) + return NET_RX_SUCCESS; +#endif + +#ifndef CONFIG_NETRXTHREAD + return __netif_receive_skb_core_end(skb, pfmemalloc); +#else + + if (pfmemalloc) + return __netif_receive_skb_core_end(skb, pfmemalloc); + + BUILD_BUG_ON(ARRAY_SIZE(gkrxd) < 2); + krxd = &gkrxd[skb->rxthread_prio & 1]; + + /* queue the packet to the rx thread */ + local_bh_disable(); + len = skb_queue_len(&krxd->pkt_queue); + if (len < RXTHREAD_MAX_PKTS) { + __skb_queue_tail(&krxd->pkt_queue, skb); + krxd->stats_pkts++; + if (!len) + wake_up(&krxd->wq); + } else { + krxd->stats_dropped++; + dev_kfree_skb(skb); + } + local_bh_enable(); + return NET_RX_SUCCESS; +#endif +} + +#ifdef CONFIG_NETRXTHREAD +static int krxd_action(void *data) +{ + struct krxd *krxd = (struct krxd *)data; + unsigned int queue = krxd - gkrxd; + struct sk_buff *skb; + + set_user_nice(current, queue > 0 ? -10 : -5); + current->flags |= PF_NOFREEZE; + __set_current_state(TASK_RUNNING); + + local_bh_disable(); + while (1) { + skb = skb_dequeue(&krxd->pkt_queue); + if (!skb) { + local_bh_enable(); + wait_event_interruptible(krxd->wq, + skb_queue_len(&krxd->pkt_queue)); + set_current_state(TASK_RUNNING); + local_bh_disable(); + continue; + } + + rcu_read_lock(); + __netif_receive_skb_core_end(skb, false); + rcu_read_unlock(); + + /* only schedule when working on lowest prio queue */ + if (queue == 0 && need_resched()) { + local_bh_enable(); + schedule(); + local_bh_disable(); + } + } + return 0; +} +#endif + +static int __netif_receive_skb_core_end(struct sk_buff *skb, bool pfmemalloc) +{ + struct packet_type *ptype, *pt_prev; + rx_handler_func_t *rx_handler; + struct net_device *orig_dev; + bool deliver_exact = false; + int ret = NET_RX_DROP; + __be16 type; + + orig_dev = skb->dev; pt_prev = NULL; another_round: @@ -8806,6 +8904,24 @@ open_softirq(NET_TX_SOFTIRQ, net_tx_action); open_softirq(NET_RX_SOFTIRQ, net_rx_action); +#ifdef CONFIG_NETRXTHREAD + for (i = 0; i < CONFIG_NETRXTHREAD_RX_QUEUE; i++) { + struct krxd *krxd = &gkrxd[i]; + struct task_struct *task; + + skb_queue_head_init(&krxd->pkt_queue); + init_waitqueue_head(&krxd->wq); + task = kthread_create(krxd_action, krxd, "krxthread_%u", i); + if (IS_ERR(task)) { + printk(KERN_ERR "unable to create krxd\n"); + return -ENOMEM; + } + krxd->task = task; + wake_up_process(task); + } +#endif + + rc = cpuhp_setup_state_nocalls(CPUHP_NET_DEV_DEAD, "net/dev:dead", NULL, dev_cpu_dead); WARN_ON(rc < 0); diff -ruw linux-4.14.127/net/core/net-procfs.c linux-4.14.127-fbx/net/core/net-procfs.c --- linux-4.14.127/net/core/net-procfs.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/core/net-procfs.c 2019-02-15 14:29:45.162668820 +0100 @@ -313,6 +313,83 @@ .release = seq_release_net, }; +#ifdef CONFIG_NETRXTHREAD +/* + * This is invoked by the /proc filesystem handler to display a device + * in detail. + */ +static void *krxthread_seq_start(struct seq_file *seq, loff_t *pos) +{ + int *queue; + + if (*pos > CONFIG_NETRXTHREAD_RX_QUEUE) + return NULL; + + queue = kmalloc(sizeof(*queue), GFP_KERNEL); + if (!queue) + return NULL; + *queue = ((int)*pos - 1); + + return queue; +} + +static void *krxthread_seq_next(struct seq_file *seq, void *v, loff_t *pos) +{ + int *queue = v; + + if (*pos == CONFIG_NETRXTHREAD_RX_QUEUE) + return NULL; + + ++*queue; + *pos = *queue + 1; + return queue; +} + +static void krxthread_seq_stop(struct seq_file *seq, void *v) +{ + kfree(v); +} + +static void krxthread_seq_printf_stats(struct seq_file *seq, int queue) +{ + seq_printf(seq, "%8u %12u %12u\n", + queue, + gkrxd[queue].stats_pkts, + gkrxd[queue].stats_dropped); +} + +static int krxthread_seq_show(struct seq_file *seq, void *v) +{ + int *queue = v; + + if (*queue == -1) + seq_printf(seq, "%8s %12s %12s\n", + "queue", "packets", "drops"); + else + krxthread_seq_printf_stats(seq, *queue); + return 0; +} + +static const struct seq_operations krxthread_seq_ops = { + .start = krxthread_seq_start, + .next = krxthread_seq_next, + .stop = krxthread_seq_stop, + .show = krxthread_seq_show, +}; + +static int krxthread_seq_open(struct inode *inode, struct file *file) +{ + return seq_open(file, &krxthread_seq_ops); +} + +static const struct file_operations krxthread_seq_fops = { + .owner = THIS_MODULE, + .open = krxthread_seq_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; +#endif /* KRXTHREAD */ static int __net_init dev_proc_net_init(struct net *net) { @@ -328,6 +405,11 @@ if (wext_proc_init(net)) goto out_ptype; +#ifdef CONFIG_NETRXTHREAD + if (!proc_create("krxthread", S_IRUGO, net->proc_net, + &krxthread_seq_fops)) + goto out_ptype; +#endif rc = 0; out: return rc; diff -ruw linux-4.14.127/net/core/net-sysfs.c linux-4.14.127-fbx/net/core/net-sysfs.c --- linux-4.14.127/net/core/net-sysfs.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/core/net-sysfs.c 2019-05-10 11:02:37.880385363 +0200 @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -635,7 +636,24 @@ }; #if IS_ENABLED(CONFIG_WIRELESS_EXT) || IS_ENABLED(CONFIG_CFG80211) +static ssize_t show_nl80211_iftype(struct device *dev, + struct device_attribute *attr, char *buf) +{ + const struct net_device *netdev = to_net_dev(dev); + ssize_t ret = 0; + + if (!rtnl_trylock()) + return restart_syscall(); + if (netdev->ieee80211_ptr) + ret = sprintf(buf, "%d\n", netdev->ieee80211_ptr->iftype); + rtnl_unlock(); + + return ret; +} +static DEVICE_ATTR(nl80211_iftype, S_IRUGO, show_nl80211_iftype, NULL); + static struct attribute *wireless_attrs[] = { + &dev_attr_nl80211_iftype.attr, NULL }; diff -ruw linux-4.14.127/net/core/skbuff.c linux-4.14.127-fbx/net/core/skbuff.c --- linux-4.14.127/net/core/skbuff.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/core/skbuff.c 2019-05-10 11:02:37.884385380 +0200 @@ -813,6 +813,10 @@ memcpy(&new->headers_start, &old->headers_start, offsetof(struct sk_buff, headers_end) - offsetof(struct sk_buff, headers_start)); + +#ifdef CONFIG_IP_FFN + new->ffn_state = FFN_STATE_INIT; +#endif CHECK_SKB_FIELD(protocol); CHECK_SKB_FIELD(csum); CHECK_SKB_FIELD(hash); @@ -4886,6 +4890,7 @@ nf_reset(skb); nf_reset_trace(skb); + skb->mark = 0; #ifdef CONFIG_NET_SWITCHDEV skb->offload_fwd_mark = 0; #endif @@ -4895,7 +4900,6 @@ ipvs_reset(skb); skb_orphan(skb); - skb->mark = 0; } EXPORT_SYMBOL_GPL(skb_scrub_packet); diff -ruw linux-4.14.127/net/core/sock.c linux-4.14.127-fbx/net/core/sock.c --- linux-4.14.127/net/core/sock.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/core/sock.c 2019-05-10 11:02:37.888385395 +0200 @@ -1058,6 +1058,9 @@ ret = -EINVAL; else sock_valbool_flag(sk, SOCK_ZEROCOPY, valbool); + + case SO_UDP_DUP_UNICAST: + sock_valbool_flag(sk, SOCK_UDP_DUP_UNICAST, valbool); break; default: @@ -1386,6 +1389,9 @@ if (len < lv) return -EINVAL; v.val64 = sock_gen_cookie(sk); + + case SO_UDP_DUP_UNICAST: + v.val = sock_flag(sk, SOCK_UDP_DUP_UNICAST); break; case SO_ZEROCOPY: diff -ruw linux-4.14.127/net/ipv4/Makefile linux-4.14.127-fbx/net/ipv4/Makefile --- linux-4.14.127/net/ipv4/Makefile 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/ipv4/Makefile 2019-02-15 14:29:45.194668947 +0100 @@ -17,6 +17,8 @@ obj-$(CONFIG_NET_IP_TUNNEL) += ip_tunnel.o obj-$(CONFIG_SYSCTL) += sysctl_net_ipv4.o + +obj-$(CONFIG_IP_FFN) += ip_ffn.o obj-$(CONFIG_PROC_FS) += proc.o obj-$(CONFIG_IP_MULTIPLE_TABLES) += fib_rules.o obj-$(CONFIG_IP_MROUTE) += ipmr.o diff -ruw linux-4.14.127/net/ipv4/ip_input.c linux-4.14.127-fbx/net/ipv4/ip_input.c --- linux-4.14.127/net/ipv4/ip_input.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/ipv4/ip_input.c 2019-05-10 11:02:37.900385445 +0200 @@ -189,8 +189,13 @@ return false; } -static int ip_local_deliver_finish(struct net *net, struct sock *sk, struct sk_buff *skb) +int ip_local_deliver_finish(struct net *net, struct sock *sk, struct sk_buff *skb) { +#ifdef CONFIG_IP_FFN + if (skb->ffn_state == FFN_STATE_FORWARDABLE) + ip_ffn_add(skb, IP_FFN_LOCAL_IN); +#endif + __skb_pull(skb, skb_network_header_len(skb)); rcu_read_lock(); @@ -490,6 +495,11 @@ /* Must drop socket now because of tproxy. */ skb_orphan(skb); +#ifdef CONFIG_IP_FFN + if (!ip_ffn_process(skb)) + return NET_RX_SUCCESS; +#endif + return NF_HOOK(NFPROTO_IPV4, NF_INET_PRE_ROUTING, net, NULL, skb, dev, NULL, ip_rcv_finish); diff -ruw linux-4.14.127/net/ipv4/ip_output.c linux-4.14.127-fbx/net/ipv4/ip_output.c --- linux-4.14.127/net/ipv4/ip_output.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/ipv4/ip_output.c 2019-07-22 10:44:48.314828871 +0200 @@ -217,6 +217,11 @@ return res; } +#ifdef CONFIG_IP_FFN + if (skb->ffn_state == FFN_STATE_FORWARDABLE) + ip_ffn_add(skb, IP_FFN_FINISH_OUT); +#endif + rcu_read_lock_bh(); nexthop = (__force u32) rt_nexthop(rt, ip_hdr(skb)->daddr); neigh = __ipv4_neigh_lookup_noref(dev, nexthop); @@ -402,6 +407,11 @@ skb->dev = dev; skb->protocol = htons(ETH_P_IP); +#ifdef CONFIG_IP_FFN + if (skb->ffn_state == FFN_STATE_FAST_FORWARDED) + return ip_finish_output(net, sk, skb); +#endif + return NF_HOOK_COND(NFPROTO_IPV4, NF_INET_POST_ROUTING, net, sk, skb, NULL, dev, ip_finish_output, @@ -1593,4 +1603,7 @@ #if defined(CONFIG_IP_MULTICAST) igmp_mc_init(); #endif +#ifdef CONFIG_IP_FFN + ip_ffn_init(); +#endif } diff -ruw linux-4.14.127/net/ipv4/ip_tunnel_core.c linux-4.14.127-fbx/net/ipv4/ip_tunnel_core.c --- linux-4.14.127/net/ipv4/ip_tunnel_core.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/ipv4/ip_tunnel_core.c 2019-02-15 14:29:45.210669010 +0100 @@ -47,6 +47,9 @@ #include #include #include +#if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE) +#include +#endif const struct ip_tunnel_encap_ops __rcu * iptun_encaps[MAX_IPTUN_ENCAP_OPS] __read_mostly; @@ -69,6 +72,11 @@ skb_scrub_packet(skb, xnet); skb_clear_hash_if_not_l4(skb); +#if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE) + if (proto == IPPROTO_IPV6) + nf_ct_set(skb, NULL, IP_CT_UNTRACKED); +#endif + skb_dst_set(skb, &rt->dst); memset(IPCB(skb), 0, sizeof(*IPCB(skb))); diff -ruw linux-4.14.127/net/ipv4/ipconfig.c linux-4.14.127-fbx/net/ipv4/ipconfig.c --- linux-4.14.127/net/ipv4/ipconfig.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/ipv4/ipconfig.c 2019-02-15 14:29:45.210669010 +0100 @@ -191,16 +191,62 @@ static struct ic_device *ic_first_dev __initdata; /* List of open device */ static struct ic_device *ic_dev __initdata; /* Selected device */ -static bool __init ic_is_init_dev(struct net_device *dev) +static bool __init ic_is_init_dev(struct net_device *dev, bool partial) { + char *p = NULL; + bool ret; + if (dev->flags & IFF_LOOPBACK) return false; - return user_dev_name[0] ? !strcmp(dev->name, user_dev_name) : + + if (partial) { + p = strchr(user_dev_name, '.'); + if (p) + *p = 0; + } + + ret = false; + if (user_dev_name[0] ? !strcmp(dev->name, user_dev_name) : (!(dev->flags & IFF_LOOPBACK) && (dev->flags & (IFF_POINTOPOINT|IFF_BROADCAST)) && - strncmp(dev->name, "dummy", 5)); + strncmp(dev->name, "dummy", 5))) + ret = true; + if (p) + *p = '.'; + return ret; } +#ifdef CONFIG_VLAN_8021Q +int register_vlan_device(struct net_device *real_dev, u16 vlan_id); + +static void __init prepare_vlan(void) +{ + unsigned short oflags; + struct net_device *dev; + char *p; + u16 vid; + + if (!strchr(user_dev_name, '.')) + return; + + p = strchr(user_dev_name, '.'); + *p = 0; + vid = simple_strtoul(p + 1, NULL, 10); + dev = __dev_get_by_name(&init_net, user_dev_name); + if (!dev) + goto fail; + + oflags = dev->flags; + if (dev_change_flags(dev, oflags | IFF_UP) < 0) + goto fail; + + register_vlan_device(dev, vid); + +fail: + *p = '.'; +} +#endif + static int __init ic_open_devs(void) { struct ic_device *d, **last; @@ -219,8 +265,13 @@ pr_err("IP-Config: Failed to open %s\n", dev->name); } +#ifdef CONFIG_VLAN_8021Q + /* register vlan device if needed */ + prepare_vlan(); +#endif + for_each_netdev(&init_net, dev) { - if (ic_is_init_dev(dev)) { + if (ic_is_init_dev(dev, false)) { int able = 0; if (dev->mtu >= 364) able |= IC_BOOTP; @@ -269,10 +320,12 @@ int wait, elapsed; for_each_netdev(&init_net, dev) - if (ic_is_init_dev(dev) && netif_carrier_ok(dev)) + if (ic_is_init_dev(dev, false) && netif_carrier_ok(dev)) goto have_carrier; + rtnl_unlock(); msleep(1); + rtnl_lock(); if (time_before(jiffies, next_msg)) continue; @@ -719,8 +772,10 @@ e += len; } if (*vendor_class_identifier) { +#ifdef IPCONFIG_DEBUG pr_info("DHCP: sending class identifier \"%s\"\n", vendor_class_identifier); +#endif *e++ = 60; /* Class-identifier */ len = strlen(vendor_class_identifier); *e++ = len; @@ -1381,7 +1436,7 @@ rtnl_lock(); for_each_netdev(&init_net, dev) { - if (ic_is_init_dev(dev)) { + if (ic_is_init_dev(dev, true)) { found = 1; break; } diff -ruw linux-4.14.127/net/ipv4/netfilter/Kconfig linux-4.14.127-fbx/net/ipv4/netfilter/Kconfig --- linux-4.14.127/net/ipv4/netfilter/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/ipv4/netfilter/Kconfig 2019-02-15 14:29:45.210669010 +0100 @@ -5,6 +5,13 @@ menu "IP: Netfilter Configuration" depends on INET && NETFILTER +config IP_FFN + bool "IP: Fast forwarding and NAT" + +config IP_FFN_PROCFS + bool "IP: Fast forwarding and NAT /proc/net entries" + depends on IP_FFN + config NF_DEFRAG_IPV4 tristate default n diff -ruw linux-4.14.127/net/ipv4/netfilter/ip_tables.c linux-4.14.127-fbx/net/ipv4/netfilter/ip_tables.c --- linux-4.14.127/net/ipv4/netfilter/ip_tables.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/ipv4/netfilter/ip_tables.c 2019-02-15 14:29:45.214669026 +0100 @@ -1104,6 +1104,8 @@ return ret; } +extern void fbxbr_flush_cache(void); + static int do_replace(struct net *net, const void __user *user, unsigned int len) { @@ -1143,6 +1145,15 @@ tmp.num_counters, tmp.counters); if (ret) goto free_newinfo_untrans; + +#ifdef CONFIG_IP_FFN + ip_ffn_flush_all(); +#endif + +#ifdef CONFIG_FBXBRIDGE + fbxbr_flush_cache(); +#endif + return 0; free_newinfo_untrans: diff -ruw linux-4.14.127/net/ipv4/route.c linux-4.14.127-fbx/net/ipv4/route.c --- linux-4.14.127/net/ipv4/route.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/ipv4/route.c 2019-07-22 10:44:48.318828887 +0200 @@ -1470,7 +1470,7 @@ static DEFINE_PER_CPU_ALIGNED(struct uncached_list, rt_uncached_list); -static void rt_add_uncached_list(struct rtable *rt) +void rt_add_uncached_list(struct rtable *rt) { struct uncached_list *ul = raw_cpu_ptr(&rt_uncached_list); @@ -1481,14 +1481,8 @@ spin_unlock_bh(&ul->lock); } -static void ipv4_dst_destroy(struct dst_entry *dst) +void rt_del_uncached_list(struct rtable *rt) { - struct dst_metrics *p = (struct dst_metrics *)DST_METRICS_PTR(dst); - struct rtable *rt = (struct rtable *) dst; - - if (p != &dst_default_metrics && refcount_dec_and_test(&p->refcnt)) - kfree(p); - if (!list_empty(&rt->rt_uncached)) { struct uncached_list *ul = rt->rt_uncached_list; @@ -1498,6 +1492,17 @@ } } +static void ipv4_dst_destroy(struct dst_entry *dst) +{ + struct dst_metrics *p = (struct dst_metrics *)DST_METRICS_PTR(dst); + struct rtable *rt = (struct rtable *)dst; + + if (p != &dst_default_metrics && refcount_dec_and_test(&p->refcnt)) + kfree(p); + + rt_del_uncached_list(rt); +} + void rt_flush_dev(struct net_device *dev) { struct net *net = dev_net(dev); diff -ruw linux-4.14.127/net/ipv4/tcp.c linux-4.14.127-fbx/net/ipv4/tcp.c --- linux-4.14.127/net/ipv4/tcp.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/ipv4/tcp.c 2019-07-22 10:44:48.318828887 +0200 @@ -2577,6 +2577,13 @@ err = -EINVAL; break; + case TCP_LINEAR_RTO: + if (val < 0 || val > 1) + err = -EINVAL; + else + tp->linear_rto = val; + break; + case TCP_REPAIR: if (!tcp_can_repair_sock(sk)) err = -EPERM; @@ -3117,6 +3124,9 @@ case TCP_THIN_DUPACK: val = 0; break; + case TCP_LINEAR_RTO: + val = tp->linear_rto; + break; case TCP_REPAIR: val = tp->repair; diff -ruw linux-4.14.127/net/ipv4/tcp_timer.c linux-4.14.127-fbx/net/ipv4/tcp_timer.c --- linux-4.14.127/net/ipv4/tcp_timer.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/ipv4/tcp_timer.c 2019-07-22 10:44:48.322828904 +0200 @@ -537,6 +537,10 @@ icsk->icsk_retransmits <= TCP_THIN_LINEAR_RETRIES) { icsk->icsk_backoff = 0; icsk->icsk_rto = min(__tcp_set_rto(tp), TCP_RTO_MAX); + + } else if (sk->sk_state == TCP_ESTABLISHED && tp->linear_rto) { + icsk->icsk_backoff = 0; + icsk->icsk_rto = min(__tcp_set_rto(tp), TCP_RTO_MAX); } else { /* Use normal (exponential) backoff */ icsk->icsk_rto = min(icsk->icsk_rto << 1, TCP_RTO_MAX); diff -ruw linux-4.14.127/net/ipv4/udp.c linux-4.14.127-fbx/net/ipv4/udp.c --- linux-4.14.127/net/ipv4/udp.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/ipv4/udp.c 2019-02-15 14:29:45.242669137 +0100 @@ -323,6 +323,49 @@ inet_sk(sk)->inet_num = snum; udp_sk(sk)->udp_port_hash = snum; udp_sk(sk)->udp_portaddr_hash ^= snum; + + /* resolve udp reuse conflict */ + if (sk->sk_reuse) { + struct sock *sk2; + bool found; + + found = false; + sk_for_each(sk2, &hslot->head) { + if (!net_eq(sock_net(sk2), net) || + sk2 == sk || + (udp_sk(sk2)->udp_port_hash != snum)) + continue; + + if (sk2->sk_bound_dev_if && + sk->sk_bound_dev_if && + sk2->sk_bound_dev_if != sk->sk_bound_dev_if) + continue; + + if (!inet_rcv_saddr_equal(sk, sk2, true)) + continue; + + found = true; + break; + } + + sk_for_each(sk2, &hslot->head) { + if (!net_eq(sock_net(sk2), net) || + sk2 == sk || + (udp_sk(sk2)->udp_port_hash != snum)) + continue; + + if (sk2->sk_bound_dev_if && + sk->sk_bound_dev_if && + sk2->sk_bound_dev_if != sk->sk_bound_dev_if) + continue; + + if (!inet_rcv_saddr_equal(sk, sk2, true)) + continue; + + sk->sk_reuse_conflict = found; + } + } + if (sk_unhashed(sk)) { if (sk->sk_reuseport && udp_reuseport_add_sock(sk, hslot)) { @@ -2018,6 +2061,90 @@ return 0; } +/* + * Unicast goes to one listener and all sockets with dup flag + * + * Note: called only from the BH handler context. + * + * Note2: it is okay to use the udp_table.hash table only here + * and not udp_table.hash2 table as the sock is always hashed in + * both udp_table.hash and udp_table.hash2. This might impact + * performance if the sock hash bucket hosts more than 10 socks + * but has the benefit of keeping the code simplier. + * + * Note3: __udp_is_mcast_sock() does not have really anything to + * do with multicast, it used there to deliver the packet only to + * the sockets that are bound to the ip:port/interface the skbuff + * is targeted to. + */ +static int __udp4_lib_uc_conflict_deliver(struct net *net, struct sk_buff *skb, + struct udphdr *uh, + __be32 saddr, __be32 daddr, + struct udp_table *udptable, + int proto) +{ + struct sock *sk, *first = NULL; + unsigned short hnum = ntohs(uh->dest); + struct udp_hslot *hslot = udp_hashslot(udptable, net, hnum); + int dif = skb->dev->ifindex; + unsigned int offset = offsetof(typeof(*sk), sk_node); + struct hlist_node *node; + struct sk_buff *nskb; + int sdif = inet_sdif(skb); + bool found_non_dup; + + found_non_dup = false; + sk_for_each_entry_offset_rcu(sk, node, &hslot->head, offset) { + bool need_deliver; + + if (!__udp_is_mcast_sock(net, sk, uh->dest, daddr, + uh->source, saddr, dif, sdif, hnum)) + continue; + + if (sock_flag(sk, SOCK_UDP_DUP_UNICAST)) + need_deliver = true; + else { + if (!found_non_dup) + need_deliver = true; + else + need_deliver = false; + found_non_dup = true; + } + + if (!need_deliver) + continue; + + if (!first) { + first = sk; + continue; + } + nskb = skb_clone(skb, GFP_ATOMIC); + + if (unlikely(!nskb)) { + atomic_inc(&sk->sk_drops); + __UDP_INC_STATS(net, UDP_MIB_RCVBUFERRORS, + IS_UDPLITE(sk)); + __UDP_INC_STATS(net, UDP_MIB_INERRORS, + IS_UDPLITE(sk)); + continue; + } + + if (udp_queue_rcv_skb(sk, nskb) > 0) + consume_skb(nskb); + } + + if (first) { + if (udp_queue_rcv_skb(first, skb) > 0) + consume_skb(skb); + } else { + kfree_skb(skb); + __UDP_INC_STATS(net, UDP_MIB_IGNOREDMULTI, + proto == IPPROTO_UDPLITE); + } + + return 0; +} + /* Initialize UDP checksum. If exited with zero value (success), * CHECKSUM_UNNECESSARY means, that no more checks are required. * Otherwise, csum completion requires chacksumming packet body, @@ -2068,11 +2195,20 @@ /* wrapper for udp_queue_rcv_skb tacking care of csum conversion and * return code conversion for ip layer consumption */ -static int udp_unicast_rcv_skb(struct sock *sk, struct sk_buff *skb, +static int udp_unicast_rcv_skb(struct net *net, + struct udp_table *udptable, + int proto, + __be32 saddr, __be32 daddr, + struct sock *sk, struct sk_buff *skb, struct udphdr *uh) { int ret; + if (sk->sk_reuse_conflict) + return __udp4_lib_uc_conflict_deliver(net, skb, uh, + saddr, daddr, + udptable, proto); + if (inet_get_convert_csum(sk) && uh->check && !IS_UDPLITE(sk)) skb_checksum_try_convert(skb, IPPROTO_UDP, uh->check, inet_compute_pseudo); @@ -2133,7 +2269,8 @@ if (unlikely(sk->sk_rx_dst != dst)) udp_sk_rx_dst_set(sk, dst); - ret = udp_unicast_rcv_skb(sk, skb, uh); + ret = udp_unicast_rcv_skb(net, udptable, proto, saddr, daddr, + sk, skb, uh); sock_put(sk); return ret; } @@ -2144,7 +2281,8 @@ sk = __udp4_lib_lookup_skb(skb, uh->source, uh->dest, udptable); if (sk) - return udp_unicast_rcv_skb(sk, skb, uh); + return udp_unicast_rcv_skb(net, udptable, proto, saddr, daddr, + sk, skb, uh); if (!xfrm4_policy_check(NULL, XFRM_POLICY_IN, skb)) goto drop; diff -ruw linux-4.14.127/net/ipv4/xfrm4_policy.c linux-4.14.127-fbx/net/ipv4/xfrm4_policy.c --- linux-4.14.127/net/ipv4/xfrm4_policy.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/ipv4/xfrm4_policy.c 2019-07-22 10:44:48.322828904 +0200 @@ -103,6 +103,7 @@ xdst->u.rt.rt_mtu_locked = rt->rt_mtu_locked; xdst->u.rt.rt_table_id = rt->rt_table_id; INIT_LIST_HEAD(&xdst->u.rt.rt_uncached); + rt_add_uncached_list(&xdst->u.rt); return 0; } @@ -244,7 +245,8 @@ struct xfrm_dst *xdst = (struct xfrm_dst *)dst; dst_destroy_metrics_generic(dst); - + if (xdst->u.rt.rt_uncached_list) + rt_del_uncached_list(&xdst->u.rt); xfrm_dst_destroy(xdst); } diff -ruw linux-4.14.127/net/ipv6/Makefile linux-4.14.127-fbx/net/ipv6/Makefile --- linux-4.14.127/net/ipv6/Makefile 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/ipv6/Makefile 2019-02-15 14:29:45.246669153 +0100 @@ -15,6 +15,7 @@ ipv6-offload := ip6_offload.o tcpv6_offload.o exthdrs_offload.o ipv6-$(CONFIG_SYSCTL) = sysctl_net_ipv6.o +ipv6-$(CONFIG_IPV6_FFN) += ip6_ffn.o ipv6-$(CONFIG_IPV6_MROUTE) += ip6mr.o ipv6-$(CONFIG_XFRM) += xfrm6_policy.o xfrm6_state.o xfrm6_input.o \ diff -ruw linux-4.14.127/net/ipv6/addrconf.c linux-4.14.127-fbx/net/ipv6/addrconf.c --- linux-4.14.127/net/ipv6/addrconf.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/ipv6/addrconf.c 2019-05-10 11:02:37.920385526 +0200 @@ -2194,12 +2194,27 @@ return 0; } +static int addrconf_ifid_ppp(u8 *eui, struct net_device *dev) +{ + if (is_zero_ether_addr(dev->perm_addr)) + return -1; + + memcpy(eui, dev->perm_addr, 3); + memcpy(eui + 5, dev->perm_addr + 3, 3); + eui[3] = 0xFF; + eui[4] = 0xFE; + eui[0] ^= 2; + return 0; +} + static int ipv6_generate_eui64(u8 *eui, struct net_device *dev) { switch (dev->type) { case ARPHRD_ETHER: case ARPHRD_FDDI: return addrconf_ifid_eui48(eui, dev); + case ARPHRD_PPP: + return addrconf_ifid_ppp(eui, dev); case ARPHRD_ARCNET: return addrconf_ifid_arcnet(eui, dev); case ARPHRD_INFINIBAND: @@ -3213,6 +3228,7 @@ if ((dev->type != ARPHRD_ETHER) && (dev->type != ARPHRD_FDDI) && + (dev->type != ARPHRD_PPP) && (dev->type != ARPHRD_ARCNET) && (dev->type != ARPHRD_INFINIBAND) && (dev->type != ARPHRD_IEEE1394) && diff -ruw linux-4.14.127/net/ipv6/af_inet6.c linux-4.14.127-fbx/net/ipv6/af_inet6.c --- linux-4.14.127/net/ipv6/af_inet6.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/ipv6/af_inet6.c 2019-05-10 11:02:37.920385526 +0200 @@ -995,6 +995,10 @@ if (err) goto udpv6_fail; +#ifdef CONFIG_IPV6_FFN + ipv6_ffn_init(); +#endif + err = udplitev6_init(); if (err) goto udplitev6_fail; diff -ruw linux-4.14.127/net/ipv6/ip6_input.c linux-4.14.127-fbx/net/ipv6/ip6_input.c --- linux-4.14.127/net/ipv6/ip6_input.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/ipv6/ip6_input.c 2019-02-15 14:29:45.258669200 +0100 @@ -205,6 +205,11 @@ /* Must drop socket now because of tproxy. */ skb_orphan(skb); +#ifdef CONFIG_IPV6_FFN + if (!ipv6_ffn_process(skb)) + return NET_RX_SUCCESS; +#endif + return NF_HOOK(NFPROTO_IPV6, NF_INET_PRE_ROUTING, net, NULL, skb, dev, NULL, ip6_rcv_finish); @@ -219,9 +224,7 @@ /* * Deliver the packet to the host */ - - -static int ip6_input_finish(struct net *net, struct sock *sk, struct sk_buff *skb) +int ip6_input_finish(struct net *net, struct sock *sk, struct sk_buff *skb) { const struct inet6_protocol *ipprot; struct inet6_dev *idev; @@ -230,6 +233,11 @@ bool raw; bool have_final = false; +#ifdef CONFIG_IPV6_FFN + if (skb->ffn_state == FFN_STATE_FORWARDABLE) + ipv6_ffn_add(skb, IPV6_FFN_LOCAL_IN); +#endif + /* * Parse extension headers */ diff -ruw linux-4.14.127/net/ipv6/ip6_output.c linux-4.14.127-fbx/net/ipv6/ip6_output.c --- linux-4.14.127/net/ipv6/ip6_output.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/ipv6/ip6_output.c 2019-05-10 11:02:37.924385542 +0200 @@ -55,6 +55,7 @@ #include #include #include +#include #include #include #include @@ -110,6 +111,11 @@ return res; } +#ifdef CONFIG_IPV6_FFN + if (skb->ffn_state == FFN_STATE_FORWARDABLE) + ipv6_ffn_add(skb, IPV6_FFN_FINISH_OUT); +#endif + rcu_read_lock_bh(); nexthop = rt6_nexthop((struct rt6_info *)dst, &ipv6_hdr(skb)->daddr); neigh = __ipv6_neigh_lookup_noref(dst->dev, nexthop); @@ -168,6 +174,11 @@ return 0; } +#ifdef CONFIG_IP_FFN + if (skb->ffn_state == FFN_STATE_FAST_FORWARDED) + return ip6_finish_output(net, sk, skb); +#endif + return NF_HOOK_COND(NFPROTO_IPV6, NF_INET_POST_ROUTING, net, sk, skb, NULL, dev, ip6_finish_output, @@ -572,6 +583,8 @@ hdr->hop_limit--; + skb->priority = rt_tos2priority(ipv6_get_dsfield(hdr)); + return NF_HOOK(NFPROTO_IPV6, NF_INET_FORWARD, net, NULL, skb, skb->dev, dst->dev, ip6_forward_finish); diff -ruw linux-4.14.127/net/ipv6/ip6_tunnel.c linux-4.14.127-fbx/net/ipv6/ip6_tunnel.c --- linux-4.14.127/net/ipv6/ip6_tunnel.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/ipv6/ip6_tunnel.c 2019-05-10 11:02:37.928385558 +0200 @@ -16,6 +16,8 @@ * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. * + * Changes: + * Steven Barth : MAP-E FMR support */ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt @@ -72,9 +74,9 @@ module_param(log_ecn_error, bool, 0644); MODULE_PARM_DESC(log_ecn_error, "Log packets received with corrupted ECN"); -static u32 HASH(const struct in6_addr *addr1, const struct in6_addr *addr2) +static u32 HASH(const struct in6_addr *addr) { - u32 hash = ipv6_addr_hash(addr1) ^ ipv6_addr_hash(addr2); + u32 hash = ipv6_addr_hash(addr); return hash_32(hash, IP6_TUNNEL_HASH_SIZE_SHIFT); } @@ -141,20 +143,29 @@ static struct ip6_tnl * ip6_tnl_lookup(struct net *net, const struct in6_addr *remote, const struct in6_addr *local) { - unsigned int hash = HASH(remote, local); + unsigned int hash = HASH(local); struct ip6_tnl *t; struct ip6_tnl_net *ip6n = net_generic(net, ip6_tnl_net_id); struct in6_addr any; + struct __ip6_tnl_fmr *fmr; for_each_ip6_tunnel_rcu(ip6n->tnls_r_l[hash]) { - if (ipv6_addr_equal(local, &t->parms.laddr) && - ipv6_addr_equal(remote, &t->parms.raddr) && - (t->dev->flags & IFF_UP)) + if (!ipv6_addr_equal(local, &t->parms.laddr) || + !(t->dev->flags & IFF_UP)) + continue; + + if (ipv6_addr_equal(remote, &t->parms.raddr)) + return t; + + for (fmr = t->parms.fmrs; fmr; fmr = fmr->next) { + if (ipv6_prefix_equal(remote, &fmr->ip6_prefix, + fmr->ip6_prefix_len)) return t; } + } memset(&any, 0, sizeof(any)); - hash = HASH(&any, local); + hash = HASH(local); for_each_ip6_tunnel_rcu(ip6n->tnls_r_l[hash]) { if (ipv6_addr_equal(local, &t->parms.laddr) && ipv6_addr_any(&t->parms.raddr) && @@ -162,7 +173,7 @@ return t; } - hash = HASH(remote, &any); + hash = HASH(&any); for_each_ip6_tunnel_rcu(ip6n->tnls_r_l[hash]) { if (ipv6_addr_equal(remote, &t->parms.raddr) && ipv6_addr_any(&t->parms.laddr) && @@ -202,7 +213,7 @@ if (!ipv6_addr_any(remote) || !ipv6_addr_any(local)) { prio = 1; - h = HASH(remote, local); + h = HASH(local); } return &ip6n->tnls[prio][h]; } @@ -383,6 +394,12 @@ struct net *net = t->net; struct ip6_tnl_net *ip6n = net_generic(net, ip6_tnl_net_id); + while (t->parms.fmrs) { + struct __ip6_tnl_fmr *next = t->parms.fmrs->next; + kfree(t->parms.fmrs); + t->parms.fmrs = next; + } + if (dev == ip6n->fb_tnl_dev) RCU_INIT_POINTER(ip6n->tnls_wc[0], NULL); else @@ -779,6 +796,107 @@ } EXPORT_SYMBOL_GPL(ip6_tnl_rcv_ctl); +/** + * ip4ip6_fmr_calc - calculate target / source IPv6-address based on FMR + * @dest: destination IPv6 address buffer + * @skb: received socket buffer + * @fmr: MAP FMR + * @xmit: Calculate for xmit or rcv + **/ +static void ip4ip6_fmr_calc(struct in6_addr *dest, + const struct iphdr *iph, const uint8_t *end, + const struct __ip6_tnl_fmr *fmr, bool xmit) +{ + int psidlen = fmr->ea_len - (32 - fmr->ip4_prefix_len); + u8 *portp = NULL; + bool use_dest_addr; + const struct iphdr *dsth = iph; + + if ((u8*)dsth >= end) + return; + + /* find significant IP header */ + if (iph->protocol == IPPROTO_ICMP) { + struct icmphdr *ih = (struct icmphdr*)(((u8*)dsth) + dsth->ihl * 4); + if (ih && ((u8*)&ih[1]) <= end && ( + ih->type == ICMP_DEST_UNREACH || + ih->type == ICMP_SOURCE_QUENCH || + ih->type == ICMP_TIME_EXCEEDED || + ih->type == ICMP_PARAMETERPROB || + ih->type == ICMP_REDIRECT)) + dsth = (const struct iphdr*)&ih[1]; + } + + /* in xmit-path use dest port by default and source port only if + this is an ICMP reply to something else; vice versa in rcv-path */ + use_dest_addr = (xmit && dsth == iph) || (!xmit && dsth != iph); + + /* get dst port */ + if (((u8*)&dsth[1]) <= end && ( + dsth->protocol == IPPROTO_UDP || + dsth->protocol == IPPROTO_TCP || + dsth->protocol == IPPROTO_SCTP || + dsth->protocol == IPPROTO_DCCP)) { + /* for UDP, TCP, SCTP and DCCP source and dest port + follow IPv4 header directly */ + portp = ((u8*)dsth) + dsth->ihl * 4; + + if (use_dest_addr) + portp += sizeof(u16); + } else if (iph->protocol == IPPROTO_ICMP) { + struct icmphdr *ih = (struct icmphdr*)(((u8*)dsth) + dsth->ihl * 4); + + /* use icmp identifier as port */ + if (((u8*)&ih) <= end && ( + (use_dest_addr && ( + ih->type == ICMP_ECHOREPLY || + ih->type == ICMP_TIMESTAMPREPLY || + ih->type == ICMP_INFO_REPLY || + ih->type == ICMP_ADDRESSREPLY)) || + (!use_dest_addr && ( + ih->type == ICMP_ECHO || + ih->type == ICMP_TIMESTAMP || + ih->type == ICMP_INFO_REQUEST || + ih->type == ICMP_ADDRESS) + ))) + portp = (u8*)&ih->un.echo.id; + } + + if ((portp && &portp[2] <= end) || psidlen == 0) { + int frombyte = fmr->ip6_prefix_len / 8; + int fromrem = fmr->ip6_prefix_len % 8; + int bytes = sizeof(struct in6_addr) - frombyte; + const u32 *addr = (use_dest_addr) ? &iph->daddr : &iph->saddr; + u64 eabits = ((u64)ntohl(*addr)) << (32 + fmr->ip4_prefix_len); + u64 t = 0; + + /* extract PSID from port and add it to eabits */ + u16 psidbits = 0; + if (psidlen > 0) { + psidbits = ((u16)portp[0]) << 8 | ((u16)portp[1]); + psidbits >>= 16 - psidlen - fmr->offset; + psidbits = (u16)(psidbits << (16 - psidlen)); + eabits |= ((u64)psidbits) << (48 - (fmr->ea_len - psidlen)); + } + + /* rewrite destination address */ + *dest = fmr->ip6_prefix; + memcpy(&dest->s6_addr[10], addr, sizeof(*addr)); + dest->s6_addr16[7] = htons(psidbits >> (16 - psidlen)); + + if (bytes > sizeof(u64)) + bytes = sizeof(u64); + + /* insert eabits */ + memcpy(&t, &dest->s6_addr[frombyte], bytes); + t = be64_to_cpu(t) & ~(((((u64)1) << fmr->ea_len) - 1) + << (64 - fmr->ea_len - fromrem)); + t = cpu_to_be64(t | (eabits >> fromrem)); + memcpy(&dest->s6_addr[frombyte], &t, bytes); + } +} + + static int __ip6_tnl_rcv(struct ip6_tnl *tunnel, struct sk_buff *skb, const struct tnl_ptk_info *tpi, struct metadata_dst *tun_dst, @@ -831,6 +949,27 @@ skb_reset_network_header(skb); memset(skb->cb, 0, sizeof(struct inet6_skb_parm)); + if (tpi->proto == htons(ETH_P_IP) && + !ipv6_addr_equal(&ipv6h->saddr, &tunnel->parms.raddr)) { + /* Packet didn't come from BR, so lookup FMR */ + struct __ip6_tnl_fmr *fmr; + struct in6_addr expected = tunnel->parms.raddr; + for (fmr = tunnel->parms.fmrs; fmr; fmr = fmr->next) + if (ipv6_prefix_equal(&ipv6h->saddr, + &fmr->ip6_prefix, fmr->ip6_prefix_len)) + break; + + /* Check that IPv6 matches IPv4 source to prevent spoofing */ + if (fmr) + ip4ip6_fmr_calc(&expected, ip_hdr(skb), + skb_tail_pointer(skb), fmr, false); + + if (!ipv6_addr_equal(&ipv6h->saddr, &expected)) { + rcu_read_unlock(); + goto drop; + } + } + __skb_tunnel_rx(skb, tunnel->dev, tunnel->net); err = dscp_ecn_decapsulate(tunnel, ipv6h, skb); @@ -963,6 +1102,7 @@ opt->ops.opt_nflen = 8; } + /** * ip6_tnl_addr_conflict - compare packet addresses to tunnel's own * @t: the outgoing tunnel device @@ -1231,6 +1371,7 @@ struct ip6_tnl *t = netdev_priv(dev); const struct iphdr *iph; int encap_limit = -1; + struct __ip6_tnl_fmr *fmr; struct flowi6 fl6; __u8 dsfield; __u32 mtu; @@ -1281,6 +1422,18 @@ fl6.flowi6_uid = sock_net_uid(dev_net(dev), NULL); + /* try to find matching FMR */ + for (fmr = t->parms.fmrs; fmr; fmr = fmr->next) { + unsigned mshift = 32 - fmr->ip4_prefix_len; + if (ntohl(fmr->ip4_prefix.s_addr) >> mshift == + ntohl(ip_hdr(skb)->daddr) >> mshift) + break; + } + + /* change dstaddr according to FMR */ + if (fmr) + ip4ip6_fmr_calc(&fl6.daddr, ip_hdr(skb), skb_tail_pointer(skb), fmr, true); + if (iptunnel_handle_offloads(skb, SKB_GSO_IPXIP6)) return -1; @@ -1500,6 +1653,14 @@ t->parms.link = p->link; t->parms.proto = p->proto; t->parms.fwmark = p->fwmark; + + while (t->parms.fmrs) { + struct __ip6_tnl_fmr *next = t->parms.fmrs->next; + kfree(t->parms.fmrs); + t->parms.fmrs = next; + } + t->parms.fmrs = p->fmrs; + dst_cache_reset(&t->dst_cache); ip6_tnl_link_config(t); return 0; @@ -1538,6 +1699,7 @@ p->flowinfo = u->flowinfo; p->link = u->link; p->proto = u->proto; + p->fmrs = NULL; memcpy(p->name, u->name, sizeof(u->name)); } @@ -1924,6 +2086,15 @@ return 0; } +static const struct nla_policy ip6_tnl_fmr_policy[IFLA_IPTUN_FMR_MAX + 1] = { + [IFLA_IPTUN_FMR_IP6_PREFIX] = { .len = sizeof(struct in6_addr) }, + [IFLA_IPTUN_FMR_IP4_PREFIX] = { .len = sizeof(struct in_addr) }, + [IFLA_IPTUN_FMR_IP6_PREFIX_LEN] = { .type = NLA_U8 }, + [IFLA_IPTUN_FMR_IP4_PREFIX_LEN] = { .type = NLA_U8 }, + [IFLA_IPTUN_FMR_EA_LEN] = { .type = NLA_U8 }, + [IFLA_IPTUN_FMR_OFFSET] = { .type = NLA_U8 } +}; + static void ip6_tnl_netlink_parms(struct nlattr *data[], struct __ip6_tnl_parm *parms) { @@ -1961,6 +2132,46 @@ if (data[IFLA_IPTUN_FWMARK]) parms->fwmark = nla_get_u32(data[IFLA_IPTUN_FWMARK]); + + if (data[IFLA_IPTUN_FMRS]) { + unsigned rem; + struct nlattr *fmr; + nla_for_each_nested(fmr, data[IFLA_IPTUN_FMRS], rem) { + struct nlattr *fmrd[IFLA_IPTUN_FMR_MAX + 1], *c; + struct __ip6_tnl_fmr *nfmr; + + nla_parse_nested(fmrd, IFLA_IPTUN_FMR_MAX, + fmr, ip6_tnl_fmr_policy, NULL); + + if (!(nfmr = kzalloc(sizeof(*nfmr), GFP_KERNEL))) + continue; + + nfmr->offset = 6; + + if ((c = fmrd[IFLA_IPTUN_FMR_IP6_PREFIX])) + nla_memcpy(&nfmr->ip6_prefix, fmrd[IFLA_IPTUN_FMR_IP6_PREFIX], + sizeof(nfmr->ip6_prefix)); + + if ((c = fmrd[IFLA_IPTUN_FMR_IP4_PREFIX])) + nla_memcpy(&nfmr->ip4_prefix, fmrd[IFLA_IPTUN_FMR_IP4_PREFIX], + sizeof(nfmr->ip4_prefix)); + + if ((c = fmrd[IFLA_IPTUN_FMR_IP6_PREFIX_LEN])) + nfmr->ip6_prefix_len = nla_get_u8(c); + + if ((c = fmrd[IFLA_IPTUN_FMR_IP4_PREFIX_LEN])) + nfmr->ip4_prefix_len = nla_get_u8(c); + + if ((c = fmrd[IFLA_IPTUN_FMR_EA_LEN])) + nfmr->ea_len = nla_get_u8(c); + + if ((c = fmrd[IFLA_IPTUN_FMR_OFFSET])) + nfmr->offset = nla_get_u8(c); + + nfmr->next = parms->fmrs; + parms->fmrs = nfmr; + } + } } static bool ip6_tnl_netlink_encap_parms(struct nlattr *data[], @@ -2076,6 +2287,12 @@ static size_t ip6_tnl_get_size(const struct net_device *dev) { + const struct ip6_tnl *t = netdev_priv(dev); + struct __ip6_tnl_fmr *c; + int fmrs = 0; + for (c = t->parms.fmrs; c; c = c->next) + ++fmrs; + return /* IFLA_IPTUN_LINK */ nla_total_size(4) + @@ -2105,6 +2322,24 @@ nla_total_size(0) + /* IFLA_IPTUN_FWMARK */ nla_total_size(4) + + /* IFLA_IPTUN_FMRS */ + nla_total_size(0) + + ( + /* nest */ + nla_total_size(0) + + /* IFLA_IPTUN_FMR_IP6_PREFIX */ + nla_total_size(sizeof(struct in6_addr)) + + /* IFLA_IPTUN_FMR_IP4_PREFIX */ + nla_total_size(sizeof(struct in_addr)) + + /* IFLA_IPTUN_FMR_EA_LEN */ + nla_total_size(1) + + /* IFLA_IPTUN_FMR_IP6_PREFIX_LEN */ + nla_total_size(1) + + /* IFLA_IPTUN_FMR_IP4_PREFIX_LEN */ + nla_total_size(1) + + /* IFLA_IPTUN_FMR_OFFSET */ + nla_total_size(1) + ) * fmrs + 0; } @@ -2112,6 +2347,9 @@ { struct ip6_tnl *tunnel = netdev_priv(dev); struct __ip6_tnl_parm *parm = &tunnel->parms; + struct __ip6_tnl_fmr *c; + int fmrcnt = 0; + struct nlattr *fmrs; if (nla_put_u32(skb, IFLA_IPTUN_LINK, parm->link) || nla_put_in6_addr(skb, IFLA_IPTUN_LOCAL, &parm->laddr) || @@ -2121,9 +2359,27 @@ nla_put_be32(skb, IFLA_IPTUN_FLOWINFO, parm->flowinfo) || nla_put_u32(skb, IFLA_IPTUN_FLAGS, parm->flags) || nla_put_u8(skb, IFLA_IPTUN_PROTO, parm->proto) || - nla_put_u32(skb, IFLA_IPTUN_FWMARK, parm->fwmark)) + nla_put_u32(skb, IFLA_IPTUN_FWMARK, parm->fwmark) || + !(fmrs = nla_nest_start(skb, IFLA_IPTUN_FMRS))) goto nla_put_failure; + for (c = parm->fmrs; c; c = c->next) { + struct nlattr *fmr = nla_nest_start(skb, ++fmrcnt); + if (!fmr || + nla_put(skb, IFLA_IPTUN_FMR_IP6_PREFIX, + sizeof(c->ip6_prefix), &c->ip6_prefix) || + nla_put(skb, IFLA_IPTUN_FMR_IP4_PREFIX, + sizeof(c->ip4_prefix), &c->ip4_prefix) || + nla_put_u8(skb, IFLA_IPTUN_FMR_IP6_PREFIX_LEN, c->ip6_prefix_len) || + nla_put_u8(skb, IFLA_IPTUN_FMR_IP4_PREFIX_LEN, c->ip4_prefix_len) || + nla_put_u8(skb, IFLA_IPTUN_FMR_EA_LEN, c->ea_len) || + nla_put_u8(skb, IFLA_IPTUN_FMR_OFFSET, c->offset)) + goto nla_put_failure; + + nla_nest_end(skb, fmr); + } + nla_nest_end(skb, fmrs); + if (nla_put_u16(skb, IFLA_IPTUN_ENCAP_TYPE, tunnel->encap.type) || nla_put_be16(skb, IFLA_IPTUN_ENCAP_SPORT, tunnel->encap.sport) || nla_put_be16(skb, IFLA_IPTUN_ENCAP_DPORT, tunnel->encap.dport) || @@ -2163,6 +2419,7 @@ [IFLA_IPTUN_ENCAP_DPORT] = { .type = NLA_U16 }, [IFLA_IPTUN_COLLECT_METADATA] = { .type = NLA_FLAG }, [IFLA_IPTUN_FWMARK] = { .type = NLA_U32 }, + [IFLA_IPTUN_FMRS] = { .type = NLA_NESTED }, }; static struct rtnl_link_ops ip6_link_ops __read_mostly = { diff -ruw linux-4.14.127/net/ipv6/netfilter/Kconfig linux-4.14.127-fbx/net/ipv6/netfilter/Kconfig --- linux-4.14.127/net/ipv6/netfilter/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/ipv6/netfilter/Kconfig 2019-02-15 14:29:45.262669216 +0100 @@ -5,6 +5,13 @@ menu "IPv6: Netfilter Configuration" depends on INET && IPV6 && NETFILTER +config IPV6_FFN + bool "IPv6: Fast forwarding and NAT" + +config IPV6_FFN_PROCFS + bool "IPv6: Fast forwarding and NAT /proc/net entries" + depends on IPV6_FFN + config NF_DEFRAG_IPV6 tristate default n diff -ruw linux-4.14.127/net/ipv6/netfilter/nf_nat_l3proto_ipv6.c linux-4.14.127-fbx/net/ipv6/netfilter/nf_nat_l3proto_ipv6.c --- linux-4.14.127/net/ipv6/netfilter/nf_nat_l3proto_ipv6.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/ipv6/netfilter/nf_nat_l3proto_ipv6.c 2019-02-15 14:29:45.270669248 +0100 @@ -81,6 +81,8 @@ enum nf_nat_manip_type maniptype) { struct ipv6hdr *ipv6h; + const __be32 *to; + __be32 *from; __be16 frag_off; int hdroff; u8 nexthdr; @@ -104,11 +106,24 @@ ipv6h = (void *)skb->data + iphdroff; manip_addr: - if (maniptype == NF_NAT_MANIP_SRC) - ipv6h->saddr = target->src.u3.in6; - else - ipv6h->daddr = target->dst.u3.in6; + if (maniptype == NF_NAT_MANIP_SRC) { + from = ipv6h->saddr.s6_addr32; + to = target->src.u3.in6.s6_addr32; + } else { + from = ipv6h->daddr.s6_addr32; + to = target->dst.u3.in6.s6_addr32; + } + + if (skb->ip_summed == CHECKSUM_COMPLETE) { + __be32 diff[] = { + ~from[0], ~from[1], ~from[2], ~from[3], + to[0], to[1], to[2], to[3], + }; + + skb->csum = ~csum_partial(diff, sizeof(diff), ~skb->csum); + } + memcpy(from, to, sizeof (struct in6_addr)); return true; } diff -ruw linux-4.14.127/net/ipv6/route.c linux-4.14.127-fbx/net/ipv6/route.c --- linux-4.14.127/net/ipv6/route.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/ipv6/route.c 2019-05-10 11:02:37.928385558 +0200 @@ -124,7 +124,7 @@ static DEFINE_PER_CPU_ALIGNED(struct uncached_list, rt6_uncached_list); -static void rt6_uncached_list_add(struct rt6_info *rt) +void rt6_uncached_list_add(struct rt6_info *rt) { struct uncached_list *ul = raw_cpu_ptr(&rt6_uncached_list); @@ -135,7 +135,7 @@ spin_unlock_bh(&ul->lock); } -static void rt6_uncached_list_del(struct rt6_info *rt) +void rt6_uncached_list_del(struct rt6_info *rt) { if (!list_empty(&rt->rt6i_uncached)) { struct uncached_list *ul = rt->rt6i_uncached_list; diff -ruw linux-4.14.127/net/ipv6/udp.c linux-4.14.127-fbx/net/ipv6/udp.c --- linux-4.14.127/net/ipv6/udp.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/ipv6/udp.c 2019-02-15 14:29:45.278669279 +0100 @@ -704,6 +704,81 @@ * Note: called only from the BH handler context, * so we don't need to lock the hashes. */ +static int __udp6_lib_uc_conflict_deliver(struct net *net, struct sk_buff *skb, + const struct in6_addr *saddr, const struct in6_addr *daddr, + struct udp_table *udptable, int proto) +{ + struct sock *sk, *first = NULL; + const struct udphdr *uh = udp_hdr(skb); + unsigned short hnum = ntohs(uh->dest); + struct udp_hslot *hslot = udp_hashslot(udptable, net, hnum); + unsigned int offset = offsetof(typeof(*sk), sk_node); + int dif = inet6_iif(skb); + struct hlist_node *node; + struct sk_buff *nskb; + bool found_non_dup; + + found_non_dup = false; + sk_for_each_entry_offset_rcu(sk, node, &hslot->head, offset) { + bool need_deliver; + + if (!__udp_v6_is_mcast_sock(net, sk, uh->dest, daddr, + uh->source, saddr, dif, hnum)) + + continue; + + /* If zero checksum and no_check is not on for + * the socket then skip it. + */ + if (!uh->check && !udp_sk(sk)->no_check6_rx) + continue; + + if (sock_flag(sk, SOCK_UDP_DUP_UNICAST)) + need_deliver = true; + else { + if (!found_non_dup) + need_deliver = true; + else + need_deliver = false; + found_non_dup = true; + } + + if (!need_deliver) + continue; + + if (!first) { + first = sk; + continue; + } + nskb = skb_clone(skb, GFP_ATOMIC); + if (unlikely(!nskb)) { + atomic_inc(&sk->sk_drops); + __UDP6_INC_STATS(net, UDP_MIB_RCVBUFERRORS, + IS_UDPLITE(sk)); + __UDP6_INC_STATS(net, UDP_MIB_INERRORS, + IS_UDPLITE(sk)); + continue; + } + + if (udpv6_queue_rcv_skb(sk, nskb) > 0) + consume_skb(nskb); + } + + if (first) { + if (udpv6_queue_rcv_skb(first, skb) > 0) + consume_skb(skb); + } else { + kfree_skb(skb); + __UDP6_INC_STATS(net, UDP_MIB_IGNOREDMULTI, + proto == IPPROTO_UDPLITE); + } + return 0; +} + +/* + * Note: called only from the BH handler context, + * so we don't need to lock the hashes. + */ static int __udp6_lib_mcast_deliver(struct net *net, struct sk_buff *skb, const struct in6_addr *saddr, const struct in6_addr *daddr, struct udp_table *udptable, int proto) @@ -783,7 +858,12 @@ /* wrapper for udp_queue_rcv_skb tacking care of csum conversion and * return code conversion for ip layer consumption */ -static int udp6_unicast_rcv_skb(struct sock *sk, struct sk_buff *skb, +static int udp6_unicast_rcv_skb(struct net *net, + struct udp_table *udptable, + int proto, + const struct in6_addr *saddr, + const struct in6_addr *daddr, + struct sock *sk, struct sk_buff *skb, struct udphdr *uh) { int ret; @@ -792,6 +872,12 @@ skb_checksum_try_convert(skb, IPPROTO_UDP, uh->check, ip6_compute_pseudo); + if (sk->sk_reuse_conflict) + return __udp6_lib_uc_conflict_deliver(net, skb, + saddr, daddr, + udptable, + proto); + ret = udpv6_queue_rcv_skb(sk, skb); /* a return value > 0 means to resubmit the input */ @@ -856,7 +942,8 @@ goto report_csum_error; } - ret = udp6_unicast_rcv_skb(sk, skb, uh); + ret = udp6_unicast_rcv_skb(net, udptable, proto, + saddr, daddr, sk, skb, uh); sock_put(sk); return ret; } @@ -873,7 +960,8 @@ if (sk) { if (!uh->check && !udp_sk(sk)->no_check6_rx) goto report_csum_error; - return udp6_unicast_rcv_skb(sk, skb, uh); + return udp6_unicast_rcv_skb(net, udptable, proto, + saddr, daddr, sk, skb, uh); } if (!uh->check) diff -ruw linux-4.14.127/net/ipv6/xfrm6_policy.c linux-4.14.127-fbx/net/ipv6/xfrm6_policy.c --- linux-4.14.127/net/ipv6/xfrm6_policy.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/ipv6/xfrm6_policy.c 2019-05-10 11:02:37.932385575 +0200 @@ -113,6 +113,8 @@ xdst->u.rt6.rt6i_gateway = rt->rt6i_gateway; xdst->u.rt6.rt6i_dst = rt->rt6i_dst; xdst->u.rt6.rt6i_src = rt->rt6i_src; + INIT_LIST_HEAD(&xdst->u.rt6.rt6i_uncached); + rt6_uncached_list_add(&xdst->u.rt6); return 0; } @@ -243,6 +245,8 @@ if (likely(xdst->u.rt6.rt6i_idev)) in6_dev_put(xdst->u.rt6.rt6i_idev); dst_destroy_metrics_generic(dst); + if (xdst->u.rt6.rt6i_uncached_list) + rt6_uncached_list_del(&xdst->u.rt6); xfrm_dst_destroy(xdst); } diff -ruw linux-4.14.127/net/mac80211/driver-ops.c linux-4.14.127-fbx/net/mac80211/driver-ops.c --- linux-4.14.127/net/mac80211/driver-ops.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/mac80211/driver-ops.c 2019-02-15 14:29:45.298669359 +0100 @@ -52,6 +52,30 @@ local->started = false; } +int drv_get_powered(struct ieee80211_local *local, bool *up, bool *busy) +{ + int ret = -EOPNOTSUPP; + + might_sleep(); + + if (local->ops->get_powered) + ret = local->ops->get_powered(&local->hw, up, busy); + + return ret; +} + +int drv_set_powered(struct ieee80211_local *local) +{ + int ret = -EOPNOTSUPP; + + might_sleep(); + + if (local->ops->set_powered) + ret = local->ops->set_powered(&local->hw); + + return ret; +} + int drv_add_interface(struct ieee80211_local *local, struct ieee80211_sub_if_data *sdata) { diff -ruw linux-4.14.127/net/mac80211/driver-ops.h linux-4.14.127-fbx/net/mac80211/driver-ops.h --- linux-4.14.127/net/mac80211/driver-ops.h 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/mac80211/driver-ops.h 2019-07-22 10:44:48.326828920 +0200 @@ -84,6 +84,8 @@ int drv_start(struct ieee80211_local *local); void drv_stop(struct ieee80211_local *local); +int drv_get_powered(struct ieee80211_local *local, bool *up, bool *busy); +int drv_set_powered(struct ieee80211_local *local); #ifdef CONFIG_PM static inline int drv_suspend(struct ieee80211_local *local, diff -ruw linux-4.14.127/net/mac80211/ethtool.c linux-4.14.127-fbx/net/mac80211/ethtool.c --- linux-4.14.127/net/mac80211/ethtool.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/mac80211/ethtool.c 2019-02-15 14:29:45.298669359 +0100 @@ -46,6 +46,22 @@ }; #define STA_STATS_LEN ARRAY_SIZE(ieee80211_gstrings_sta_stats) +struct ethtool_priv_flags_strings { + const char string[ETH_GSTRING_LEN]; +}; + +enum { + POWERED_SUPPORTED = (1 << 0), + POWERED_STATUS = (1 << 1), + POWERED_CHANGE_BUSY = (1 << 2), +}; + +static const struct ethtool_priv_flags_strings ieee80211_pflags_strings[] = { + { .string = "powered-supported" }, + { .string = "powered-status" }, + { .string = "powered-change-busy", }, +}; + static int ieee80211_get_sset_count(struct net_device *dev, int sset) { struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); @@ -56,6 +72,9 @@ rv += drv_get_et_sset_count(sdata, sset); + if (sset == ETH_SS_PRIV_FLAGS) + rv += ARRAY_SIZE(ieee80211_pflags_strings); + if (rv == 0) return -EOPNOTSUPP; return rv; @@ -212,6 +231,9 @@ memcpy(data, ieee80211_gstrings_sta_stats, sz_sta_stats); } drv_get_et_strings(sdata, sset, &(data[sz_sta_stats])); + if (sset == ETH_SS_PRIV_FLAGS) + memcpy(data, ieee80211_pflags_strings, + sizeof (ieee80211_pflags_strings)); } static int ieee80211_get_regs_len(struct net_device *dev) @@ -229,6 +251,35 @@ regs->len = 0; } +static u32 ieee80211_get_priv_flags(struct net_device *dev) +{ + struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); + struct ieee80211_local *local = sdata->local; + bool powered, powered_busy; + u32 ret; + + ret = 0; + if (!drv_get_powered(local, &powered, &powered_busy)) { + ret |= POWERED_SUPPORTED; + if (powered) + ret |= POWERED_STATUS; + if (powered_busy) + ret |= POWERED_CHANGE_BUSY; + } + return ret; +} + +static int ieee80211_set_priv_flags(struct net_device *dev, u32 flags) +{ + struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); + struct ieee80211_local *local = sdata->local; + + if (flags & (POWERED_STATUS)) + return drv_set_powered(local); + + return 0; +} + const struct ethtool_ops ieee80211_ethtool_ops = { .get_drvinfo = cfg80211_get_drvinfo, .get_regs_len = ieee80211_get_regs_len, @@ -239,4 +290,6 @@ .get_strings = ieee80211_get_strings, .get_ethtool_stats = ieee80211_get_stats, .get_sset_count = ieee80211_get_sset_count, + .set_priv_flags = ieee80211_set_priv_flags, + .get_priv_flags = ieee80211_get_priv_flags, }; diff -ruw linux-4.14.127/net/mac80211/key.c linux-4.14.127-fbx/net/mac80211/key.c --- linux-4.14.127/net/mac80211/key.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/mac80211/key.c 2019-02-15 14:29:45.298669359 +0100 @@ -168,9 +168,16 @@ * The driver doesn't know anything about VLAN interfaces. * Hence, don't send GTKs for VLAN interfaces to the driver. */ - if (!(key->conf.flags & IEEE80211_KEY_FLAG_PAIRWISE)) + if (!(key->conf.flags & IEEE80211_KEY_FLAG_PAIRWISE)) { + if (ieee80211_hw_check(&key->local->hw, + APVLAN_NEED_MCAST_TO_UCAST)) { + /* no need to fail, this key will + * never be used */ + return 0; + } goto out_unsupported; } + } ret = drv_set_key(key->local, SET_KEY, sdata, sta ? &sta->sta : NULL, &key->conf); diff -ruw linux-4.14.127/net/mac80211/tx.c linux-4.14.127-fbx/net/mac80211/tx.c --- linux-4.14.127/net/mac80211/tx.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/mac80211/tx.c 2019-07-22 10:44:48.330828936 +0200 @@ -3645,6 +3645,9 @@ return false; if (sdata->wdev.use_4addr) return false; + if (ieee80211_hw_check(&sdata->local->hw, + APVLAN_NEED_MCAST_TO_UCAST)) + break; /* fall through */ case NL80211_IFTYPE_AP: /* check runtime toggle for this bss */ diff -ruw linux-4.14.127/net/netfilter/nf_conntrack_core.c linux-4.14.127-fbx/net/netfilter/nf_conntrack_core.c --- linux-4.14.127/net/netfilter/nf_conntrack_core.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/netfilter/nf_conntrack_core.c 2019-07-22 10:44:48.334828953 +0200 @@ -437,6 +437,14 @@ } EXPORT_SYMBOL_GPL(nf_ct_tmpl_free); +#ifdef CONFIG_IP_FFN +extern void ip_ffn_ct_destroy(struct nf_conn *ct); +#endif + +#ifdef CONFIG_IPV6_FFN +extern void ipv6_ffn_ct_destroy(struct nf_conn *ct); +#endif + static void destroy_conntrack(struct nf_conntrack *nfct) { @@ -446,6 +454,15 @@ pr_debug("destroy_conntrack(%p)\n", ct); WARN_ON(atomic_read(&nfct->use) != 0); +#ifdef CONFIG_IP_FFN + if (ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.src.l3num == AF_INET) + ip_ffn_ct_destroy(ct); +#endif +#ifdef CONFIG_IPV6_FFN + if (ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.src.l3num == AF_INET6) + ipv6_ffn_ct_destroy(ct); +#endif + if (unlikely(nf_ct_is_template(ct))) { nf_ct_tmpl_free(ct); return; diff -ruw linux-4.14.127/net/netfilter/nf_conntrack_ftp.c linux-4.14.127-fbx/net/netfilter/nf_conntrack_ftp.c --- linux-4.14.127/net/netfilter/nf_conntrack_ftp.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/netfilter/nf_conntrack_ftp.c 2019-02-15 14:29:45.334669501 +0100 @@ -29,6 +29,11 @@ #include #include +#if defined(CONFIG_FREEBOX_BRIDGE) || defined(CONFIG_FREEBOX_BRIDGE_MODULE) +#include +#include +#endif + MODULE_LICENSE("GPL"); MODULE_AUTHOR("Rusty Russell "); MODULE_DESCRIPTION("ftp connection tracking helper"); @@ -399,6 +404,17 @@ return NF_ACCEPT; } +#if defined(CONFIG_FREEBOX_BRIDGE) || defined(CONFIG_FREEBOX_BRIDGE_MODULE) + if (!ct_ftp_info->is_fbxbridge && skb->dev->fbx_bridge) { + struct fbxbridge *fbxbr; + + fbxbr = skb->dev->fbx_bridge; + ct_ftp_info->is_fbxbridge = 1; + ct_ftp_info->fbxbridge_remote = ntohl(fbxbr->br_remote_ipaddr); + ct_ftp_info->fbxbridge_wan = fbxbr->wan_ipaddr; + } +#endif + th = skb_header_pointer(skb, protoff, sizeof(_tcph), &_tcph); if (th == NULL) return NF_ACCEPT; @@ -485,6 +501,50 @@ * Doesn't matter unless NAT is happening. */ daddr = &ct->tuplehash[!dir].tuple.dst.u3; +#if defined(CONFIG_FREEBOX_BRIDGE) || defined(CONFIG_FREEBOX_BRIDGE_MODULE) + if (ct_ftp_info->is_fbxbridge && + search[dir][i].ftptype == NF_CT_FTP_PORT) { + unsigned long orig_ip_addr; + unsigned short orig_port; + char buffer[sizeof("nnn,nnn,nnn,nnn,nnn,nnn")]; + unsigned int len; + __be32 addr; + + /* kludge: if we are here, then this is a local pkt + * that has gone through internal fbxbridge snat. + * + * If we see a port command, then we mangle packet to + * change ip address given to the remote bridge + * address */ + + /* check address is packet is the one fbxbridge + * changed */ + orig_ip_addr = cmd.u3.ip; + if (orig_ip_addr != ct_ftp_info->fbxbridge_wan) + goto donttouch; + + /* now mangle the remote address */ + orig_port = cmd.u.tcp.port; + addr = ct_ftp_info->fbxbridge_remote; + len = sprintf(buffer, "%u,%u,%u,%u,%u,%u", + ((unsigned char *)&addr)[0], + ((unsigned char *)&addr)[1], + ((unsigned char *)&addr)[2], + ((unsigned char *)&addr)[3], + orig_port >> 8 , orig_port & 0xFF); + + nf_nat_mangle_tcp_packet(skb, ct, ctinfo, matchoff, + matchlen, buffer, len); + + /* then adjust as if nothing happened */ + matchlen = len; + cmd.u3.ip = ct_ftp_info->fbxbridge_remote; + } +donttouch: + +#endif + + /* Update the ftp info */ if ((cmd.l3num == nf_ct_l3num(ct)) && memcmp(&cmd.u3.all, &ct->tuplehash[dir].tuple.src.u3.all, diff -ruw linux-4.14.127/net/netfilter/nf_conntrack_helper.c linux-4.14.127-fbx/net/netfilter/nf_conntrack_helper.c --- linux-4.14.127/net/netfilter/nf_conntrack_helper.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/netfilter/nf_conntrack_helper.c 2019-02-15 14:29:45.338669517 +0100 @@ -38,7 +38,7 @@ EXPORT_SYMBOL_GPL(nf_ct_helper_hsize); static unsigned int nf_ct_helper_count __read_mostly; -static bool nf_ct_auto_assign_helper __read_mostly = false; +static bool nf_ct_auto_assign_helper __read_mostly = true; module_param_named(nf_conntrack_helper, nf_ct_auto_assign_helper, bool, 0644); MODULE_PARM_DESC(nf_conntrack_helper, "Enable automatic conntrack helper assignment (default 0)"); diff -ruw linux-4.14.127/net/netfilter/nf_conntrack_proto_tcp.c linux-4.14.127-fbx/net/netfilter/nf_conntrack_proto_tcp.c --- linux-4.14.127/net/netfilter/nf_conntrack_proto_tcp.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/netfilter/nf_conntrack_proto_tcp.c 2019-02-15 14:29:45.342669533 +0100 @@ -1021,7 +1021,8 @@ break; } - if (!tcp_in_window(ct, &ct->proto.tcp, dir, index, + if (!ct->proto.tcp.no_window_track && + !tcp_in_window(ct, &ct->proto.tcp, dir, index, skb, dataoff, th, pf)) { spin_unlock_bh(&ct->lock); return -NF_ACCEPT; @@ -1087,6 +1088,29 @@ return NF_ACCEPT; } +#ifdef CONFIG_IP_FFN +int external_tcpv4_packet(struct nf_conn *ct, + const struct sk_buff *skb, + unsigned int dataoff, + enum ip_conntrack_info ctinfo) +{ + return tcp_packet(ct, skb, dataoff, ctinfo, AF_INET, + tcp_get_timeouts(nf_ct_net(ct))); +} +#endif + +#ifdef CONFIG_IPV6_FFN +int external_tcpv6_packet(struct nf_conn *ct, + const struct sk_buff *skb, + unsigned int dataoff, + enum ip_conntrack_info ctinfo) +{ + return tcp_packet(ct, skb, dataoff, ctinfo, AF_INET6, + tcp_get_timeouts(nf_ct_net(ct))); +} +#endif + + /* Called when a new connection for this protocol found. */ static bool tcp_new(struct nf_conn *ct, const struct sk_buff *skb, unsigned int dataoff, unsigned int *timeouts) diff -ruw linux-4.14.127/net/netfilter/nf_conntrack_proto_udp.c linux-4.14.127-fbx/net/netfilter/nf_conntrack_proto_udp.c --- linux-4.14.127/net/netfilter/nf_conntrack_proto_udp.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/netfilter/nf_conntrack_proto_udp.c 2019-02-15 14:29:45.342669533 +0100 @@ -91,6 +91,28 @@ return NF_ACCEPT; } +#ifdef CONFIG_IP_FFN +int external_udpv4_packet(struct nf_conn *ct, + const struct sk_buff *skb, + unsigned int dataoff, + enum ip_conntrack_info ctinfo) +{ + return udp_packet(ct, skb, dataoff, ctinfo, AF_INET, + udp_get_timeouts(nf_ct_net(ct))); +} +#endif + +#ifdef CONFIG_IPV6_FFN +int external_udpv6_packet(struct nf_conn *ct, + const struct sk_buff *skb, + unsigned int dataoff, + enum ip_conntrack_info ctinfo) +{ + return udp_packet(ct, skb, dataoff, ctinfo, AF_INET, + udp_get_timeouts(nf_ct_net(ct))); +} +#endif + /* Called when a new connection for this protocol found. */ static bool udp_new(struct nf_conn *ct, const struct sk_buff *skb, unsigned int dataoff, unsigned int *timeouts) diff -ruw linux-4.14.127/net/netfilter/nf_nat_core.c linux-4.14.127-fbx/net/netfilter/nf_nat_core.c --- linux-4.14.127/net/netfilter/nf_nat_core.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/netfilter/nf_nat_core.c 2019-02-15 14:29:45.346669549 +0100 @@ -443,6 +443,11 @@ else ct->status |= IPS_SRC_NAT_DONE; + if (maniptype == NF_NAT_MANIP_SRC) { + ct->nat_src_proto_min = range->min_proto; + ct->nat_src_proto_max = range->max_proto; + } + return NF_ACCEPT; } EXPORT_SYMBOL(nf_nat_setup_info); diff -ruw linux-4.14.127/net/netfilter/nf_nat_ftp.c linux-4.14.127-fbx/net/netfilter/nf_nat_ftp.c --- linux-4.14.127/net/netfilter/nf_nat_ftp.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/netfilter/nf_nat_ftp.c 2019-02-15 14:29:45.346669549 +0100 @@ -65,7 +65,8 @@ struct nf_conntrack_expect *exp) { union nf_inet_addr newaddr; - u_int16_t port; + u_int16_t port, sport, eport; + unsigned int i; int dir = CTINFO2DIR(ctinfo); struct nf_conn *ct = exp->master; char buffer[sizeof("|1||65535|") + INET6_ADDRSTRLEN]; @@ -82,8 +83,26 @@ * this one. */ exp->expectfn = nf_nat_follow_master; + if (dir == IP_CT_DIR_ORIGINAL && + (ct->status & IPS_SRC_NAT) && + ct->nat_src_proto_min.all && + ct->nat_src_proto_max.all) { + sport = ntohs(ct->nat_src_proto_min.all); + eport = ntohs(ct->nat_src_proto_max.all); + } else { + sport = 1024; + eport = 65535; + } + + port = ntohs(exp->saved_proto.tcp.port); + if (port < sport || port > eport) { + get_random_bytes(&port, sizeof (port)); + port %= eport - sport; + port += sport; + } + /* Try to get same port: if not, try to change it. */ - for (port = ntohs(exp->saved_proto.tcp.port); port != 0; port++) { + for (i = 0; i < eport - sport + 1; i++) { int ret; exp->tuple.dst.u.tcp.port = htons(port); @@ -94,6 +113,10 @@ port = 0; break; } + + port++; + if (port > eport) + port = sport; } if (port == 0) { diff -ruw linux-4.14.127/net/netfilter/nf_nat_helper.c linux-4.14.127-fbx/net/netfilter/nf_nat_helper.c --- linux-4.14.127/net/netfilter/nf_nat_helper.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/netfilter/nf_nat_helper.c 2019-02-15 14:29:45.346669549 +0100 @@ -200,6 +200,14 @@ range.flags = NF_NAT_RANGE_MAP_IPS; range.min_addr = range.max_addr = ct->master->tuplehash[!exp->dir].tuple.dst.u3; + + if (ct->master->nat_src_proto_min.all && + ct->master->nat_src_proto_max.all) { + range.flags |= NF_NAT_RANGE_PROTO_SPECIFIED; + range.min_proto = ct->master->nat_src_proto_min; + range.max_proto = ct->master->nat_src_proto_max; + } + nf_nat_setup_info(ct, &range, NF_NAT_MANIP_SRC); /* For DST manip, map port here to where it's expected. */ diff -ruw linux-4.14.127/net/netfilter/xt_owner.c linux-4.14.127-fbx/net/netfilter/xt_owner.c --- linux-4.14.127/net/netfilter/xt_owner.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/netfilter/xt_owner.c 2019-02-15 14:29:45.358669596 +0100 @@ -59,6 +59,55 @@ return 0; } +static int __owner_match_simple_gid(kgid_t gid, kgid_t gid_min, kgid_t gid_max) +{ + return gid_gte(gid, gid_min) && gid_lte(gid, gid_max); +} + +/* + * see kernel/groups.c:groups_to_user() function, which inspired the + * content of this function. + */ +static int __owner_match_gid_groupinfo(const struct group_info *group_info, + kgid_t gid_min, kgid_t gid_max) +{ + int i; + + for (i = 0; i < group_info->ngroups; i++) { + kgid_t kgid = group_info->gid[i]; + + if (__owner_match_simple_gid(kgid, gid_min, gid_max)) + return 1; + } + + return 0; +} + +static int owner_match_gid(struct net *net, + const struct file *filp, + const struct xt_owner_match_info *info) +{ + kgid_t gid_min = make_kgid(net->user_ns, info->gid_min); + kgid_t gid_max = make_kgid(net->user_ns, info->gid_max); + + /* + * direct match, this is the simple and only case handled by + * the old code, file fsgid matches info gid range. + */ + if (__owner_match_simple_gid(filp->f_cred->fsgid, gid_min, gid_max)) + return 1; + + /* + * otherwise we need to have a look to the group list available + * in f_cred->group_info. + */ + if (__owner_match_gid_groupinfo(filp->f_cred->group_info, + gid_min, gid_max)) + return 1; + + return 0; +} + static bool owner_mt(const struct sk_buff *skb, struct xt_action_param *par) { @@ -91,10 +140,7 @@ } if (info->match & XT_OWNER_GID) { - kgid_t gid_min = make_kgid(net->user_ns, info->gid_min); - kgid_t gid_max = make_kgid(net->user_ns, info->gid_max); - if ((gid_gte(filp->f_cred->fsgid, gid_min) && - gid_lte(filp->f_cred->fsgid, gid_max)) ^ + if (owner_match_gid(net, filp, info) ^ !(info->invert & XT_OWNER_GID)) return false; } diff -ruw linux-4.14.127/net/sched/sch_drr.c linux-4.14.127-fbx/net/sched/sch_drr.c --- linux-4.14.127/net/sched/sch_drr.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/sched/sch_drr.c 2019-02-15 14:29:45.406669787 +0100 @@ -330,7 +330,9 @@ cl = drr_find_class(sch, res.classid); return cl; } - return NULL; + + /* default to first minor if it exists, or drop */ + return drr_find_class(sch, TC_H_MAKE(TC_H_MAJ(sch->handle), 1)); } static int drr_enqueue(struct sk_buff *skb, struct Qdisc *sch, diff -ruw linux-4.14.127/net/socket.c linux-4.14.127-fbx/net/socket.c --- linux-4.14.127/net/socket.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/socket.c 2019-05-10 11:02:37.980385770 +0200 @@ -983,6 +983,29 @@ return err; } +static DEFINE_MUTEX(fbxbridge_ioctl_mutex); +static int (*fbxbridge_ioctl_hook)(struct net *, unsigned int cmd, void __user *arg) = NULL; + +void fbxbridge_set(int (*hook)(struct net *, unsigned int, void __user *)) +{ + mutex_lock(&fbxbridge_ioctl_mutex); + fbxbridge_ioctl_hook = hook; + mutex_unlock(&fbxbridge_ioctl_mutex); +} + +static DEFINE_MUTEX(fbxdiverter_ioctl_mutex); +static int (*fbxdiverter_ioctl_hook) (struct net *, unsigned int cmd, void __user *arg) = NULL; + +void fbxdiverter_ioctl_set(int (*hook) (struct net *, unsigned int, + void __user *)) +{ + mutex_lock(&fbxdiverter_ioctl_mutex); + fbxdiverter_ioctl_hook = hook; + mutex_unlock(&fbxdiverter_ioctl_mutex); +} + +EXPORT_SYMBOL(fbxdiverter_ioctl_set); + /* * With an ioctl, arg may well be a user mode pointer, but we don't know * what to do with it - that's up to the protocol still. @@ -1066,6 +1089,28 @@ break; err = open_related_ns(&net->ns, get_net_ns); + + case SIOCGFBXDIVERT: + case SIOCSFBXDIVERT: + err = -ENOPKG; + if (!fbxdiverter_ioctl_hook) + request_module("fbxdiverter"); + + mutex_lock(&fbxdiverter_ioctl_mutex); + if (fbxdiverter_ioctl_hook) + err = fbxdiverter_ioctl_hook(net, cmd, argp); + mutex_unlock(&fbxdiverter_ioctl_mutex); + break; + case SIOCGFBXBRIDGE: + case SIOCSFBXBRIDGE: + err = -ENOPKG; + if (!fbxbridge_ioctl_hook) + request_module("fbxbridge"); + + mutex_lock(&fbxbridge_ioctl_mutex); + if (fbxbridge_ioctl_hook) + err = fbxbridge_ioctl_hook(net, cmd, argp); + mutex_unlock(&fbxbridge_ioctl_mutex); break; default: err = sock_do_ioctl(net, sock, cmd, arg); diff -ruw linux-4.14.127/net/unix/Kconfig linux-4.14.127-fbx/net/unix/Kconfig --- linux-4.14.127/net/unix/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/unix/Kconfig 2019-02-15 14:29:45.454669977 +0100 @@ -19,6 +19,9 @@ Say Y unless you know what you are doing. +config UNIX_ABSTRACT_IGNORE_NETNS + bool "make abstract namespace global to all network namespaces" + config UNIX_DIAG tristate "UNIX: socket monitoring interface" depends on UNIX diff -ruw linux-4.14.127/net/unix/af_unix.c linux-4.14.127-fbx/net/unix/af_unix.c --- linux-4.14.127/net/unix/af_unix.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/unix/af_unix.c 2019-05-10 11:02:37.988385803 +0200 @@ -280,8 +280,10 @@ sk_for_each(s, &unix_socket_table[hash ^ type]) { struct unix_sock *u = unix_sk(s); +#ifdef UNIX_ABSTRACT_IGNORE_NETNS if (!net_eq(sock_net(s), net)) continue; +#endif if (u->addr->len == len && !memcmp(u->addr->name, sunname, len)) diff -ruw linux-4.14.127/net/wireless/db.txt linux-4.14.127-fbx/net/wireless/db.txt --- linux-4.14.127/net/wireless/db.txt 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/wireless/db.txt 2019-02-15 14:29:45.462670009 +0100 @@ -1,17 +1,1319 @@ +# This is the world regulatory domain +country 00: + (2402 - 2472 @ 40), (20) + # Channel 12 - 13. + (2457 - 2482 @ 20), (20), NO-IR, AUTO-BW + # Channel 14. Only JP enables this and for 802.11b only + (2474 - 2494 @ 20), (20), NO-IR, NO-OFDM + # Channel 36 - 48 + (5170 - 5250 @ 80), (20), NO-IR, AUTO-BW + # Channel 52 - 64 + (5250 - 5330 @ 80), (20), NO-IR, DFS, AUTO-BW + # Channel 100 - 144 + (5490 - 5730 @ 160), (20), NO-IR, DFS + # Channel 149 - 165 + (5735 - 5835 @ 80), (20), NO-IR + # IEEE 802.11ad (60GHz), channels 1..3 + (57240 - 63720 @ 2160), (0) + + +country AD: + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20) + (5250 - 5330 @ 80), (20), DFS + (5490 - 5710 @ 80), (27), DFS + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country AE: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (17), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country AF: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + +# Source: +# http://pucanguilla.org/Downloads/January2005-Anguilla%20Table%20of%20Allocations.pdf +country AI: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + +country AL: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20.00), AUTO-BW + (5250 - 5330 @ 80), (20.00), DFS, AUTO-BW + (5490 - 5710 @ 160), (27.00), DFS + +country AM: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 20), (18) + (5250 - 5330 @ 20), (18), DFS + +country AN: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + +country AR: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (17), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country AS: DFS-FCC + (2402 - 2472 @ 40), (30) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country AT: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +# Source: +# https://www.legislation.gov.au/Details/F2016C00432 +# Both DFS-ETSI and DFS-FCC are acceptable per AS/NZS 4268 Appendix B. +# The EIRP for DFS bands can be increased by 3dB if TPC is implemented. +# In order to allow 80MHz operation between 5650-5730MHz the upper boundary +# of this more restrictive band has been shifted up by 5MHz from 5725MHz. +country AU: DFS-ETSI + (2400 - 2483.5 @ 40), (36) + (5150 - 5250 @ 80), (23), NO-OUTDOOR, AUTO-BW + (5250 - 5350 @ 80), (20), NO-OUTDOOR, AUTO-BW, DFS + (5470 - 5600 @ 80), (27), DFS + (5650 - 5730 @ 80), (27), DFS + (5730 - 5850 @ 80), (36) + (57000 - 66000 @ 2160), (43), NO-OUTDOOR + +country AW: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + +country AZ: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (18), AUTO-BW + (5250 - 5330 @ 80), (18), DFS, AUTO-BW + +country BA: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country BB: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5735 - 5835 @ 80), (30) + +country BD: DFS-JP + (2402 - 2482 @ 40), (20) + (5735 - 5835 @ 80), (30) + +country BE: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country BF: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (17), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +# Bulgarian rules as defined by the Communications Regulation Commission in the +# following documents: # -# This file is a placeholder to prevent accidental build breakage if someone -# enables CONFIG_CFG80211_INTERNAL_REGDB. Almost no one actually needs to -# enable that build option. -# -# You should be using CRDA instead. It is even better if you use the CRDA -# package provided by your distribution, since they will probably keep it -# up-to-date on your behalf. -# -# If you _really_ intend to use CONFIG_CFG80211_INTERNAL_REGDB then you will -# need to replace this file with one containing appropriately formatted -# regulatory rules that cover the regulatory domains you will be using. Your -# best option is to extract the db.txt file from the wireless-regdb git -# repository: +# Rules for carrying out electronic communications through radio equipment using +# radio spectrum, which does not need to be individually assigned (the Rules): +# http://www.crc.bg/files/_bg/Pravila_09_06_2015.pdf # -# git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-regdb.git +# List of radio equipment that uses harmonized within the European Union bands +# and electronic communications terminal equipment (the List): +# http://www.crc.bg/files/_bg/Spisak_2015.pdf # +# Note: The transmit power limits in the 5250-5350 MHz and 5470-5725 MHz bands +# can be raised by 3 dBm if TPC is enabled. Refer to BDS EN 301 893 for details. +country BG: DFS-ETSI + # Wideband data transmission systems (WDTS) in the 2.4GHz ISM band, ref: + # I.22 of the List, BDS EN 300 328 + (2402 - 2482 @ 40), (20) + # 5 GHz Radio Local Area Networks (RLANs), ref: + # II.H01 of the List, BDS EN 301 893 + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + # II.H01 of the List, I.54 from the List, BDS EN 301 893 + (5490 - 5710 @ 160), (27), DFS + # Short range devices (SRDs) in the 5725-5875 MHz frequency range, ref: + # I.43 of the List, BDS EN 300 440-2, BDS EN 300 440-1 + (5725 - 5875 @ 80), (14) + # 60 GHz Multiple-Gigabit RLAN Systems, ref: + # II.H03 of the List, BDS EN 302 567-2 + (57000 - 66000 @ 2160), (40), NO-OUTDOOR + +country BH: DFS-JP + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 20), (20) + (5250 - 5330 @ 20), (20), DFS + (5735 - 5835 @ 20), (20) + +country BL: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + +country BM: DFS-FCC + (2402 - 2472 @ 40), (30) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country BN: DFS-JP + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5735 - 5835 @ 80), (20) + +country BO: DFS-JP + (2402 - 2482 @ 40), (20) + (5250 - 5330 @ 80), (30), DFS + (5735 - 5835 @ 80), (30) + +country BR: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (17), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country BS: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +# Source: +# http://www.bicma.gov.bt/paper/publication/nrrpart4.pdf +country BT: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + +country BY: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + +country BZ: DFS-JP + (2402 - 2482 @ 40), (30) + (5735 - 5835 @ 80), (30) + +# Source: +# https://www.ic.gc.ca/eic/site/smt-gst.nsf/vwapj/rss-247-i2-e.pdf/$file/rss-247-i2-e.pdf +country CA: DFS-FCC + (2402 - 2472 @ 40), (30) + (5150 - 5250 @ 80), (23), NO-OUTDOOR, AUTO-BW + (5250 - 5350 @ 80), (24), DFS, AUTO-BW + (5470 - 5600 @ 80), (24), DFS + (5650 - 5730 @ 80), (24), DFS + (5735 - 5835 @ 80), (30) + +# Source: +# http://www.art-rca.org +country CF: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 40), (17) + (5250 - 5330 @ 40), (24), DFS + (5490 - 5730 @ 40), (24), DFS + (5735 - 5835 @ 40), (30) + +country CH: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country CI: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (17), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country CL: DFS-JP + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5735 - 5835 @ 80), (20) + +country CN: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5735 - 5835 @ 80), (30) + # 60 GHz band channels 1,4: 28dBm, channels 2,3: 44dBm + # ref: http://www.miit.gov.cn/n11293472/n11505629/n11506593/n11960250/n11960606/n11960700/n12330791.files/n12330790.pdf + (57240 - 59400 @ 2160), (28) + (59400 - 63720 @ 2160), (44) + (63720 - 65880 @ 2160), (28) + +country CO: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (17), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country CR: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 20), (17) + (5250 - 5330 @ 20), (24), DFS + (5490 - 5730 @ 20), (24), DFS + (5735 - 5835 @ 20), (30) + +# http://www.mincom.gob.cu/?q=marcoregulatorio +# - Redes Informáticas +# Resolución 127, 2011 - Reglamento Banda 2,4 GHz. +country CU: DFS-FCC + (2400 - 2483.5 @ 40), (200 mW) + +country CX: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country CY: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +# Data from http://www.ctu.eu/164/download/VOR/VOR-12-08-2005-34.pdf +# and http://www.ctu.eu/164/download/VOR/VOR-12-05-2007-6-AN.pdf +# Power at 5250 - 5350 MHz and 5470 - 5725 MHz can be doubled if TPC is +# implemented. +country CZ: DFS-ETSI + (2400 - 2483.5 @ 40), (100 mW) + (5150 - 5250 @ 80), (200 mW), NO-OUTDOOR, AUTO-BW + (5250 - 5350 @ 80), (100 mW), NO-OUTDOOR, DFS, AUTO-BW + (5470 - 5725 @ 160), (500 mW), DFS + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +# Allocation for the 2.4 GHz band (Vfg 10 / 2013, Allgemeinzuteilung von +# Frequenzen für die Nutzung in lokalen Netzwerken; Wireless Local Area +# Networks (WLAN-Funkanwendungen). +# https://www.bundesnetzagentur.de/SharedDocs/Downloads/DE/Sachgebiete/Telekommunikation/Unternehmen_Institutionen/Frequenzen/Allgemeinzuteilungen/2013_10_WLAN_2,4GHz_pdf.pdf +# +# Allocation for the 5 GHz band (Vfg. 7 / 2010, Allgemeinzuteilung von +# Frequenzen in den Bereichen 5150 MHz - 5350 MHz und 5470 MHz - 5725 MHz für +# Funkanwendungen zur breitbandigen Datenübertragung, WAS/WLAN („Wireless +# Access Systems including Wireless Local Area Networks“). +# https://www.bundesnetzagentur.de/SharedDocs/Downloads/DE/Sachgebiete/Telekommunikation/Unternehmen_Institutionen/Frequenzen/Allgemeinzuteilungen/2010_07_WLAN_5GHz_pdf.pdf +# The values for the 5 GHz have been reduced by a factor of 2 (3db) for non TPC +# devices (in other words: devices with TPC can use twice the tx power of this +# table). Note that the docs do not require TPC for 5150--5250; the reduction +# to 100mW thus is not strictly required -- however the conservative 100mW +# limit is used here as the non-interference with radar and satellite +# apps relies on the attenuation by the building walls only in the +# absence of DFS; the neighbour countries have 100mW limit here as well. +# +# The ETSI EN 300 440-1 standard for short range devices in the 5 GHz band has +# been implemented in Germany: +# https://www.bundesnetzagentur.de/SharedDocs/Downloads/DE/Sachgebiete/Telekommunikation/Unternehmen_Institutionen/Frequenzen/Allgemeinzuteilungen/2014_69_SRD_pdf.pdf +# +# Allocation for the 60 GHz band (Allgemeinzuteilung von Frequenzen im +# Bereich 57 GHz - 66 GHz für Funkanwendungen für weitbandige +# Datenübertragungssysteme; „Multiple Gigabit WAS/RLAN Systems (MGWS)“). +# https://www.bundesnetzagentur.de/SharedDocs/Downloads/DE/Sachgebiete/Telekommunikation/Unternehmen_Institutionen/Frequenzen/Allgemeinzuteilungen/2011_08_MGWS_pdf.pdf + +country DE: DFS-ETSI + (2400 - 2483.5 @ 40), (100 mW) + (5150 - 5250 @ 80), (100 mW), NO-OUTDOOR, AUTO-BW + (5250 - 5350 @ 80), (100 mW), NO-OUTDOOR, DFS, AUTO-BW + (5470 - 5725 @ 160), (500 mW), DFS + # short range devices (ETSI EN 300 440-1) + (5725 - 5875 @ 80), (25 mW) + # 60 GHz band channels 1-4 (ETSI EN 302 567) + (57000 - 66000 @ 2160), (40) + +country DK: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +# Source: +# http://www.ntrcdom.org/index.php?option=com_content&view=category&layout=blog&id=10&Itemid=55 +country DM: DFS-FCC + (2402 - 2472 @ 40), (30) + (5170 - 5250 @ 80), (17), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5735 - 5835 @ 80), (30) + +country DO: DFS-FCC + (2402 - 2472 @ 40), (30) + (5170 - 5250 @ 80), (17), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5735 - 5835 @ 80), (30) + +country DZ: DFS-JP + (2402 - 2482 @ 40), (20) + (5170.000 - 5250.000 @ 80.000), (23.00), AUTO-BW + (5250.000 - 5330.000 @ 80.000), (23.00), DFS, AUTO-BW + (5490.000 - 5670.000 @ 160.000), (23.00), DFS + +country EC: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 20), (17) + (5250 - 5330 @ 20), (24), DFS + (5490 - 5730 @ 20), (24), DFS + (5735 - 5835 @ 20), (30) + +country EE: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country EG: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 40), (20) + (5250 - 5330 @ 40), (20), DFS + +# Orden IET/787/2013, de 25 de abril, por la que se aprueba +# el cuadro nacional de atribución de frecuencias. +# http://www.boe.es/diario_boe/txt.php?id=BOE-A-2013-4845 +# +# more info at "Cuadro nacional de atribución de frecuencias (CNAF)": +# http://www.minetur.gob.es/telecomunicaciones/espectro/paginas/cnaf.aspx + +country ES: DFS-ETSI + (2400 - 2483.5 @ 40), (100 mW) + (5150 - 5250 @ 80), (200 mW), NO-OUTDOOR, AUTO-BW + (5250 - 5350 @ 80), (100 mW), NO-OUTDOOR, DFS, AUTO-BW + (5470 - 5725 @ 160), (500 mW), DFS + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country ET: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + +country FI: DFS-ETSI + (2400 - 2483.5 @ 40), (20) + (5150 - 5250 @ 80), (23), NO-OUTDOOR, AUTO-BW + (5250 - 5350 @ 80), (20), NO-OUTDOOR, DFS, AUTO-BW + (5470 - 5725 @ 160), (27), DFS + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country FM: DFS-FCC + (2402 - 2472 @ 40), (30) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country FR: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country GB: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country GD: DFS-FCC + (2402 - 2472 @ 40), (30) + (5170 - 5250 @ 80), (17), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country GE: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (18), AUTO-BW + (5250 - 5330 @ 80), (18), DFS, AUTO-BW + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country GF: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + +country GH: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (17), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country GL: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + +country GP: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + +country GR: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country GT: DFS-FCC + (2402 - 2472 @ 40), (30) + (5170 - 5250 @ 80), (17), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5735 - 5835 @ 80), (30) + +country GU: DFS-FCC + (2402 - 2472 @ 40), (30) + (5170 - 5250 @ 20), (17) + (5250 - 5330 @ 20), (24), DFS + (5490 - 5730 @ 20), (24), DFS + (5735 - 5835 @ 20), (30) + +country GY: + (2402 - 2482 @ 40), (30) + (5735 - 5835 @ 80), (30) + +country HK: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (17), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5710 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country HN: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (17), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country HR: DFS-ETSI + (2400 - 2483.5 @ 40), (20) + (5150 - 5250 @ 80), (23), NO-OUTDOOR, AUTO-BW + (5250 - 5350 @ 80), (20), NO-OUTDOOR, DFS, AUTO-BW + (5470 - 5725 @ 160), (27), DFS + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country HT: DFS-FCC + (2402 - 2472 @ 40), (30) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country HU: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country ID: DFS-JP + # ref: http://www.postel.go.id/content/ID/regulasi/standardisasi/kepdir/bwa%205,8%20ghz.pdf + (2402 - 2482 @ 20), (20) + (5735 - 5815 @ 20), (23) + +country IE: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country IL: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5150 - 5250 @ 80), (200 mW), NO-OUTDOOR, AUTO-BW + (5250 - 5350 @ 80), (200 mW), NO-OUTDOOR, DFS, AUTO-BW + +country IN: + (2402 - 2482 @ 40), (20) + (5150 - 5350 @ 160), (23) + (5725 - 5875 @ 80), (23) + +country IR: DFS-JP + (2402 - 2482 @ 40), (20) + (5735 - 5835 @ 80), (30) + +country IS: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country IT: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country JM: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (17), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country JO: DFS-JP + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23) + (5735 - 5835 @ 80), (23) + +country JP: DFS-JP + (2402 - 2482 @ 40), (20) + (2474 - 2494 @ 20), (20), NO-OFDM + (4910 - 4990 @ 40), (23) + (5030 - 5090 @ 40), (23) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (23), DFS + # 60 GHz band channels 2-4 at 10mW, + # ref: http://www.arib.or.jp/english/html/overview/doc/1-STD-T74v1_1.pdf + (59000 - 66000 @ 2160), (10 mW) + +country KE: DFS-JP + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23) + (5490 - 5570 @ 80), (30), DFS + (5735 - 5775 @ 40), (23) + +country KH: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + +# Source +# http://ntrc.kn/?page_id=7 +country KN: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + (5735 - 5815 @ 80), (30) + +country KP: DFS-JP + (2402 - 2482 @ 20), (20) + (5170 - 5250 @ 20), (20) + (5250 - 5330 @ 20), (20), DFS + (5490 - 5630 @ 20), (30), DFS + (5735 - 5815 @ 20), (30) + +country KR: DFS-JP + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + (5735 - 5835 @ 80), (30) + # 60 GHz band channels 1-4, + # ref: http://www.law.go.kr/%ED%96%89%EC%A0%95%EA%B7%9C%EC%B9%99/%EB%AC%B4%EC%84%A0%EC%84%A4%EB%B9%84%EA%B7%9C%EC%B9%99 + (57000 - 66000 @ 2160), (43) + +country KW: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + +country KY: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country KZ: + (2402 - 2482 @ 40), (20) + +country LB: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (17), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +# Source: +# http://www.ntrc.org.lc/operational_structures.htm +country LC: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (30), DFS + (5735 - 5815 @ 80), (30) + +country LI: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + +country LK: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 20), (17) + (5250 - 5330 @ 20), (24), DFS + (5490 - 5730 @ 20), (24), DFS + (5735 - 5835 @ 20), (30) + +# Source: +# http://lca.org.ls/images/documents/lesotho_national_frequency_allocation_plan.pdf +country LS: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + +country LT: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country LU: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country LV: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country MA: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + +country MC: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + +# Source: +# http://www.cnfr.md/index.php?pag=sec&id=117&l=en +country MD: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + +# Source: +# http://www.cept.org/files/1050/Tools%20and%20Services/EFIS%20-%20ECO%20Frequency%20Information%20System/National%20frequency%20tables/Montenegro%20NAFT%20-%202010.pdf +country ME: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + +country MF: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + +country MH: DFS-FCC + (2402 - 2472 @ 40), (30) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country MK: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country MN: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country MO: DFS-FCC + (2402 - 2482 @ 40), (23) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5730 @ 160), (30), DFS + (5735 - 5835 @ 80), (30) + +country MP: DFS-FCC + (2402 - 2472 @ 40), (30) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country MQ: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + +# Source: +# http://www.are.mr/pdfs/telec_freq_TNAbf_2010.pdf +country MR: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + +country MT: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country MU: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +# Source: +# http://www.cam.gov.mv/docs/tech_standards/TAM-TS-100-2004-WLAN.pdf +country MV: DFS-ETSI + (2400 - 2483.5 @ 40), (100 mW) + (5150 - 5250 @ 80), (200 mW), AUTO-BW + (5250 - 5350 @ 80), (100 mW), DFS, AUTO-BW + (5725 - 5850 @ 80), (100 mW) + +country MW: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + +country MX: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (17), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country MY: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5650 @ 160), (24), DFS + (5735 - 5835 @ 80), (24) + +country NG: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5250 - 5330 @ 80), (30), DFS + (5735 - 5835 @ 80), (30) + +country NI: DFS-FCC + (2402 - 2472 @ 40), (30) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +# Regulation on the use of frequency space without a license and +# without notification 2015 +# +# http://wetten.overheid.nl/BWBR0036378/2015-03-05 + +country NL: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), NO-OUTDOOR, AUTO-BW + (5250 - 5330 @ 80), (20), NO-OUTDOOR, DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + # short range devices (ETSI EN 300 440-1) + (5725 - 5875 @ 80), (25 mW) + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +# Data from http://www.lovdata.no/dokument/SF/forskrift/2012-01-19-77 +# Power at 5250 - 5350 MHz, 5470 - 5725 MHz and 5815 – 5850 MHz can +# be doubled if TPC is implemented. +# Up to 2W (or 4W with TPC) is allowed in the 5725 – 5795 MHz band +# which has been merged with 5470 - 5725 MHz to allow wide channels +country NO: DFS-ETSI + (2400 - 2483.5 @ 40), (100 mW) + (5150 - 5250 @ 80), (200 mW), AUTO-BW + (5250 - 5350 @ 80), (100 mW), DFS, AUTO-BW + (5470 - 5795 @ 160), (500 mW), DFS + (5815 - 5850 @ 35), (2000 mW), DFS + (17100 - 17300 @ 200), (100 mW) + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country NP: DFS-JP + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5735 - 5835 @ 80), (20) + +country NZ: DFS-ETSI + (2402 - 2482 @ 40), (30) + (5170 - 5250 @ 80), (17), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country OM: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + +country PA: DFS-FCC + (2402 - 2472 @ 40), (30) + (5170 - 5250 @ 80), (17), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5735 - 5835 @ 80), (30) + +country PE: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (17), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country PF: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + +country PG: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (17), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country PH: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (17), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country PK: DFS-JP + (2402 - 2482 @ 40), (20) + (5735 - 5835 @ 80), (30) + +country PL: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country PM: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + +country PR: DFS-FCC + (2402 - 2472 @ 40), (30) + (5170 - 5250 @ 80), (17), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country PT: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country PW: DFS-FCC + (2402 - 2472 @ 40), (30) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country PY: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country QA: DFS-JP + (2402 - 2482 @ 40), (20) + (5735 - 5835 @ 80), (30) + +country RE: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + +country RO: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + + +# Source: +# http://www.ratel.rs/upload/documents/Plan_namene/Plan_namene-sl_glasnik.pdf +country RS: DFS-ETSI + (2400 - 2483.5 @ 40), (100 mW) + (5150 - 5350 @ 40), (200 mW), NO-OUTDOOR + (5470 - 5725 @ 20), (1000 mW), DFS + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country RU: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5650 - 5730 @ 80), (30), DFS + (5735 - 5835 @ 80), (30) + # 60 GHz band channels 1-4, ref: Changes to NLA 124_Order №129_22042015.pdf + (57000 - 66000 @ 2160), (40) + +country RW: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (17), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country SA: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + +country SE: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country SG: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (17), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country SI: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country SK: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +# Source: +# Regulation N° 2004-005 ART/DG/DRC/D.Rég +country SN: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (17), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country SR: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + +country SV: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 20), (17) + (5250 - 5330 @ 20), (23), DFS + (5735 - 5835 @ 20), (30) + +country SY: + (2402 - 2482 @ 40), (20) + +# Source: +# http://www.telecommission.tc/Spectrum-plan20110324-101210.html +country TC: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country TD: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + +country TG: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 40), (20) + (5250 - 5330 @ 40), (20), DFS + (5490 - 5710 @ 40), (27), DFS + +country TH: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (17), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country TN: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + +country TR: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country TT: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (17), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +# Source: +# Table of Frequency Allocations of Republic of China (Taiwan) / Feb 2017: +# https://www.motc.gov.tw/websitedowndoc?file=post/201702221012200.doc& \ +# filedisplay=Table%2Bof%2Bradio%2Bfrequency%2Ballocation.doc +# LP0002 Low-power Radio-frequency Devices Technical Regulations / 23 Aug 2016: +# http://www.ncc.gov.tw/english/show_file.aspx?table_name=news&file_sn=681 +country TW: DFS-FCC + # 2.4g band, LP0002 section 3.10.1 + (2400 - 2483.5 @ 40), (30) + # 5g U-NII band, LP0002 section 4.7 + # 5.15 ~ 5.25 GHz: 30 dBm for master mode, 23 dBm for clients + (5150 - 5250 @ 80), (23), AUTO-BW + (5250 - 5350 @ 80), (23), DFS, AUTO-BW + (5470 - 5725 @ 160), (23), DFS + (5725 - 5850 @ 80), (30) + # 60g band, LP0002 section 3.13.1.1 (3)(C), EIRP=40dBm(43dBm peak) + (57000 - 66000 @ 2160), (40) + +country TZ: + (2402 - 2482 @ 40), (20) + (5735 - 5835 @ 80), (30) + +# Source: +# #914 / 06 Sep 2007: http://www.ucrf.gov.ua/uk/doc/nkrz/1196068874 +# #1174 / 23 Oct 2008: http://www.nkrz.gov.ua/uk/activities/ruling/1225269361 +# (appendix 8) +# Listed 5GHz range is a lowest common denominator for all related +# rules in the referenced laws. Such a range is used because of +# disputable definitions there. +country UA: DFS-ETSI + (2400 - 2483.5 @ 40), (20), NO-OUTDOOR + (5150 - 5250 @ 80), (20), NO-OUTDOOR, AUTO-BW + (5250 - 5350 @ 80), (20), DFS, NO-OUTDOOR, AUTO-BW + (5490 - 5670 @ 160), (20), DFS + (5735 - 5835 @ 80), (20) + # 60 GHz band channels 1-4, ref: Etsi En 302 567 + (57000 - 66000 @ 2160), (40) + +country UG: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country US: DFS-FCC + (2402 - 2472 @ 40), (30) + # 5.15 ~ 5.25 GHz: 30 dBm for master mode, 23 dBm for clients + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5490 - 5730 @ 160), (23), DFS + (5735 - 5835 @ 80), (30) + # 60g band + # reference: http://cfr.regstoday.com/47cfr15.aspx#47_CFR_15p255 + # channels 1,2,3, EIRP=40dBm(43dBm peak) + (57240 - 63720 @ 2160), (40) + +country UY: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5735 - 5835 @ 80), (30) + +# Source: +# http://cemc.uz/article/1976/ +country UZ: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + +# Source: +# http://www.ntrc.vc/regulations/Jun_2006_Spectrum_Managment_Regulations.pdf +country VC: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + +# Source: +# Official Gazette (Gaceta Oficial) concerning Unlicensed transmitter use +# (10 June 2013) +# http://www.conatel.gob.ve/ +country VE: DFS-FCC + (2402 - 2482 @ 40), (30) + (5170 - 5250 @ 80), (23), AUTO-BW + (5250 - 5330 @ 80), (23), DFS, AUTO-BW + (5735 - 5835 @ 80), (30) + +country VI: DFS-FCC + (2402 - 2472 @ 40), (30) + (5170 - 5250 @ 80), (24), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country VN: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (17) + (5250 - 5330 @ 80), (24), DFS + (5490 - 5730 @ 80), (24), DFS + (5735 - 5835 @ 80), (30) + +# Source: +# http://www.trr.vu/attachments/category/130/GURL_for_Short-range_Radiocommunication_Devices2.pdf +country VU: DFS-FCC + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (17), AUTO-BW + (5250 - 5330 @ 80), (24), DFS, AUTO-BW + (5490 - 5730 @ 160), (24), DFS + (5735 - 5835 @ 80), (30) + +country WF: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + +country WS: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 40), (20) + (5250 - 5330 @ 40), (20), DFS + (5490 - 5710 @ 40), (27), DFS + +country YE: + (2402 - 2482 @ 40), (20) + +country YT: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + +country ZA: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (30) + +country ZW: DFS-ETSI + (2402 - 2482 @ 40), (20) + (5170 - 5250 @ 80), (20), AUTO-BW + (5250 - 5330 @ 80), (20), DFS, AUTO-BW + (5490 - 5710 @ 160), (27), DFS + diff -ruw linux-4.14.127/net/wireless/reg.c linux-4.14.127-fbx/net/wireless/reg.c --- linux-4.14.127/net/wireless/reg.c 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/net/wireless/reg.c 2019-05-10 11:02:37.992385819 +0200 @@ -1219,6 +1219,9 @@ if (chan->flags & IEEE80211_CHAN_RADAR) { chan->dfs_cac_ms = IEEE80211_DFS_MIN_CAC_TIME_MS; + if (chan->center_freq >= 5600 && + chan->center_freq <= 5650) + chan->dfs_cac_ms = IEEE80211_DFS_WEATHER_MIN_CAC_TIME_MS; if (reg_rule->dfs_cac_ms) chan->dfs_cac_ms = reg_rule->dfs_cac_ms; } @@ -1239,9 +1242,14 @@ if (chan->flags & IEEE80211_CHAN_RADAR) { if (reg_rule->dfs_cac_ms) chan->dfs_cac_ms = reg_rule->dfs_cac_ms; + else { + if (chan->center_freq >= 5600 && + chan->center_freq <= 5650) + chan->dfs_cac_ms = IEEE80211_DFS_WEATHER_MIN_CAC_TIME_MS; else chan->dfs_cac_ms = IEEE80211_DFS_MIN_CAC_TIME_MS; } + } if (chan->orig_mpwr) { /* diff -ruw linux-4.14.127/scripts/Makefile.lib linux-4.14.127-fbx/scripts/Makefile.lib --- linux-4.14.127/scripts/Makefile.lib 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/scripts/Makefile.lib 2019-02-15 14:29:45.494670136 +0100 @@ -288,11 +288,11 @@ DTC_FLAGS += $(DTC_FLAGS_$(basetarget)) # Generate an assembly file to wrap the output of the device tree compiler -quiet_cmd_dt_S_dtb= DTB $@ +quiet_cmd_dt_S_dtb= DTB_bin $@ cmd_dt_S_dtb= \ ( \ echo '\#include '; \ - echo '.section .dtb.init.rodata,"a"'; \ + echo '.section .dtb.rodata,"a"'; \ echo '.balign STRUCT_ALIGNMENT'; \ echo '.global __dtb_$(subst -,_,$(*F))_begin'; \ echo '__dtb_$(subst -,_,$(*F))_begin:'; \ @@ -302,6 +302,8 @@ echo '.balign STRUCT_ALIGNMENT'; \ ) > $@ +.PRECIOUS: $(src)/%.dtb.S + $(obj)/%.dtb.S: $(obj)/%.dtb $(call cmd,dt_S_dtb) diff -ruw linux-4.14.127/scripts/Makefile.ubsan linux-4.14.127-fbx/scripts/Makefile.ubsan --- linux-4.14.127/scripts/Makefile.ubsan 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/scripts/Makefile.ubsan 2019-03-29 17:33:21.529534915 +0100 @@ -15,10 +15,6 @@ CFLAGS_UBSAN += $(call cc-option, -fsanitize=alignment) endif -ifdef CONFIG_UBSAN_NULL - CFLAGS_UBSAN += $(call cc-option, -fsanitize=null) -endif - # -fsanitize=* options makes GCC less smart than usual and # increase number of 'maybe-uninitialized false-positives CFLAGS_UBSAN += $(call cc-option, -Wno-maybe-uninitialized) diff -ruw linux-4.14.127/scripts/dtc/include-prefixes/arm64/marvell/Makefile linux-4.14.127-fbx/scripts/dtc/include-prefixes/arm64/marvell/Makefile --- linux-4.14.127/scripts/dtc/include-prefixes/arm64/marvell/Makefile 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/scripts/dtc/include-prefixes/arm64/marvell/Makefile 2019-02-15 14:29:36.054632721 +0100 @@ -10,6 +10,15 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-db.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-8080-db.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_exp1_dsl_lte.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_exp2_ftth_p2p.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_exp2_ftth_pon.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_exp1_test_module.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_exp2_test_module.dtb + +# export symbols in DTBs file to allow overlay usage +DTC_FLAGS += -@ always := $(dtb-y) subdir-y := $(dts-dirs) diff -ruw linux-4.14.127/scripts/dtc/include-prefixes/arm64/marvell/armada-3720-db.dts linux-4.14.127-fbx/scripts/dtc/include-prefixes/arm64/marvell/armada-3720-db.dts --- linux-4.14.127/scripts/dtc/include-prefixes/arm64/marvell/armada-3720-db.dts 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/scripts/dtc/include-prefixes/arm64/marvell/armada-3720-db.dts 2019-02-15 14:29:36.054632721 +0100 @@ -94,6 +94,16 @@ 3300000 0x0>; enable-active-high; }; + + vcc_sd_reg2: regulator-vmcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_sd2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpio = <&gpio_exp 4 GPIO_ACTIVE_HIGH>; + }; }; /* Gigabit module on CON19(V2.0)/CON21(V1.4) */ @@ -179,6 +189,7 @@ bus-width = <4>; marvell,pad-type = "sd"; vqmmc-supply = <&vcc_sd_reg1>; + vmmc-supply = <&vcc_sd_reg2>; status = "okay"; }; @@ -216,7 +227,7 @@ /* * Exported on the micro USB connector CON30(V2.0)/CON32(V1.4) through - * an FTDI + * an FTDI (also on CON24(V2.0)/CON26(V1.4)). */ &uart0 { pinctrl-names = "default"; @@ -224,6 +235,13 @@ status = "okay"; }; +/* CON26(V2.0)/CON28(V1.4) */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + /* CON27(V2.0)/CON29(V1.4) */ &usb2 { status = "okay"; diff -ruw linux-4.14.127/scripts/dtc/include-prefixes/arm64/marvell/armada-37xx.dtsi linux-4.14.127-fbx/scripts/dtc/include-prefixes/arm64/marvell/armada-37xx.dtsi --- linux-4.14.127/scripts/dtc/include-prefixes/arm64/marvell/armada-37xx.dtsi 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/scripts/dtc/include-prefixes/arm64/marvell/armada-37xx.dtsi 2019-02-15 14:29:36.054632721 +0100 @@ -55,6 +55,7 @@ aliases { serial0 = &uart0; + serial1 = &uart1; }; cpus { @@ -134,8 +135,24 @@ uart0: serial@12000 { compatible = "marvell,armada-3700-uart"; - reg = <0x12000 0x400>; - interrupts = ; + reg = <0x12000 0x200>; + clocks = <&xtalclk>; + interrupts = + , + , + ; + interrupt-names = "uart-sum", "uart-tx", "uart-rx"; + status = "disabled"; + }; + + uart1: serial@12200 { + compatible = "marvell,armada-3700-uart-ext"; + reg = <0x12200 0x30>; + clocks = <&xtalclk>; + interrupts = + , + ; + interrupt-names = "uart-tx", "uart-rx"; status = "disabled"; }; @@ -183,7 +200,6 @@ , , ; - }; xtalclk: xtal-clk { diff -ruw linux-4.14.127/scripts/dtc/include-prefixes/arm64/marvell/armada-7040-db.dts linux-4.14.127-fbx/scripts/dtc/include-prefixes/arm64/marvell/armada-7040-db.dts --- linux-4.14.127/scripts/dtc/include-prefixes/arm64/marvell/armada-7040-db.dts 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/scripts/dtc/include-prefixes/arm64/marvell/armada-7040-db.dts 2019-02-15 14:29:36.054632721 +0100 @@ -130,6 +130,8 @@ &uart0 { status = "okay"; + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; }; @@ -150,6 +152,36 @@ }; }; +&cpm_nand { + /* + * SPI on CPM and NAND have common pins on this board. We can + * use only one at a time. To enable the NAND (whihch will + * disable the SPI), the "status = "okay";" line have to be + * added here. + */ + num-cs = <1>; + pinctrl-0 = <&nand_pins>, <&nand_rb>; + pinctrl-names = "default"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + + partition@0 { + label = "U-Boot"; + reg = <0 0x200000>; + }; + partition@200000 { + label = "Linux"; + reg = <0x200000 0xe00000>; + }; + partition@1000000 { + label = "Filesystem"; + reg = <0x1000000 0x3f000000>; + }; +}; + + &cpm_spi1 { status = "okay"; @@ -221,10 +253,21 @@ status = "okay"; }; +&cpm_eth0 { + status = "okay"; + /* Network PHY */ + phy-mode = "10gbase-kr"; + /* Generic PHY, providing serdes lanes */ + phys = <&cpm_comphy2 0>; +}; + &cpm_eth1 { status = "okay"; + /* Network PHY */ phy = <&phy0>; phy-mode = "sgmii"; + /* Generic PHY, providing serdes lanes */ + phys = <&cpm_comphy0 1>; }; &cpm_eth2 { diff -ruw linux-4.14.127/scripts/dtc/include-prefixes/arm64/marvell/armada-70x0.dtsi linux-4.14.127-fbx/scripts/dtc/include-prefixes/arm64/marvell/armada-70x0.dtsi --- linux-4.14.127/scripts/dtc/include-prefixes/arm64/marvell/armada-70x0.dtsi 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/scripts/dtc/include-prefixes/arm64/marvell/armada-70x0.dtsi 2019-02-15 14:29:36.054632721 +0100 @@ -64,5 +64,19 @@ &cpm_syscon0 { cpm_pinctrl: pinctrl { compatible = "marvell,armada-7k-pinctrl"; + + nand_pins: nand-pins { + marvell,pins = + "mpp15", "mpp16", "mpp17", "mpp18", + "mpp19", "mpp20", "mpp21", "mpp22", + "mpp23", "mpp24", "mpp25", "mpp26", + "mpp27"; + marvell,function = "dev"; + }; + + nand_rb: nand-rb { + marvell,pins = "mpp13"; + marvell,function = "nf"; + }; }; }; diff -ruw linux-4.14.127/scripts/dtc/include-prefixes/arm64/marvell/armada-8040-db.dts linux-4.14.127-fbx/scripts/dtc/include-prefixes/arm64/marvell/armada-8040-db.dts --- linux-4.14.127/scripts/dtc/include-prefixes/arm64/marvell/armada-8040-db.dts 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/scripts/dtc/include-prefixes/arm64/marvell/armada-8040-db.dts 2019-02-15 14:29:36.054632721 +0100 @@ -146,6 +146,8 @@ /* Accessible over the mini-USB CON9 connector on the main board */ &uart0 { status = "okay"; + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; }; @@ -207,6 +209,11 @@ status = "okay"; }; +&cpm_eth0 { + status = "okay"; + phy-mode = "10gbase-kr"; +}; + &cpm_eth2 { status = "okay"; phy = <&phy1>; @@ -251,6 +258,11 @@ status = "okay"; }; +&cps_eth0 { + status = "okay"; + phy-mode = "10gbase-kr"; +}; + &cps_eth1 { status = "okay"; phy = <&phy0>; diff -ruw linux-4.14.127/scripts/dtc/include-prefixes/arm64/marvell/armada-8040-mcbin.dts linux-4.14.127-fbx/scripts/dtc/include-prefixes/arm64/marvell/armada-8040-mcbin.dts --- linux-4.14.127/scripts/dtc/include-prefixes/arm64/marvell/armada-8040-mcbin.dts 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/scripts/dtc/include-prefixes/arm64/marvell/armada-8040-mcbin.dts 2019-02-15 14:29:36.054632721 +0100 @@ -107,6 +107,8 @@ &uart0 { status = "okay"; + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; }; &ap_sdhci0 { diff -ruw linux-4.14.127/scripts/dtc/include-prefixes/arm64/marvell/armada-ap806.dtsi linux-4.14.127-fbx/scripts/dtc/include-prefixes/arm64/marvell/armada-ap806.dtsi --- linux-4.14.127/scripts/dtc/include-prefixes/arm64/marvell/armada-ap806.dtsi 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/scripts/dtc/include-prefixes/arm64/marvell/armada-ap806.dtsi 2019-07-22 10:44:47.682826276 +0200 @@ -258,6 +258,12 @@ }; + watchdog: watchdog@600000 { + compatible = "arm,sbsa-gwdt"; + reg = <0x610000 0x1000>, <0x600000 0x1000>; + interrupts = ; + }; + ap_sdhci0: sdhci@6e0000 { compatible = "marvell,armada-ap806-sdhci"; reg = <0x6e0000 0x300>; @@ -280,6 +286,11 @@ ap_pinctrl: pinctrl { compatible = "marvell,ap806-pinctrl"; + + uart0_pins: uart0-pins { + marvell,pins = "mpp11", "mpp19"; + marvell,function = "uart0"; + }; }; ap_gpio: gpio@1040 { @@ -291,6 +302,11 @@ gpio-ranges = <&ap_pinctrl 0 0 20>; }; }; + + ap_hwmon: ap806-hwmon@6f8084 { + compatible = "marvell,ap806-hwmon"; + reg = <0x6f8084 0xc>; + }; }; }; }; diff -ruw linux-4.14.127/scripts/dtc/include-prefixes/arm64/marvell/armada-cp110-master.dtsi linux-4.14.127-fbx/scripts/dtc/include-prefixes/arm64/marvell/armada-cp110-master.dtsi --- linux-4.14.127/scripts/dtc/include-prefixes/arm64/marvell/armada-cp110-master.dtsi 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/scripts/dtc/include-prefixes/arm64/marvell/armada-cp110-master.dtsi 2019-02-15 14:29:36.054632721 +0100 @@ -76,9 +76,10 @@ , , , - ; + , + ; interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", - "tx-cpu3", "rx-shared"; + "tx-cpu3", "rx-shared", "link"; port-id = <0>; gop-port-id = <0>; status = "disabled"; @@ -89,9 +90,10 @@ , , , - ; + , + ; interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", - "tx-cpu3", "rx-shared"; + "tx-cpu3", "rx-shared", "link"; port-id = <1>; gop-port-id = <2>; status = "disabled"; @@ -102,9 +104,10 @@ , , , - ; + , + ; interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", - "tx-cpu3", "rx-shared"; + "tx-cpu3", "rx-shared", "link"; port-id = <2>; gop-port-id = <3>; status = "disabled"; @@ -117,6 +120,11 @@ marvell,system-controller = <&cpm_syscon0>; #address-cells = <1>; #size-cells = <0>; + marvell,cp_mgmt = <&cpm_mgmt>; + marvell,sar = <&cpm_mgmt>; + + clocks = <&cpm_clk 1 9>, <&cpm_clk 1 5>; + clock-names = "gop_clk", "mg_clk"; cpm_comphy0: phy@0 { reg = <0>; @@ -175,6 +183,11 @@ msi-parent = <&gicp>; }; + cpm_mgmt: system-controller@400000 { + compatible = "syscon", "simple-mfd"; + reg = <0x400000 0x300>; + }; + cpm_rtc: rtc@284000 { compatible = "marvell,armada-8k-rtc"; reg = <0x284000 0x20>, <0x284080 0x24>; @@ -184,7 +197,7 @@ cpm_syscon0: system-controller@440000 { compatible = "syscon", "simple-mfd"; - reg = <0x440000 0x1000>; + reg = <0x440000 0x2000>; cpm_clk: clock { compatible = "marvell,cp110-clock"; @@ -243,12 +256,55 @@ }; cpm_sata0: sata@540000 { + #size-cells = <0>; + #address-cells = <1>; compatible = "marvell,armada-8k-ahci", "generic-ahci"; reg = <0x540000 0x30000>; interrupts = ; clocks = <&cpm_clk 1 15>; status = "disabled"; + comreset_u = <0x17>; + comwake = <0x6>; + dma-coherent; + }; + + cpm_uart0: uart@702000 { + compatible = "snps,dw-apb-uart"; + reg = <0x702000 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + status = "disabled"; + clock-frequency = <(250 * 1000 * 1000)>; + }; + + cpm_uart1: uart@702100 { + compatible = "snps,dw-apb-uart"; + reg = <0x702100 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + status = "disabled"; + clock-frequency = <(250 * 1000 * 1000)>; + }; + + cpm_uart2: uart@702200 { + compatible = "snps,dw-apb-uart"; + reg = <0x702200 0x200>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + status = "disabled"; + clock-frequency = <(250 * 1000 * 1000)>; + }; + + cpm_utmi: utmi@580000 { + compatible = "marvell,cp110-utmi-phy"; + #phy-cells = <1>; + reg = <0x580000 0x2000>; + reg-names = "utmi-unit"; + marvell,system-controller = <&cpm_syscon0>; }; cpm_xor0: xor@6a0000 { @@ -289,6 +345,11 @@ status = "disabled"; }; + cpm_hwmon: cp110-hwmon@0x400070 { + compatible = "marvell,cp110-hwmon"; + reg = <0x400070 0xc>; + }; + cpm_i2c0: i2c@701000 { compatible = "marvell,mv78230-i2c"; reg = <0x701000 0x20>; @@ -309,24 +370,36 @@ status = "disabled"; }; + cpm_mss_i2c: i2c@211000 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x211000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&cpm_clk 1 21>; + status = "disabled"; + }; + cpm_nand: nand@720000 { /* * Due to the limiation of the pin available * this controller is only usable on the CPM * for A7K and on the CPS for A8K. */ - compatible = "marvell,armada370-nand"; + compatible = "marvell,armada-8k-nand", + "marvell,armada370-nand"; reg = <0x720000 0x54>; #address-cells = <1>; #size-cells = <1>; interrupts = ; clocks = <&cpm_clk 1 2>; + marvell,system-controller = <&cpm_syscon0>; status = "disabled"; }; cpm_trng: trng@760000 { - compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76"; - reg = <0x760000 0x7d>; + compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip150"; + reg = <0x760000 0x10000>; interrupts = ; clocks = <&cpm_clk 1 25>; status = "okay"; diff -ruw linux-4.14.127/scripts/dtc/include-prefixes/arm64/marvell/armada-cp110-slave.dtsi linux-4.14.127-fbx/scripts/dtc/include-prefixes/arm64/marvell/armada-cp110-slave.dtsi --- linux-4.14.127/scripts/dtc/include-prefixes/arm64/marvell/armada-cp110-slave.dtsi 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/scripts/dtc/include-prefixes/arm64/marvell/armada-cp110-slave.dtsi 2019-02-15 14:29:36.054632721 +0100 @@ -76,9 +76,10 @@ , , , - ; + , + ; interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", - "tx-cpu3", "rx-shared"; + "tx-cpu3", "rx-shared", "link"; port-id = <0>; gop-port-id = <0>; status = "disabled"; @@ -89,9 +90,10 @@ , , , - ; + , + ; interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", - "tx-cpu3", "rx-shared"; + "tx-cpu3", "rx-shared", "link"; port-id = <1>; gop-port-id = <2>; status = "disabled"; @@ -102,9 +104,10 @@ , , , - ; + , + ; interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2", - "tx-cpu3", "rx-shared"; + "tx-cpu3", "rx-shared", "link"; port-id = <2>; gop-port-id = <3>; status = "disabled"; @@ -118,6 +121,13 @@ #address-cells = <1>; #size-cells = <0>; + marvell,cp_mgmt = <&cps_mgmt>; + /* always use Master CP S@R */ + marvell,sar = <&cpm_mgmt>; + + clocks = <&cps_clk 1 9>, <&cps_clk 1 5>; + clock-names = "gop_clk", "mg_clk"; + cps_comphy0: phy@0 { reg = <0>; #phy-cells = <1>; @@ -175,6 +185,11 @@ msi-parent = <&gicp>; }; + cps_mgmt: system-controller@400000 { + compatible = "syscon", "simple-mfd"; + reg = <0x400000 0x300>; + }; + cps_rtc: rtc@284000 { compatible = "marvell,armada-8k-rtc"; reg = <0x284000 0x20>, <0x284080 0x24>; @@ -184,11 +199,12 @@ cps_syscon0: system-controller@440000 { compatible = "syscon", "simple-mfd"; - reg = <0x440000 0x1000>; + reg = <0x440000 0x2000>; cps_clk: clock { compatible = "marvell,cp110-clock"; #clock-cells = <2>; + fbx,ignore-eip150; }; cps_gpio1: gpio@100 { @@ -244,12 +260,55 @@ }; cps_sata0: sata@540000 { + #size-cells = <0>; + #address-cells = <1>; compatible = "marvell,armada-8k-ahci", "generic-ahci"; reg = <0x540000 0x30000>; interrupts = ; clocks = <&cps_clk 1 15>; status = "disabled"; + comreset_u = <0x17>; + comwake = <0x6>; + dma-coherent; + }; + + cps_uart0: uart@702000 { + compatible = "snps,dw-apb-uart"; + reg = <0x702000 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + status = "disabled"; + clock-frequency = <(250 * 1000 * 1000)>; + }; + + cps_uart1: uart@702100 { + compatible = "snps,dw-apb-uart"; + reg = <0x702100 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + status = "disabled"; + clock-frequency = <(250 * 1000 * 1000)>; + }; + + cps_uart2: uart@702200 { + compatible = "snps,dw-apb-uart"; + reg = <0x702200 0x200>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + status = "disabled"; + clock-frequency = <(250 * 1000 * 1000)>; + }; + + cps_utmi: utmi@580000 { + compatible = "marvell,cp110-utmi-phy"; + #phy-cells = <1>; + reg = <0x580000 0x2000>; + reg-names = "utmi-unit"; + marvell,system-controller = <&cps_syscon0>; }; cps_xor0: xor@6a0000 { @@ -290,6 +349,11 @@ status = "disabled"; }; + cps_hwmon: cp110-hwmon@0x400070 { + compatible = "marvell,cp110-hwmon"; + reg = <0x400070 0xc>; + }; + cps_i2c0: i2c@701000 { compatible = "marvell,mv78230-i2c"; reg = <0x701000 0x20>; @@ -310,13 +374,24 @@ status = "disabled"; }; + cps_mss_i2c: i2c@211000 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x211000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&cps_clk 1 21>; + status = "disabled"; + }; + cps_nand: nand@720000 { /* * Due to the limiation of the pin available * this controller is only usable on the CPM * for A7K and on the CPS for A8K. */ - compatible = "marvell,armada370-nand"; + compatible = "marvell,armada370-nand", + "marvell,armada370-nand"; reg = <0x720000 0x54>; #address-cells = <1>; #size-cells = <1>; @@ -326,8 +401,8 @@ }; cps_trng: trng@760000 { - compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76"; - reg = <0x760000 0x7d>; + compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip150"; + reg = <0x760000 0x10000>; interrupts = ; clocks = <&cps_clk 1 25>; status = "okay"; @@ -355,6 +430,19 @@ */ status = "disabled"; }; + + cps_tdm0: tdmmc@7a0000 { + compatible = "marvell,armada-a8k-tdm"; + reg = <0x7a0000 0x20000>, + <0x440400 0x20>; + reg-names = "tdm_regs", "pll_regs"; + interrupts = , + , + ; + clocks = <&cps_clk 1 1>; + clock-names = "gateclk"; + status = "disabled"; + }; }; cps_pcie0: pcie@f4600000 { diff -ruw linux-4.14.127/sound/soc/kirkwood/Kconfig linux-4.14.127-fbx/sound/soc/kirkwood/Kconfig --- linux-4.14.127/sound/soc/kirkwood/Kconfig 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/sound/soc/kirkwood/Kconfig 2019-02-15 14:29:46.066672402 +0100 @@ -16,3 +16,8 @@ Say Y if you want to add support for SoC audio on the Armada 370 Development Board. +config SND_KIRKWOOD_SOC_FBXGW2R + tristate "Soc Audio support for fbxgw2r" + depends on SND_KIRKWOOD_SOC && MACH_FBXGW2R && I2C + select SND_KIRKWOOD_SOC_I2S + select SND_SOC_CS42L52 diff -ruw linux-4.14.127/sound/soc/kirkwood/Makefile linux-4.14.127-fbx/sound/soc/kirkwood/Makefile --- linux-4.14.127/sound/soc/kirkwood/Makefile 2019-06-17 19:52:45.000000000 +0200 +++ linux-4.14.127-fbx/sound/soc/kirkwood/Makefile 2019-02-15 14:29:46.066672402 +0100 @@ -5,3 +5,6 @@ snd-soc-armada-370-db-objs := armada-370-db.o obj-$(CONFIG_SND_KIRKWOOD_SOC_ARMADA370_DB) += snd-soc-armada-370-db.o + +snd-soc-fbxgw2r-objs := kirkwood-fbxgw2r.o +obj-$(CONFIG_SND_KIRKWOOD_SOC_FBXGW2R) += snd-soc-fbxgw2r.o --- /dev/null 2019-09-30 09:50:43.919599165 +0200 +++ linux-4.14.127-fbx/arch/arm64/boot/dts/marvell/fbxgw7r.dts 2019-07-22 10:44:47.682826276 +0200 @@ -0,0 +1,887 @@ +#include +#include + +#include "armada-8040.dtsi" + +/ { + model = "Freebox V7R Board"; + compatible = "freebox,fbxgw7r", "marvell,armada8040", + "marvell,armada-ap806-quad", "marvell,armada-ap806"; + + chosen { + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ramoops@3fff8000 { + compatible = "ramoops"; + /* RAM top - 32k */ + reg = <0x0 0x3fff8000 0x0 (32 * 1024)>; + record-size = <(32 * 1024)>; + ecc-size = <16>; + no-dump-oops; + }; + }; + + memory@00000000 { + device_type = "memory"; + // hopefully patched by ATF. + reg = <0x0 0x0 0x0 0x0>; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + fbx7r-fbxgpio { + compatible = "fbx,fbxgpio"; + + lan-sfp-txdis { + gpio = <&cpm_gpio2 22 0>; + output-high; + }; + lan-sfp-txfault { + gpio = <&cpm_gpio2 21 0>; + input; + }; + lan-sfp-pwren { + gpio = <&io_expander1 7 0>; + output-low; + }; + lan-sfp-presence { + gpio = <&cps_gpio1 27 0>; + input; + }; + lan-sfp-pwrgood { + gpio = <&cps_gpio1 10 0>; + input; + }; + lan-sfp-rxlos { + gpio = <&cps_gpio1 28 0>; + input; + }; + + sata0-pwren { + gpio = <&io_expander0 13 0>; + output-low; + }; + sata1-pwren { + gpio = <&io_expander0 14 0>; + output-low; + }; + sata0-pwrfault { + gpio = <&io_expander0 11 0>; + input; + }; + sata1-pwrfault { + gpio = <&io_expander0 12 0>; + input; + }; + + sata2-pwren { + gpio = <&io_expander1 11 0>; + output-low; + }; + sata3-pwren { + gpio = <&io_expander1 10 0>; + output-low; + }; + sata2-pwrfault { + gpio = <&io_expander1 5 0>; + input; + }; + sata3-pwrfault { + gpio = <&io_expander1 4 0>; + input; + }; + + usbhub2-rst { + gpio = <&io_expander0 15 0>; + output-low; + }; + usbhub3-rst { + gpio = <&io_expander1 6 0>; + output-low; + }; + + mpcie0-rst { + /* WiFi 5.0Ghz */ + gpio = <&io_expander0 8 0>; + output-low; + no-claim; + }; + mpcie1-rst { + /* WiFI 2.4 Ghz */ + gpio = <&io_expander1 15 0>; + output-low; + no-claim; + }; + mpcie2-rst { + /* WiFi Listen */ + gpio = <&io_expander1 9 0>; + output-low; + no-claim; + }; + + ha-rst { + gpio = <&cps_gpio1 25 0 >; + output-low; + }; + + sw-int { + gpio = <&cpm_gpio2 1 0>; + input; + }; + sw-reset { + gpio = <&io_expander0 0 0>; + output-high; + no-claim; + }; + phy-int { + gpio = <&cpm_gpio2 20 0>; + input; + }; + phy-reset { + gpio = <&io_expander0 1 0>; + output-high; + }; + + dect_jtag_tck: dect-jtag-tck { + gpio = <&cps_gpio1 20 0>; + output-low; + }; + dect_jtag_tdi: dect-jtag-tdi { + gpio = <&cps_gpio1 17 0>; + output-low; + }; + dect_jtag_tdo: dect-jtag-tdo { + gpio = <&cps_gpio1 18 0>; + input; + }; + dect_jtag_tms: dect-jtag-tms { + gpio = <&cps_gpio1 26 0>; + output-low; + }; + dect-reset { + gpio = <&cps_gpio1 4 0>; + output-low; + }; + + exp1-rst0 { + gpio = <&io_expander0 2 0>; + output-low; + }; + exp1-rst1 { + gpio = <&io_expander0 3 0>; + output-high; + }; + exp1-3v3-en { + gpio = <&io_expander0 6 0>; + output-low; + }; + exp1-20v-pwren { + gpio = <&io_expander0 5 0>; + output-low; + }; + + exp2-rst0 { + gpio = <&io_expander1 3 0>; + output-low; + }; + exp2-rst1 { + gpio = <&io_expander1 1 0>; + output-high; + }; + exp2-3v3-en { + gpio = <&io_expander1 2 0>; + output-low; + }; + exp2-20v-pwren { + gpio = <&io_expander1 8 0>; + output-low; + }; + + + boot-eth { + gpio = <&cpm_gpio2 29 0>; + input; + }; + }; + + /* + * I2C mux isolating LAN SFP, both expansion boards + * Expansion boards branches from each other. + */ + i2c_bigmux { + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + mux-gpios = <&cps_gpio1 24 0>, /* lan-sfp-i2c-en */ + <&io_expander1 12 0>, /* exp2-i2c-en */ + <&io_expander1 13 0>; /* exp1-i2c-en */ + idle-state = <0x0>; + i2c-parent = <&misc_i2c>; + + lan_sfp_i2c: i2c@1 { + reg = <0x1>; + }; + + exp2_ext_i2c: i2c@2 { + reg = <0x2>; + }; + + exp1_ext_i2c: i2c@4 { + reg = <0x4>; + }; + }; + + jtag_dect { + compatible = "fbx,fbxjtag"; + + clock-delay = <500>; + wait-tms = <0>; + data-read-size = <128>; + inst-read-size = <128>; + + fbxgpio-tck = <&dect_jtag_tck>; + fbxgpio-tdo = <&dect_jtag_tdo>; + fbxgpio-tdi = <&dect_jtag_tdi>; + fbxgpio-tms = <&dect_jtag_tms>; + }; + + cpm_i2c1_gpio: cpm_i2c1_gpio { + /* aka I2C #1, A8K I2C bus CPM_I2C1 */ + compatible = "i2c-gpio"; + gpios = <&cpm_gpio2 3 0 /* sda */ + &cpm_gpio2 4 0 /* scl */ + >; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + + spd@0x53 { + /* SPD eeprom */ + compatible = "at24,ee1004"; + reg = <0x53>; + }; + }; + + misc_i2c: cps_mss_i2c { + /* aka I2C #2, A8K I2C bus CP1_MSS_I2C */ + compatible = "i2c-gpio"; + gpios = <&cps_gpio1 29 0 /* sda */ + &cps_gpio1 30 0 /* scl */ + >; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + }; + + aliases { + /* console */ + serial0 = &uart0; + /* DECT */ + serial1 = &cpm_uart0; + /* EXP2 */ + serial2 = &cpm_uart1; + /* EXP1 */ + serial3 = &cpm_uart2; + /* BT */ + serial4 = &cps_uart0; + /* HA */ + serial5 = &cps_uart2; + + i2c0 = &cpm_i2c0; + i2c1 = &cpm_i2c1_gpio; + i2c2 = &misc_i2c; + i2c3 = &lan_sfp_i2c; + i2c4 = &exp2_ext_i2c; + i2c5 = &exp1_ext_i2c; + i2c6 = &cpm_mss_i2c; + }; + +}; + +&cps_gpio1 { + gpio-line-names = "", /* 0 */ + "", /* 1 */ + "", /* 2 */ + "", /* 3 */ + "tdm-rst", /* 4 */ + "", /* 5 */ + "", /* 6 */ + "", /* 7 */ + "", /* 8 */ + "nfc-int", /* 9 */ + "lan-sfp-pwrfault", /* 10 */ + "", /* 11 */ + "", /* 12 */ + "", /* 13 */ + "", /* 14 */ + "", /* 15 */ + "", /* 16 */ + "dect-jtag-tdi", /* 17 */ + "dect-jtag-tdo", /* 18 */ + "ha-swd", /* 19 */ + "dect-jtag-tck", /* 20 */ + "display-swc", /* 21 */ + "", /* 22 */ + "display-swd", /* 23 */ + "lan-sfp-i2c-en", /* 24 */ + "ha-reset", /* 25 */ + "dect-jtag-tms", /* 26 */ + "lan-sfp-presence", /* 27 */ + "lan-sfp-rxlos", /* 28 */ + "", /* 29 */ + "", /* 30 */ + "exp1-3v3-pwrfault"; /* 31 */ +}; + +&cpm_gpio2 { + /* starts at offset 32 in cp110-master */ + + gpio-line-names = "exp2-3v3-pwrfault", /* 0 */ + "sw-int", /* 1 */ + "keypad-int", /* 2 */ + "", /* 3 */ + "", /* 4 */ + "", /* 5 */ + "", /* 6 */ + "", /* 7 */ + "", /* 8 */ + "", /* 9 */ + "", /* 10 */ + "", /* 11 */ + "ha-swc", /* 12 */ + "", /* 13 */ + "keypad-rst", /* 14 */ + "", /* 15 */ + "io-expander-reset", /* 16 */ + "", /* 17 */ + "", /* 18 */ + "", /* 19 */ + "phy-int", /* 20 */ + "lan-sfp-txfault", /* 21 */ + "lan-sfp-txdisable", /* 22 */ + "sdr-event", /* 23 */ + "fan-alert-int", /* 24 */ + "", /* 25 */ + "", /* 26 */ + "", /* 27 */ + "", /* 28 */ + "boot-eth", /* 29 */ + ""; /* 30 */ +}; + +&uart0 { + status = "okay"; +}; + +&ap_sdhci0 { + status = "okay"; + bus-width = <8>; + non-removable; + + partitions-main { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + disk-name = "mmcblk%d"; + + bank0@0 { + label = "bank0"; + reg = /bits/64 <0 (32 * 1024 * 1024)>; + read-only; + }; + + bank1@0 { + label = "bank1"; + reg = /bits/64 <(-1) (256 * 1024 * 1024)>; + }; + + nvram@0 { + label = "nvram"; + reg = /bits/64 <(-1) (4 * 1024 * 1024)>; + }; + + config@0 { + label = "config"; + reg = /bits/64 <(-1) (32 * 1024 * 1024)>; + }; + + new-bank0@0 { + label = "new_bank0"; + reg = /bits/64 <(-1) (32 * 1024 * 1024)>; + }; + + fbxmbr@0 { + label = "fbxmbr"; + reg = /bits/64 <(-1) (4096)>; + }; + + fortknox@0 { + label = "fortknox"; + reg = /bits/64 <(-1) (128 * 1024 * 1024)>; + }; + + userdata@0 { + label = "userdata"; + reg = /bits/64 <(-1) (-1)>; + }; + }; + + partitions-boot { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + disk-name = "mmcblk%dboot0"; + + ipl@0 { + label = "ipl"; + reg = /bits/64 <0 (1 * 1024 * 1024)>; + read-only; + }; + + serial@0 { + label = "fbxserial"; + reg = /bits/64 <(-1) (8 * 1024)>; + read-only; + }; + + randomdata@0 { + label = "randomdata"; + reg = /bits/64 <(-1) (8 * 1024)>; + read-only; + }; + + calibration@0 { + label = "calibration"; + reg = /bits/64 <(-1) (64 * 1024)>; + read-only; + }; + + field-calibration@0 { + label = "field_calibration"; + reg = /bits/64 <(-1) (64 * 1024)>; + }; + }; + + partitions-boot1 { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + disk-name = "mmcblk%dboot1"; + + backup-ipl@0 { + label = "backup-ipl"; + reg = /bits/64 <0 (1 * 1024 * 1024)>; + read-only; + }; + }; +}; + +&ap_hwmon { + status = "okay"; + fbx,requires-smc; +}; + +&cpm_hwmon { + status = "okay"; +}; + +&cps_hwmon { + status = "okay"; + fbx,requires-smc; +}; + +&cpm_i2c0 { + status = "okay"; + pinctrl-names = "default"; + + adt7475@2e { + compatible = "adi,adt7475"; + reg = <0x2e>; + }; + + io_expander0: exp0@74 { + compatible = "nxp,pca9539"; + reg = <0x74>; + gpio-controller; + ngpios = <16>; + #gpio-cells = <2>; + gpio-line-names = "sw-rst", /* 0 */ + "phy-rst", /* 1 */ + "exp1-rst1", /* 2 */ + "exp1-rst2", /* 3 */ + "exp1-presence", /* 4 */ + "exp1-20v-pwren", /* 5 */ + "exp1-3v3-pwren", /* 6 */ + "", /* 7 */ + "pcie0-rst", /* 8 */ + "nfc-en", /* 9 */ + "type-c-i2c-en", /* 10 */ + "sata0-pwrfault", /* 11 */ + "sata1-pwrfault", /* 12 */ + "sata0-pwren", /* 13 */ + "sata1-pwren", /* 14 */ + "usbhub2-rst"; /* 15 */ + }; + + io_expander1: exp1@75 { + compatible = "nxp,pca9539"; + reg = <0x75>; + gpio-controller; + gpiobase = <300>; + ngpios = <16>; + #gpio-cells = <2>; + gpio-line-names = "exp2-presence", /* 0 */ + "exp2-rst1", /* 1 */ + "exp2-3v3-en", /* 2 */ + "exp2-rst0", /* 3 */ + "sata3-pwrfault", /* 4 */ + "sata2-pwrfault", /* 5 */ + "usbhub3-rst", /* 6 */ + "lan-sfp-pwren", /* 7 */ + "exp2-20v-pwren", /* 8 */ + "pcie2-rst", /* 9 */ + "sata3-pwren", /* 10 */ + "sata2-pwren", /* 11 */ + "exp2-i2c-en", /* 12 */ + "exp1-i2c-en", /* 13 */ + "pcie1-bt-rst", /* 14 */ + "pcie1-rst"; /* 15 */ + }; +}; + +&cpm_mss_i2c { + status = "okay"; + pinctrl-0 = <&cpm_mss_i2c_pins>; + pinctrl-names = "default"; +}; + +&cpm_ethernet { + status = "okay"; +}; + +&cpm_mdio { + status = "okay"; + + mv6141: mv6141@16 { + compatible = "freebox,fbxgw7r-mv6141"; + reg = <0>; + gpio-reset = <&io_expander0 0 0>; + }; +}; + + +/* + * Internal port to midplane for "EXP2" expansion connector. Can + * operate in 10GBase-KR. + */ +&cpm_comphy2 { + kr-gen1-s0-amplitude = <0x12>; + kr-gen1-s0-emphasis = <0x8>; + kr-gen1-s2-emphasis = <0x2>; + + kr-ffe-cap-sel = <0xe>; + kr-ffe-res-sel = <0x6>; + kr-ffe-dfe-res = <0x1>; + kr-phase-offset = <0x60>; +}; +&cpm_eth0 { + status = "okay"; + phys = <&cpm_comphy2 0>; + phy-mode = "1000base-x"; + mac-address = [00 07 cb 00 00 fd]; +}; + +/* + * Switch uplink port in 2500Base-X. + */ +&cpm_eth2 { + status = "okay"; + phy-mode = "1000base-x"; + phys = <&cpm_comphy5 2>; + fbxserial-mac-address = <0>; + mdio-bus = <&cpm_mdio>; +}; + +&cps_ethernet { + status = "okay"; +}; + +/* + * 10G Lan port (SFP) + */ +&cps_comphy4 { + kr-gen1-s0-amplitude = <0x12>; + kr-gen1-s0-emphasis = <0x4>; + kr-gen1-s2-emphasis = <0x0>; +}; + +&cps_eth0 { + status = "okay"; + phys = <&cps_comphy4 0>; + phy-mode = "10gbase-kr"; + fbxserial-mac-address = <1>; +}; + +/* + * Internal port to midplane for "EXP1" expansion connector. 1000BaseX + * only, not 10G capapable + */ +&cps_eth2 { + status = "okay"; + phys = <&cps_comphy5 2>; + phy-mode = "1000base-x"; + mac-address = [00 07 cb 00 00 fd]; +}; + +&cpm_comphy1 { + sata-gen3-s0-amplitude = <0x15>; + sata-gen3-s0-emphasis = <0x7>; + sata-gen3-s4-dfe-res = <0x1>; + sata-phase-offset = <0x61>; +}; + +&cpm_comphy3 { + sata-gen3-s0-amplitude = <0x15>; + sata-gen3-s0-emphasis = <0x5>; + sata-gen3-s4-dfe-res = <0x1>; + sata-phase-offset = <0x61>; +}; + +&cpm_sata0 { + status = "okay"; + comreset_u = <0x17>; + comwake = <0x6>; + + sata-port@0 { + status = "okay"; + reg = <0>; + phys = <&cpm_comphy1 0>; + }; + sata-port@1 { + status = "okay"; + reg = <1>; + phys = <&cpm_comphy3 1>; + }; +}; + +&cps_comphy2 { + sata-gen3-s0-amplitude = <0x14>; + sata-gen3-s0-emphasis = <0x5>; + sata-gen3-s4-dfe-res = <0x1>; + sata-phase-offset = <0x61>; +}; + +&cps_comphy3 { + sata-gen3-s0-amplitude = <0x14>; + sata-gen3-s0-emphasis = <0x5>; + sata-gen3-s4-dfe-res = <0x1>; + sata-phase-offset = <0x61>; +}; + +&cps_sata0 { + status = "okay"; + comreset_u = <0x17>; + comwake = <0x6>; + + sata-port@1 { + status = "okay"; + reg = <1>; + phys = <&cps_comphy3 1>; + }; + sata-port@0 { + status = "okay"; + reg = <0>; + phys = <&cps_comphy2 0>; + }; +}; + +&cpm_usb3_1 { + status = "okay"; + + phys = <&cpm_utmi 0>; + phy-names = "usb2"; +}; + +&cps_usb3_0 { + status = "okay"; + + phys = <&cps_comphy1 0>, + <&cps_utmi 0>; + phy-names = "usb3", "usb2"; +}; + +&cpm_pcie0 { + /* + * WiFi 5.0Ghz + */ + status = "okay"; + num-lanes = <1>; + + phys = <&cpm_comphy0 0>; + phy-names = "lane0"; + + reset-gpios = <&io_expander0 8 0>; +}; + +&cpm_pcie1 { + /* + * WiFi Listen + */ + status = "okay"; + num-lanes = <1>; + + phys = <&cpm_comphy4 1>; + phy-names = "lane0"; + + reset-gpio = <&io_expander1 9 0>; +}; + +&cps_pcie0 { + /* + * WiFi 2.4 Ghz + */ + status = "okay"; + num-lanes = <1>; + + phys = <&cps_comphy0 0>; + phy-names = "lane0"; + reset-gpio = <&io_expander1 15 0>, <&io_expander1 14 0>; +}; + +&cpm_spi0 { + status = "okay"; + pinctrl-0 = <&cpm_spi0_pins>; + pinctrl-names = "default"; + + spi-slac@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "microsemi,le9641"; + reg = <0>; + spi-max-frequency = <5000000>; + }; + + spi-panel@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "freebox,fbxgw7r-panel"; + reg = <1>; + spi-max-frequency = <(750 * 1000)>; + irq-gpio = <&cpm_gpio2 2 0>; + }; +}; + +&cps_spi1 { + status = "okay"; + pinctrl-0 = <&cps_spi1_pins>; + pinctrl-names = "default"; +}; + +&cpm_pinctrl { + /* DECT */ + cpm_uart0_pins: uart0-pins-0 { + marvell,pins = "mpp45", "mpp62"; + marvell,function = "uart0"; + }; + /* EXP2 */ + cpm_uart1_pins: uart1-pins-0 { + marvell,pins = "mpp59", "mpp60"; + marvell,function = "uart1"; + }; + /* EXP1 */ + cpm_uart2_pins: uart2-pins-0 { + marvell,pins = "mpp50", "mpp51"; + marvell,function = "uart2"; + }; + /* SPI SLAC */ + cpm_spi0_pins: spi0-pins-0 { + marvell,pins = "mpp39", "mpp40", "mpp41", "mpp42", "mpp43"; + marvell,function = "spi0"; + }; + cpm_mss_i2c_pins: mss-i2c-pins-0 { + marvell,pins = "mpp57", "mpp58"; + marvell,function = "mss_i2c"; + }; +}; + +&cps_pinctrl { + cps_mss_i2c_pins: mss-i2c-pins-0 { + marvell,pins = "mpp29", "mpp30"; + marvell,function = "mss_i2c"; + }; + cps_spi1_pins: spi1-pins-0 { + marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16"; + marvell,function = "spi1"; + }; + cps_tdm0_pins: tdm0-pins-0 { + marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", "mpp5"; + marvell,function = "tdm"; + }; + /* BT */ + cps_uart0_pins: uart0-pins-0 { + marvell,pins = "mpp6", "mpp7"; + marvell,function = "uart0"; + }; + /* HA */ + cps_uart2_pins: uart2-pins-0 { + marvell,pins = "mpp8", "mpp11"; + marvell,function = "uart2"; + }; +}; + +/* DECT */ +&cpm_uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cpm_uart0_pins>; +}; + +/* EXP2 */ +&cpm_uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cpm_uart1_pins>; +}; + +/* EXP1 */ +&cpm_uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cpm_uart2_pins>; +}; + +&cps_tdm0 { + pinctrl-names = "default"; + pinctrl-0 = <&cps_tdm0_pins>; + status = "okay"; + pclk-freq-mhz = <2>; +}; + +/* BT */ +&cps_uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cps_uart0_pins>; +}; + +/* HA */ +&cps_uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cps_uart2_pins>; +}; + +&cps_trng { + /* secure TRNG on fbxgw7r */ + status = "foutu"; +}; --- /dev/null 2019-09-30 09:50:43.919599165 +0200 +++ linux-4.14.127-fbx/arch/arm64/boot/dts/marvell/fbxgw7r_exp1_dsl_lte.dts 2019-02-15 14:29:36.054632721 +0100 @@ -0,0 +1,33 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "freebox,fbxgw7r"; + + fragment@0 { + target-path="/"; + __overlay__ { + fbxatm-remote@0 { + compatible = "freebox,fbxatm-remote"; + mac-address = [00 07 cb 00 00 fe]; + netdev-name = "bcmfbxatm0"; + remote-name = "bcm63xx_fbxxtm0"; + }; + }; + }; + + fragment@1 { + target = <&cps_spi1>; + __overlay__ { + #address-cells = <0x1>; + #size-cells = <0x0>; + + exp1-flash@1 { + compatible = "m25p80"; + reg = <1>; + spi-max-frequency = <(1 * 1000 * 1000)>; + label = "exp1-spi-flash"; + }; + }; + }; +}; --- /dev/null 2019-09-30 09:50:43.919599165 +0200 +++ linux-4.14.127-fbx/arch/arm64/boot/dts/marvell/fbxgw7r_exp1_test_module.dts 2019-02-15 14:29:36.054632721 +0100 @@ -0,0 +1,97 @@ +#include + +/dts-v1/; +/plugin/; + +/ { + compatible = "freebox,fbxgw7r"; + + fragment@0 { + target = <&exp1_ext_i2c>; + __overlay__ { + #address-cells = <0x1>; + #size-cells = <0x0>; + + exp1_gpio_extender: exp1@74 { + compatible = "nxp,pca9539"; + reg = <0x74>; + gpio-controller; + ngpios = <16>; + #gpio-cells = <2>; + gpio-line-names = "sfp-pwren", /* 0 */ + "sfp-pwrgood", /* 1 */ + "sfp-txfault", /* 2 */ + "sfp-txdisable", /* 3 */ + "sfp-presence", /* 4 */ + "sfp-rxlos", /* 5 */ + "sfp-led", /* 6 */ + "sfp-i2cen", /* 7 */ + "", /* 8 */ + "", /* 9 */ + "", /* 10 */ + "", /* 11 */ + "", /* 12 */ + "", /* 13 */ + "", /* 14 */ + ""; /* 15 */ + }; + }; + }; + + fragment@1 { + target-path="/"; + __overlay__ { + exp1-test-module-fbxgpio { + compatible = "fbx,fbxgpio"; + exp1-test-module-sfp-pwren { + gpio = <&exp1_gpio_extender 0 0>; + output-low; + }; + exp1-test-module-sfp-pwrgood { + gpio = <&exp1_gpio_extender 1 0>; + input; + }; + exp1-test-module-sfp-txfault { + gpio = <&exp1_gpio_extender 2 0>; + input; + }; + exp1-test-module-sfp-txdis { + gpio = <&exp1_gpio_extender 3 0>; + output-high; + }; + exp1-test-module-sfp-presence { + gpio = <&exp1_gpio_extender 4 0>; + input; + }; + exp1-test-module-sfp-rxlos { + gpio = <&exp1_gpio_extender 5 0>; + input; + }; + exp1-test-module-sfp-link-led { + gpio = <&exp1_gpio_extender 6 GPIO_ACTIVE_LOW>; + output-low; + }; + exp1-test-module-sfp-i2cen { + gpio = <&exp1_gpio_extender 7 0>; + /* enable it by default, revisit later */ + output-high; + }; + }; + }; + }; + + fragment@2 { + target = <&cps_spi1>; + __overlay__ { + #address-cells = <0x1>; + #size-cells = <0x0>; + + exp1-flash@1 { + compatible = "m25p80"; + reg = <1>; + spi-max-frequency = <(1 * 1000 * 1000)>; + label = "exp1-spi-flash"; + }; + }; + }; +}; --- /dev/null 2019-09-30 09:50:43.919599165 +0200 +++ linux-4.14.127-fbx/arch/arm64/boot/dts/marvell/fbxgw7r_exp2_ftth_p2p.dts 2019-02-15 14:29:36.054632721 +0100 @@ -0,0 +1,118 @@ +#include + +/dts-v1/; +/plugin/; + +/ { + compatible = "freebox,fbxgw7r"; + + fragment@0 { + target = <&exp2_ext_i2c>; + __overlay__ { + #address-cells = <0x1>; + #size-cells = <0x0>; + + // IO expander found only on P2P Fiber + // expansion board. + exp2_gpio_extender: exp2@74 { + compatible = "nxp,pca9539"; + reg = <0x74>; + gpio-controller; + ngpios = <16>; + #gpio-cells = <2>; + gpio-line-names = "wan-sfp-pwren", /* 0 */ + "wan-sfp-pwrgood", /* 1 */ + "wan-sfp-txfault", /* 2 */ + "wan-sfp-txdisable", /* 3 */ + "wan-sfp-presence", /* 4 */ + "wan-sfp-rxlos", /* 5 */ + "wan-sfp-led", /* 6 */ + "wan-sfp-i2cen", /* 7 */ + "redriver-eqb", /* 8 */ + "redriver-fgb", /* 9 */ + "redriver-swb", /* 10 */ + "redriver-eqa", /* 11 */ + "redriver-fga", /* 12 */ + "redriver-swa", /* 13 */ + "redriver-mode", /* 14 */ + "redriver-enable"; /* 15 */ + }; + }; + }; + + fragment@1 { + target-path="/"; + __overlay__ { + exp2-ftth-p2p-fbxgpio { + compatible = "fbx,fbxgpio"; + exp2-ftth-p2p-sfp-pwren { + gpio = <&exp2_gpio_extender 0 0>; + output-low; + }; + exp2-ftth-p2p-sfp-pwrgood { + gpio = <&exp2_gpio_extender 1 0>; + input; + }; + exp2-ftth-p2p-sfp-txfault { + gpio = <&exp2_gpio_extender 2 0>; + input; + }; + exp2-ftth-p2p-sfp-txdis { + gpio = <&exp2_gpio_extender 3 0>; + output-high; + }; + exp2-ftth-p2p-sfp-presence { + gpio = <&exp2_gpio_extender 4 0>; + input; + }; + exp2-ftth-p2p-sfp-rxlos { + gpio = <&exp2_gpio_extender 5 0>; + input; + }; + exp2-ftth-p2p-sfp-link-led { + gpio = <&exp2_gpio_extender 6 GPIO_ACTIVE_LOW>; + output-low; + }; + exp2-ftth-p2p-sfp-i2cen { + gpio = <&exp2_gpio_extender 7 0>; + /* enable it by default, revisit later */ + output-high; + }; + + exp2-ftth-p2p-redriver-eqb { + gpio = <&exp2_gpio_extender 8 0>; + output-high; + }; + exp2-ftth-p2p-redriver-fgb { + gpio = <&exp2_gpio_extender 9 0>; + output-high; + }; + exp2-ftth-p2p-redriver-swb { + gpio = <&exp2_gpio_extender 10 0>; + output-high; + }; + exp2-ftth-p2p-redriver-eqa { + gpio = <&exp2_gpio_extender 11 0>; + output-high; + }; + exp2-ftth-p2p-redriver-fga { + gpio = <&exp2_gpio_extender 12 0>; + output-high; + }; + exp2-ftth-p2p-redriver-swa { + gpio = <&exp2_gpio_extender 13 0>; + output-high; + }; + exp2-ftth-p2p-redriver-mode { + gpio = <&exp2_gpio_extender 14 0>; + output-low; + }; + exp2-ftth-p2p-redriver-en { + gpio = <&exp2_gpio_extender 15 0>; + output-low; + }; + }; + }; + }; + +}; --- /dev/null 2019-09-30 09:50:43.919599165 +0200 +++ linux-4.14.127-fbx/arch/arm64/boot/dts/marvell/fbxgw7r_exp2_ftth_pon.dts 2019-02-15 14:29:36.054632721 +0100 @@ -0,0 +1,13 @@ +#include + +/dts-v1/; +/plugin/; + +/ { + compatible = "freebox,fbxgw7r"; + fragment@0 { + target-path="/"; + __overlay__ { + }; + }; +}; --- /dev/null 2019-09-30 09:50:43.919599165 +0200 +++ linux-4.14.127-fbx/arch/arm64/boot/dts/marvell/fbxgw7r_exp2_test_module.dts 2019-02-15 14:29:36.058632737 +0100 @@ -0,0 +1,97 @@ +#include + +/dts-v1/; +/plugin/; + +/ { + compatible = "freebox,fbxgw7r"; + + fragment@0 { + target = <&exp2_ext_i2c>; + __overlay__ { + #address-cells = <0x1>; + #size-cells = <0x0>; + + exp2_gpio_extender: exp2@74 { + compatible = "nxp,pca9539"; + reg = <0x74>; + gpio-controller; + ngpios = <16>; + #gpio-cells = <2>; + gpio-line-names = "sfp-pwren", /* 0 */ + "sfp-pwrgood", /* 1 */ + "sfp-txfault", /* 2 */ + "sfp-txdisable", /* 3 */ + "sfp-presence", /* 4 */ + "sfp-rxlos", /* 5 */ + "sfp-led", /* 6 */ + "sfp-i2cen", /* 7 */ + "", /* 8 */ + "", /* 9 */ + "", /* 10 */ + "", /* 11 */ + "", /* 12 */ + "", /* 13 */ + "", /* 14 */ + ""; /* 15 */ + }; + }; + }; + + fragment@1 { + target-path="/"; + __overlay__ { + exp2-test-module-fbxgpio { + compatible = "fbx,fbxgpio"; + exp2-test-module-sfp-pwren { + gpio = <&exp2_gpio_extender 0 0>; + output-low; + }; + exp2-test-module-sfp-pwrgood { + gpio = <&exp2_gpio_extender 1 0>; + input; + }; + exp2-test-module-sfp-txfault { + gpio = <&exp2_gpio_extender 2 0>; + input; + }; + exp2-test-module-sfp-txdis { + gpio = <&exp2_gpio_extender 3 0>; + output-high; + }; + exp2-test-module-sfp-presence { + gpio = <&exp2_gpio_extender 4 0>; + input; + }; + exp2-test-module-sfp-rxlos { + gpio = <&exp2_gpio_extender 5 0>; + input; + }; + exp2-test-module-sfp-link-led { + gpio = <&exp2_gpio_extender 6 GPIO_ACTIVE_LOW>; + output-low; + }; + exp2-test-module-sfp-i2cen { + gpio = <&exp2_gpio_extender 7 0>; + /* enable it by default, revisit later */ + output-high; + }; + }; + }; + }; + + fragment@2 { + target = <&cps_spi1>; + __overlay__ { + #address-cells = <0x1>; + #size-cells = <0x0>; + + exp2-flash@0 { + compatible = "m25p80"; + reg = <0>; + spi-max-frequency = <(1 * 1000 * 1000)>; + label = "exp2-spi-flash"; + }; + }; + }; +}; --- /dev/null 2019-09-30 09:50:43.919599165 +0200 +++ linux-4.14.127-fbx/block/partitions/dt.c 2019-02-15 14:29:37.242637429 +0100 @@ -0,0 +1,205 @@ +#define PREFIX "dtparts" + +#include +#include +#include +#include "check.h" +#include "dt.h" + +/** + * match_one: - Determines if a string matches a simple pattern + * @s: the string to examine for presence of the pattern + * @p: the string containing the pattern + */ +static int match_one(char *s, const char *p) +{ + char *meta, *from, *to; + + while (1) { + int len = -1; + + meta = strchr(p, '%'); + if (!meta) + return strcmp(p, s) == 0; + + if (strncmp(p, s, meta-p)) + return 0; + + s += meta - p; + p = meta + 1; + + if (isdigit(*p)) + len = simple_strtoul(p, (char **) &p, 10); + else if (*p == '%') { + if (*s++ != '%') + return 0; + p++; + continue; + } + + from = s; + switch (*p++) { + case 's': { + size_t str_len = strlen(s); + + if (str_len == 0) + return 0; + if (len == -1 || len > str_len) + len = str_len; + to = s + len; + break; + } + case 'd': + simple_strtol(s, &to, 0); + goto num; + case 'u': + simple_strtoul(s, &to, 0); + goto num; + case 'o': + simple_strtoul(s, &to, 8); + goto num; + case 'x': + simple_strtoul(s, &to, 16); + + num: + if (to == from) + return 0; + break; + default: + return 0; + } + s = to; + } +} + +/* + * + */ +static struct device_node *find_first_parent_node(const struct device *ddev) +{ + while (ddev && !ddev->of_node) + ddev = ddev->parent; + + if (!ddev) + return NULL; + return ddev->of_node; +} + +/* + * + */ +int dt_partition(struct parsed_partitions *state) +{ + struct device *ddev = disk_to_dev(state->bdev->bd_disk); + struct device_node *np, *part_node, *pp; + u64 disk_size, last_end; + int nr_parts, i; + + /* find first parent device with a non null device tree + * node */ + np = find_first_parent_node(ddev); + if (!np) + return -1; + + part_node = NULL; + for_each_child_of_node(np, pp) { + char diskname[BDEVNAME_SIZE]; + const char *pattern; + + if (!of_device_is_compatible(pp, "fixed-partitions")) + continue; + + /* check device name match pattern */ + bdevname(state->bdev, diskname); + + if (of_property_read_string(pp, "disk-name", &pattern)) { + part_node = pp; + break; + } + + if (match_one(diskname, pattern)) { + part_node = pp; + break; + } + } + + if (!part_node) + return -1; + + /* First count the subnodes */ + nr_parts = 0; + for_each_child_of_node(part_node, pp) + nr_parts++; + + if (nr_parts == 0) + return 0; + + disk_size = get_capacity(state->bdev->bd_disk) << 9; + + last_end = 0; + i = 1; + for_each_child_of_node(part_node, pp) { + struct partition_meta_info *info; + char tmp[sizeof (info->volname) + 4]; + const __be32 *reg; + const char *partname; + int a_cells, s_cells; + u64 size, offset; + int len; + + reg = of_get_property(pp, "reg", &len); + if (!reg) { + pr_err("part %pOF (%pOF) missing reg property.\n", + pp, np); + return -1; + } + + a_cells = of_n_addr_cells(pp); + s_cells = of_n_size_cells(pp); + if (len / 4 != a_cells + s_cells) { + pr_err("ofpart partition %pOF (%pOF) " + "error parsing reg property.\n", + pp, np); + return -1; + } + + partname = of_get_property(pp, "label", &len); + if (!partname) + partname = of_get_property(pp, "name", &len); + + if (i >= state->limit) { + pr_err("too many partitions\n"); + return -1; + } + + offset = of_read_number(reg, a_cells); + if (offset == (u64)-1) { + offset = last_end; + } + + size = of_read_number(reg + a_cells, s_cells); + if (size == (u64)-1) + size = disk_size - offset; + + last_end = offset + size; + put_partition(state, i, offset >> 9, size >> 9); + + info = &state->parts[i].info; + strlcpy(info->volname, partname, sizeof (info->volname)); + state->parts[i].has_info = true; + + if (!IS_ENABLED(CONFIG_OF_PARTITION_IGNORE_RO) && + of_get_property(pp, "read-only", &len)) + state->parts[i].flags |= ADDPART_FLAG_RO; + + snprintf(tmp, sizeof(tmp), "(%s/%s)", + info->volname, + state->parts[i].flags ? "ro" : "rw"); + strlcat(state->pp_buf, tmp, PAGE_SIZE); + + i++; + } + + strlcat(state->pp_buf, "\n", PAGE_SIZE); + return 1; +} --- /dev/null 2019-09-30 09:50:43.919599165 +0200 +++ linux-4.14.127-fbx/block/partitions/dt.h 2019-02-15 14:29:37.242637429 +0100 @@ -0,0 +1 @@ +int dt_partition(struct parsed_partitions *); --- /dev/null 2019-09-30 09:50:43.919599165 +0200 +++ linux-4.14.127-fbx/config 2019-10-04 13:23:55.799870630 +0200 @@ -0,0 +1,3950 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm64 4.14.127 Kernel Configuration +# +CONFIG_ARM64=y +CONFIG_64BIT=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_MMU=y +CONFIG_ARM64_PAGE_SHIFT=12 +CONFIG_ARM64_CONT_SHIFT=4 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_HAVE_GENERIC_GUP=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_SMP=y +CONFIG_SWIOTLB=y +CONFIG_IOMMU_HELPER=y +CONFIG_KERNEL_MODE_NEON=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_PGTABLE_LEVELS=3 +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_PROC_KCORE_TEXT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y +CONFIG_THREAD_INFO_IN_TASK=y + +# +# General setup +# +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="/opt/toolchains/aarch64-musl-1.1.21-gcc-8.3.0-binutils-2.32-gdb-7.12.1-1/bin/aarch64-linux-musl-" +# CONFIG_COMPILE_TEST is not set +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_DEFAULT_HOSTNAME="(none)" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_CROSS_MEMORY_ATTACH is not set +# CONFIG_FHANDLE is not set +# CONFIG_USELIB is not set +CONFIG_AUDIT=y +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_AUDITSYSCALL=y +CONFIG_AUDIT_WATCH=y +CONFIG_AUDIT_TREE=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_HANDLE_DOMAIN_IRQ=y +# CONFIG_IRQ_DOMAIN_DEBUG is not set +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +# CONFIG_GENERIC_IRQ_DEBUGFS is not set +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_HZ_PERIODIC=y +# CONFIG_NO_HZ_IDLE is not set +# CONFIG_NO_HZ_FULL is not set +# CONFIG_NO_HZ is not set +CONFIG_HIGH_RES_TIMERS=y + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +CONFIG_IRQ_TIME_ACCOUNTING=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +CONFIG_TREE_SRCU=y +# CONFIG_TASKS_RCU is not set +CONFIG_RCU_STALL_COMMON=y +CONFIG_RCU_NEED_SEGCBLIST=y +CONFIG_BUILD_BIN2C=y +CONFIG_IKCONFIG=y +# CONFIG_IKCONFIG_PROC is not set +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 +# CONFIG_FBX_DECRYPT_INITRD is not set +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y +CONFIG_CGROUPS=y +# CONFIG_MEMCG is not set +# CONFIG_BLK_CGROUP is not set +# CONFIG_CGROUP_SCHED is not set +# CONFIG_CGROUP_PIDS is not set +# CONFIG_CGROUP_RDMA is not set +# CONFIG_CGROUP_FREEZER is not set +# CONFIG_CPUSETS is not set +# CONFIG_CGROUP_DEVICE is not set +# CONFIG_CGROUP_CPUACCT is not set +# CONFIG_CGROUP_PERF is not set +# CONFIG_CGROUP_DEBUG is not set +# CONFIG_SOCK_CGROUP_DATA is not set +# CONFIG_CHECKPOINT_RESTORE is not set +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_NET_NS=y +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SYSFS_DEPRECATED is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_INITRAMFS_FORCE is not set +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_BPF=y +CONFIG_EXPERT=y +CONFIG_MULTIUSER=y +# CONFIG_SGETMASK_SYSCALL is not set +# CONFIG_SYSFS_SYSCALL is not set +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_POSIX_TIMERS=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set +CONFIG_KALLSYMS_BASE_RELATIVE=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_FUTEX_PI=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +# CONFIG_BPF_SYSCALL is not set +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_ADVISE_SYSCALLS=y +# CONFIG_USERFAULTFD is not set +CONFIG_PCI_QUIRKS=y +CONFIG_MEMBARRIER=y +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +# CONFIG_PC104 is not set + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_SLAB_MERGE_DEFAULT=y +# CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_SLAB_FREELIST_HARDENED is not set +CONFIG_SLUB_CPU_PARTIAL=y +# CONFIG_SYSTEM_DATA_VERIFICATION is not set +# CONFIG_PROFILING is not set +# CONFIG_KPROBES is not set +# CONFIG_JUMP_LABEL is not set +# CONFIG_UPROBES is not set +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_RCU_TABLE_FREE=y +CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y +CONFIG_HAVE_CMPXCHG_LOCAL=y +CONFIG_HAVE_CMPXCHG_DOUBLE=y +CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_SECCOMP_FILTER=y +CONFIG_HAVE_GCC_PLUGINS=y +# CONFIG_GCC_PLUGINS is not set +CONFIG_HAVE_CC_STACKPROTECTOR=y +# CONFIG_CC_STACKPROTECTOR is not set +CONFIG_CC_STACKPROTECTOR_NONE=y +# CONFIG_CC_STACKPROTECTOR_REGULAR is not set +# CONFIG_CC_STACKPROTECTOR_STRONG is not set +CONFIG_THIN_ARCHIVES=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_ARCH_MMAP_RND_BITS=18 +# CONFIG_HAVE_ARCH_HASH is not set +# CONFIG_ISA_BUS_API is not set +CONFIG_CLONE_BACKWARDS=y +# CONFIG_CPU_NO_EFFICIENT_FFS is not set +CONFIG_HAVE_ARCH_VMAP_STACK=y +# CONFIG_ARCH_OPTIONAL_KERNEL_RWX is not set +# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_STRICT_MODULE_RWX=y +CONFIG_REFCOUNT_FULL=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +# CONFIG_MODULE_COMPRESS is not set +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_BLOCK=y +CONFIG_BLK_SCSI_REQUEST=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_DEV_ZONED is not set +# CONFIG_BLK_CMDLINE_PARSER is not set +# CONFIG_BLK_WBT is not set +CONFIG_BLK_DEBUG_FS=y +# CONFIG_BLK_SED_OPAL is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_AIX_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +# CONFIG_CMDLINE_PARTITION is not set +CONFIG_OF_PARTITION=y +CONFIG_OF_PARTITION_IGNORE_RO=y +CONFIG_BLK_MQ_PCI=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=y +# CONFIG_IOSCHED_BFQ is not set +CONFIG_PREEMPT_NOTIFIERS=y +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_LOCK_SPIN_ON_OWNER=y +# CONFIG_FREEZER is not set + +# +# Platform selection +# +# CONFIG_ARCH_ACTIONS is not set +# CONFIG_ARCH_SUNXI is not set +# CONFIG_ARCH_ALPINE is not set +# CONFIG_ARCH_BCM2835 is not set +# CONFIG_ARCH_BCM_IPROC is not set +# CONFIG_ARCH_BERLIN is not set +# CONFIG_ARCH_BRCMSTB is not set +# CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_LAYERSCAPE is not set +# CONFIG_ARCH_LG1K is not set +# CONFIG_ARCH_HISI is not set +# CONFIG_ARCH_MEDIATEK is not set +# CONFIG_ARCH_MESON is not set +CONFIG_ARCH_MVEBU=y +# CONFIG_ARCH_QCOM is not set +# CONFIG_ARCH_REALTEK is not set +# CONFIG_ARCH_ROCKCHIP is not set +# CONFIG_ARCH_SEATTLE is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_STRATIX10 is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_SPRD is not set +# CONFIG_ARCH_THUNDER is not set +# CONFIG_ARCH_THUNDER2 is not set +# CONFIG_ARCH_UNIPHIER is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_VULCAN is not set +# CONFIG_ARCH_XGENE is not set +# CONFIG_ARCH_ZX is not set +# CONFIG_ARCH_ZYNQMP is not set + +# +# Bus support +# +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_SYSCALL=y +CONFIG_PCIEPORTBUS=y +# CONFIG_PCIEAER is not set +# CONFIG_PCIEASPM is not set +# CONFIG_PCIE_DPC is not set +# CONFIG_PCIE_PTM is not set +CONFIG_PCI_BUS_ADDR_T_64BIT=y +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCI_PRI is not set +# CONFIG_PCI_PASID is not set +# CONFIG_HOTPLUG_PCI is not set + +# +# DesignWare PCI Core Support +# +CONFIG_PCIE_DW=y +CONFIG_PCIE_DW_HOST=y +# CONFIG_PCIE_DW_PLAT is not set +# CONFIG_PCI_HISI is not set +CONFIG_PCIE_ARMADA_8K=y +# CONFIG_PCIE_KIRIN is not set + +# +# PCI host controller drivers +# +# CONFIG_PCI_AARDVARK is not set +# CONFIG_PCI_HOST_GENERIC is not set +# CONFIG_PCI_XGENE is not set +# CONFIG_PCI_HOST_THUNDER_PEM is not set +# CONFIG_PCI_HOST_THUNDER_ECAM is not set + +# +# PCI Endpoint +# +# CONFIG_PCI_ENDPOINT is not set + +# +# PCI switch controller drivers +# +# CONFIG_PCI_SW_SWITCHTEC is not set + +# +# Kernel Features +# + +# +# ARM errata workarounds via the alternatives framework +# +# CONFIG_ARM64_ERRATUM_826319 is not set +# CONFIG_ARM64_ERRATUM_827319 is not set +# CONFIG_ARM64_ERRATUM_824069 is not set +# CONFIG_ARM64_ERRATUM_819472 is not set +# CONFIG_ARM64_ERRATUM_832075 is not set +CONFIG_ARM64_ERRATUM_834220=y +# CONFIG_ARM64_ERRATUM_843419 is not set +CONFIG_ARM64_ERRATUM_1024718=y +# CONFIG_CAVIUM_ERRATUM_22375 is not set +# CONFIG_CAVIUM_ERRATUM_23154 is not set +# CONFIG_CAVIUM_ERRATUM_27456 is not set +# CONFIG_CAVIUM_ERRATUM_30115 is not set +# CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set +# CONFIG_QCOM_FALKOR_ERRATUM_1009 is not set +# CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set +# CONFIG_QCOM_FALKOR_ERRATUM_E1041 is not set +CONFIG_ARM64_4K_PAGES=y +# CONFIG_ARM64_16K_PAGES is not set +# CONFIG_ARM64_64K_PAGES is not set +CONFIG_ARM64_VA_BITS_39=y +# CONFIG_ARM64_VA_BITS_48 is not set +CONFIG_ARM64_VA_BITS=39 +# CONFIG_CPU_BIG_ENDIAN is not set +# CONFIG_SCHED_MC is not set +# CONFIG_SCHED_SMT is not set +CONFIG_NR_CPUS=4 +# CONFIG_HOTPLUG_CPU is not set +# CONFIG_NUMA is not set +CONFIG_HOLES_IN_ZONE=y +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_PREEMPT_COUNT=y +CONFIG_HZ_100=y +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +CONFIG_SCHED_HRTICK=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_DEFAULT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HW_PERF_EVENTS=y +CONFIG_SYS_SUPPORTS_HUGETLBFS=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM=y +CONFIG_HAVE_MEMORY_PRESENT=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_NO_BOOTMEM=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_COMPACTION is not set +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_BOUNCE=y +CONFIG_MMU_NOTIFIER=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y +# CONFIG_MEMORY_FAILURE is not set +# CONFIG_TRANSPARENT_HUGEPAGE is not set +# CONFIG_ARCH_WANTS_THP_SWAP is not set +# CONFIG_CLEANCACHE is not set +# CONFIG_CMA is not set +# CONFIG_ZPOOL is not set +# CONFIG_ZBUD is not set +# CONFIG_ZSMALLOC is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_IDLE_PAGE_TRACKING is not set +# CONFIG_PERCPU_STATS is not set +CONFIG_SECCOMP=y +# CONFIG_PARAVIRT is not set +# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set +# CONFIG_CRASH_DUMP is not set +# CONFIG_XEN is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +# CONFIG_UNMAP_KERNEL_AT_EL0 is not set +# CONFIG_HARDEN_BRANCH_PREDICTOR is not set +# CONFIG_ARM64_SSBD is not set +# CONFIG_ARM64_SW_TTBR0_PAN is not set + +# +# ARMv8.1 architectural features +# +CONFIG_ARM64_HW_AFDBM=y +CONFIG_ARM64_PAN=y +# CONFIG_ARM64_LSE_ATOMICS is not set +# CONFIG_ARM64_VHE is not set + +# +# ARMv8.2 architectural features +# +CONFIG_ARM64_UAO=y +# CONFIG_ARM64_PMEM is not set +# CONFIG_RANDOMIZE_BASE is not set + +# +# Boot options +# +CONFIG_CMDLINE="console=ttyS0,115200 earlycon=uart8250,mmio32,0xf0512000 maxcpus=4 root=/dev/nfs ip=:::::eth1.41:dhcp memtest=0 dhcpclass=linux-fbxgw7r" +CONFIG_CMDLINE_FORCE=y +# CONFIG_EFI is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ELFCORE=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_BINFMT_SCRIPT=y +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_COREDUMP=y +# CONFIG_COMPAT is not set + +# +# Power management options +# +# CONFIG_SUSPEND is not set +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y + +# +# CPU Power Management +# + +# +# CPU Idle +# +# CONFIG_CPU_IDLE is not set +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set +CONFIG_NET=y +CONFIG_NET_INGRESS=y +CONFIG_NET_EGRESS=y + +# +# Networking options +# +CONFIG_NETSKBPAD=64 +# CONFIG_NETRXTHREAD is not set +CONFIG_PACKET=y +# CONFIG_PACKET_DIAG is not set +CONFIG_UNIX=y +CONFIG_UNIX_ABSTRACT_IGNORE_NETNS=y +# CONFIG_UNIX_DIAG is not set +# CONFIG_TLS is not set +CONFIG_XFRM=y +CONFIG_XFRM_ALGO=y +CONFIG_XFRM_USER=y +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_FIB_TRIE_STATS is not set +CONFIG_IP_MULTIPLE_TABLES=y +# CONFIG_IP_ROUTE_MULTIPATH is not set +# CONFIG_IP_ROUTE_VERBOSE is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +CONFIG_NET_IPGRE_DEMUX=y +CONFIG_NET_IP_TUNNEL=y +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_NET_IPVTI is not set +# CONFIG_NET_UDP_TUNNEL is not set +# CONFIG_NET_FOU is not set +# CONFIG_NET_FOU_IP_TUNNELS is not set +CONFIG_INET_AH=y +CONFIG_INET_ESP=y +# CONFIG_INET_ESP_OFFLOAD is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_UDP_DIAG is not set +# CONFIG_INET_RAW_DIAG is not set +# CONFIG_INET_DIAG_DESTROY is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_IPV6_ILA is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +CONFIG_INET6_TUNNEL=y +# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET6_XFRM_MODE_TUNNEL is not set +# CONFIG_INET6_XFRM_MODE_BEET is not set +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=y +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=y +# CONFIG_IPV6_GRE is not set +# CONFIG_IPV6_FOU is not set +# CONFIG_IPV6_FOU_TUNNEL is not set +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +# CONFIG_IPV6_MROUTE is not set +# CONFIG_IPV6_SEG6_LWTUNNEL is not set +# CONFIG_IPV6_SEG6_HMAC is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NET_PTP_CLASSIFY is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETFILTER=y +CONFIG_NETFILTER_ADVANCED=y +# CONFIG_BRIDGE_NETFILTER is not set + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_INGRESS is not set +# CONFIG_NETFILTER_NETLINK_ACCT is not set +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +CONFIG_NF_CONNTRACK=y +# CONFIG_NF_LOG_NETDEV is not set +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_PROCFS=y +# CONFIG_NF_CONNTRACK_EVENTS is not set +# CONFIG_NF_CONNTRACK_TIMEOUT is not set +# CONFIG_NF_CONNTRACK_TIMESTAMP is not set +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_GRE=m +CONFIG_NF_CT_PROTO_SCTP=y +# CONFIG_NF_CT_PROTO_UDPLITE is not set +# CONFIG_NF_CONNTRACK_AMANDA is not set +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +# CONFIG_NF_CONNTRACK_SNMP is not set +CONFIG_NF_CONNTRACK_PPTP=m +# CONFIG_NF_CONNTRACK_SANE is not set +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=y +# CONFIG_NF_CT_NETLINK is not set +# CONFIG_NF_CT_NETLINK_TIMEOUT is not set +CONFIG_NF_NAT=y +CONFIG_NF_NAT_NEEDED=y +CONFIG_NF_NAT_PROTO_DCCP=y +CONFIG_NF_NAT_PROTO_SCTP=y +# CONFIG_NF_NAT_AMANDA is not set +CONFIG_NF_NAT_FTP=y +CONFIG_NF_NAT_IRC=m +CONFIG_NF_NAT_SIP=m +CONFIG_NF_NAT_TFTP=y +CONFIG_NF_NAT_REDIRECT=y +# CONFIG_NF_TABLES is not set +CONFIG_NETFILTER_XTABLES=y + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=y +CONFIG_NETFILTER_XT_CONNMARK=y + +# +# Xtables targets +# +# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set +# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y +CONFIG_NETFILTER_XT_TARGET_CONNMARK=y +CONFIG_NETFILTER_XT_TARGET_DSCP=y +# CONFIG_NETFILTER_XT_TARGET_HL is not set +# CONFIG_NETFILTER_XT_TARGET_HMARK is not set +# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set +# CONFIG_NETFILTER_XT_TARGET_LED is not set +# CONFIG_NETFILTER_XT_TARGET_LOG is not set +CONFIG_NETFILTER_XT_TARGET_MARK=y +CONFIG_NETFILTER_XT_NAT=y +# CONFIG_NETFILTER_XT_TARGET_NETMAP is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +CONFIG_NETFILTER_XT_TARGET_REDIRECT=y +# CONFIG_NETFILTER_XT_TARGET_TEE is not set +CONFIG_NETFILTER_XT_TARGET_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_TCPMSS=y +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set + +# +# Xtables matches +# +# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_BPF is not set +# CONFIG_NETFILTER_XT_MATCH_CGROUP is not set +# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set +# CONFIG_NETFILTER_XT_MATCH_CONNLABEL is not set +# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +# CONFIG_NETFILTER_XT_MATCH_CPU is not set +CONFIG_NETFILTER_XT_MATCH_DCCP=y +# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set +CONFIG_NETFILTER_XT_MATCH_DSCP=y +# CONFIG_NETFILTER_XT_MATCH_ECN is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set +# CONFIG_NETFILTER_XT_MATCH_HL is not set +# CONFIG_NETFILTER_XT_MATCH_IPCOMP is not set +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +# CONFIG_NETFILTER_XT_MATCH_L2TP is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MAC=y +CONFIG_NETFILTER_XT_MATCH_MARK=y +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set +CONFIG_NETFILTER_XT_MATCH_OWNER=y +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +CONFIG_NETFILTER_XT_MATCH_SCTP=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +# CONFIG_IP_SET is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +CONFIG_IP_FFN=y +CONFIG_IP_FFN_PROCFS=y +CONFIG_NF_DEFRAG_IPV4=y +CONFIG_NF_CONNTRACK_IPV4=y +# CONFIG_NF_SOCKET_IPV4 is not set +# CONFIG_NF_DUP_IPV4 is not set +# CONFIG_NF_LOG_ARP is not set +# CONFIG_NF_LOG_IPV4 is not set +CONFIG_NF_REJECT_IPV4=y +CONFIG_NF_NAT_IPV4=y +CONFIG_NF_NAT_MASQUERADE_IPV4=y +CONFIG_NF_NAT_PROTO_GRE=m +CONFIG_NF_NAT_PPTP=m +CONFIG_NF_NAT_H323=m +CONFIG_IP_NF_IPTABLES=y +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_RPFILTER is not set +# CONFIG_IP_NF_MATCH_TTL is not set +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +# CONFIG_IP_NF_TARGET_SYNPROXY is not set +CONFIG_IP_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +# CONFIG_IP_NF_TARGET_NETMAP is not set +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_MANGLE=y +# CONFIG_IP_NF_TARGET_CLUSTERIP is not set +# CONFIG_IP_NF_TARGET_ECN is not set +# CONFIG_IP_NF_TARGET_TTL is not set +# CONFIG_IP_NF_RAW is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# IPv6: Netfilter Configuration +# +CONFIG_IPV6_FFN=y +CONFIG_IPV6_FFN_PROCFS=y +CONFIG_NF_DEFRAG_IPV6=y +CONFIG_NF_CONNTRACK_IPV6=y +# CONFIG_NF_SOCKET_IPV6 is not set +# CONFIG_NF_DUP_IPV6 is not set +CONFIG_NF_REJECT_IPV6=y +# CONFIG_NF_LOG_IPV6 is not set +CONFIG_NF_NAT_IPV6=y +CONFIG_NF_NAT_MASQUERADE_IPV6=y +CONFIG_IP6_NF_IPTABLES=y +# CONFIG_IP6_NF_MATCH_AH is not set +# CONFIG_IP6_NF_MATCH_EUI64 is not set +# CONFIG_IP6_NF_MATCH_FRAG is not set +# CONFIG_IP6_NF_MATCH_OPTS is not set +# CONFIG_IP6_NF_MATCH_HL is not set +# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set +# CONFIG_IP6_NF_MATCH_MH is not set +# CONFIG_IP6_NF_MATCH_RPFILTER is not set +# CONFIG_IP6_NF_MATCH_RT is not set +# CONFIG_IP6_NF_TARGET_HL is not set +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +# CONFIG_IP6_NF_TARGET_SYNPROXY is not set +CONFIG_IP6_NF_MANGLE=y +# CONFIG_IP6_NF_RAW is not set +CONFIG_IP6_NF_NAT=y +CONFIG_IP6_NF_TARGET_MASQUERADE=y +# CONFIG_IP6_NF_TARGET_NPT is not set +# CONFIG_BRIDGE_NF_EBTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +CONFIG_FBXATM=y +CONFIG_FBXATM_REMOTE=y +CONFIG_FBXATM_STACK=y +# CONFIG_FBXATM_REMOTE_STUB is not set +CONFIG_FBXATM_REMOTE_DRIVER=y +CONFIG_FBXBRIDGE=y +CONFIG_STP=y +CONFIG_BRIDGE=y +# CONFIG_BRIDGE_IGMP_SNOOPING is not set +# CONFIG_BRIDGE_VLAN_FILTERING is not set +CONFIG_HAVE_NET_DSA=y +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=y +# CONFIG_VLAN_8021Q_GVRP is not set +# CONFIG_VLAN_8021Q_MVRP is not set +# CONFIG_DECNET is not set +CONFIG_LLC=y +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_6LOWPAN is not set +# CONFIG_IEEE802154 is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +# CONFIG_NET_SCH_CBQ is not set +# CONFIG_NET_SCH_HTB is not set +# CONFIG_NET_SCH_HFSC is not set +CONFIG_NET_SCH_PRIO=y +CONFIG_NET_SCH_MULTIQ=y +# CONFIG_NET_SCH_RED is not set +# CONFIG_NET_SCH_SFB is not set +CONFIG_NET_SCH_SFQ=y +# CONFIG_NET_SCH_TEQL is not set +# CONFIG_NET_SCH_TBF is not set +# CONFIG_NET_SCH_GRED is not set +# CONFIG_NET_SCH_DSMARK is not set +# CONFIG_NET_SCH_NETEM is not set +CONFIG_NET_SCH_DRR=y +# CONFIG_NET_SCH_MQPRIO is not set +# CONFIG_NET_SCH_CHOKE is not set +# CONFIG_NET_SCH_QFQ is not set +# CONFIG_NET_SCH_CODEL is not set +CONFIG_NET_SCH_FQ_CODEL=y +# CONFIG_NET_SCH_FQ is not set +# CONFIG_NET_SCH_HHF is not set +# CONFIG_NET_SCH_PIE is not set +CONFIG_NET_SCH_INGRESS=y +# CONFIG_NET_SCH_PLUG is not set +# CONFIG_NET_SCH_DEFAULT is not set + +# +# Classification +# +CONFIG_NET_CLS=y +# CONFIG_NET_CLS_BASIC is not set +# CONFIG_NET_CLS_TCINDEX is not set +# CONFIG_NET_CLS_ROUTE4 is not set +# CONFIG_NET_CLS_FW is not set +CONFIG_NET_CLS_U32=y +# CONFIG_CLS_U32_PERF is not set +CONFIG_CLS_U32_MARK=y +# CONFIG_NET_CLS_RSVP is not set +# CONFIG_NET_CLS_RSVP6 is not set +# CONFIG_NET_CLS_FLOW is not set +# CONFIG_NET_CLS_CGROUP is not set +# CONFIG_NET_CLS_BPF is not set +# CONFIG_NET_CLS_FLOWER is not set +# CONFIG_NET_CLS_MATCHALL is not set +# CONFIG_NET_EMATCH is not set +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +# CONFIG_NET_ACT_GACT is not set +# CONFIG_NET_ACT_MIRRED is not set +# CONFIG_NET_ACT_SAMPLE is not set +# CONFIG_NET_ACT_IPT is not set +# CONFIG_NET_ACT_NAT is not set +# CONFIG_NET_ACT_PEDIT is not set +# CONFIG_NET_ACT_SIMP is not set +CONFIG_NET_ACT_SKBEDIT=y +# CONFIG_NET_ACT_CSUM is not set +# CONFIG_NET_ACT_VLAN is not set +# CONFIG_NET_ACT_BPF is not set +# CONFIG_NET_ACT_CONNMARK is not set +# CONFIG_NET_ACT_SKBMOD is not set +# CONFIG_NET_ACT_IFE is not set +# CONFIG_NET_ACT_TUNNEL_KEY is not set +# CONFIG_NET_CLS_IND is not set +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +CONFIG_VSOCKETS=y +CONFIG_VIRTIO_VSOCKETS_COMMON=y +# CONFIG_NETLINK_DIAG is not set +# CONFIG_MPLS is not set +# CONFIG_NET_NSH is not set +# CONFIG_HSR is not set +# CONFIG_NET_SWITCHDEV is not set +# CONFIG_NET_L3_MASTER_DEV is not set +# CONFIG_NET_NCSI is not set +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_XPS=y +# CONFIG_CGROUP_NET_PRIO is not set +# CONFIG_CGROUP_NET_CLASSID is not set +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +CONFIG_BPF_JIT=y +CONFIG_NET_FLOW_LIMIT=y + +# +# Network testing +# +CONFIG_NET_PKTGEN=y +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_AF_KCM is not set +# CONFIG_STREAM_PARSER is not set +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +CONFIG_CFG80211=y +CONFIG_NL80211_TESTMODE=y +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +CONFIG_CFG80211_CERTIFICATION_ONUS=y +# CONFIG_CFG80211_REG_CELLULAR_HINTS is not set +# CONFIG_CFG80211_REG_RELAX_NO_IR is not set +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEBUGFS is not set +CONFIG_CFG80211_INTERNAL_REGDB=y +CONFIG_CFG80211_CRDA_SUPPORT=y +# CONFIG_CFG80211_WEXT is not set +# CONFIG_LIB80211 is not set +CONFIG_MAC80211=y +CONFIG_MAC80211_HAS_RC=y +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_RC_MINSTREL_HT=y +# CONFIG_MAC80211_RC_MINSTREL_VHT is not set +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" +# CONFIG_MAC80211_MESH is not set +CONFIG_MAC80211_LEDS=y +# CONFIG_MAC80211_DEBUGFS is not set +# CONFIG_MAC80211_MESSAGE_TRACING is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +# CONFIG_PSAMPLE is not set +# CONFIG_NET_IFE is not set +# CONFIG_LWTUNNEL is not set +CONFIG_DST_CACHE=y +CONFIG_GRO_CELLS=y +# CONFIG_NET_DEVLINK is not set +CONFIG_MAY_USE_DEVLINK=y +CONFIG_HAVE_EBPF_JIT=y + +# +# Device Drivers +# +CONFIG_ARM_AMBA=y + +# +# Generic Driver Options +# +# CONFIG_UEVENT_HELPER is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_EXTRA_FIRMWARE="" +CONFIG_FW_LOADER_USER_HELPER=y +CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y +CONFIG_WANT_DEV_COREDUMP=y +# CONFIG_ALLOW_DEV_COREDUMP is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set +# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=m +CONFIG_REGMAP_MMIO=y +CONFIG_DMA_SHARED_BUFFER=y +# CONFIG_DMA_FENCE_TRACE is not set +CONFIG_GENERIC_ARCH_TOPOLOGY=y + +# +# Bus devices +# +# CONFIG_ARM_CCI400_PMU is not set +# CONFIG_ARM_CCI5xx_PMU is not set +# CONFIG_ARM_CCN is not set +# CONFIG_BRCMSTB_GISB_ARB is not set +# CONFIG_VEXPRESS_CONFIG is not set +# CONFIG_CONNECTOR is not set +CONFIG_FREEBOX_PROCFS=y +CONFIG_MTD=y +# CONFIG_MTD_TESTS is not set +CONFIG_MTD_ERASE_PRINTK=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +CONFIG_MTD_OF_PARTS=y +# CONFIG_MTD_OF_PARTS_IGNORE_RO is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# Partition parsers +# +# CONFIG_MTD_FBX6HD_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_PARTITIONED_MASTER is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_M25P80=y +# CONFIG_MTD_MCHP23K256 is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR & LPDDR2 PCM memory drivers +# +# CONFIG_MTD_LPDDR is not set +CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_MT81xx_NOR is not set +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set +# CONFIG_MTD_UBI is not set +CONFIG_DTC=y +CONFIG_OF=y +# CONFIG_OF_UNITTEST is not set +CONFIG_OF_DTB_BUILTIN_LIST="" +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_ADDRESS_PCI=y +CONFIG_OF_IRQ=y +CONFIG_OF_NET=y +CONFIG_OF_MDIO=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OF_RESOLVE=y +CONFIG_OF_OVERLAY=y +CONFIG_OF_CONFIGFS=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_NULL_BLK is not set +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_DRBD is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SKD is not set +# CONFIG_BLK_DEV_SX8 is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=1 +CONFIG_BLK_DEV_RAM_SIZE=65536 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV_RSXX is not set +# CONFIG_BLK_DEV_NVME is not set +# CONFIG_NVME_FC is not set +# CONFIG_NVME_TARGET is not set + +# +# Misc devices +# +# CONFIG_WINTEGRA_MMAP is not set +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_AD525X_DPOT is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_INTELCE_PIC16PMU is not set +CONFIG_FBXSERIAL_OF=y +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +# CONFIG_SRAM is not set +# CONFIG_PCI_ENDPOINT_TEST is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=m +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_EEPROM_IDT_89HPESX is not set +CONFIG_EEPROM_EE1004_RAW=y +# CONFIG_CB710_CORE is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set + +# +# Altera FPGA firmware download module +# +# CONFIG_ALTERA_STAPL is not set + +# +# Intel MIC Bus Driver +# + +# +# SCIF Bus Driver +# + +# +# VOP Bus Driver +# + +# +# Intel MIC Host Driver +# + +# +# Intel MIC Card Driver +# + +# +# SCIF Driver +# + +# +# Intel MIC Coprocessor State Management (COSM) Drivers +# + +# +# VOP Driver +# +# CONFIG_GENWQE is not set +# CONFIG_ECHO is not set +# CONFIG_CXL_BASE is not set +# CONFIG_CXL_AFU_DRIVER_OPS is not set +# CONFIG_CXL_LIB is not set + +# +# RemoTI support +# + +# +# HDMI CEC support +# +# CONFIG_HDMI_CEC is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_NETLINK is not set +# CONFIG_SCSI_MQ_DEFAULT is not set +# CONFIG_SCSI_PROC_FS is not set + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +CONFIG_SCSI_SCAN_ASYNC=y + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +CONFIG_HAVE_PATA_PLATFORM=y +CONFIG_ATA=y +# CONFIG_ATA_NONSTANDARD is not set +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_SATA_PMP=y + +# +# Controllers with non-SFF native interface +# +# CONFIG_SATA_AHCI is not set +# CONFIG_SATA_AHCI_PLATFORM is not set +# CONFIG_AHCI_CEVA is not set +CONFIG_AHCI_MVEBU=m +# CONFIG_AHCI_QORIQ is not set +# CONFIG_SATA_INIC162X is not set +# CONFIG_SATA_ACARD_AHCI is not set +# CONFIG_SATA_SIL24 is not set +# CONFIG_ATA_SFF is not set +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +# CONFIG_MD_AUTODETECT is not set +# CONFIG_MD_LINEAR is not set +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +CONFIG_MD_RAID10=y +CONFIG_MD_RAID456=y +# CONFIG_MD_MULTIPATH is not set +# CONFIG_MD_FAULTY is not set +# CONFIG_BCACHE is not set +CONFIG_BLK_DEV_DM_BUILTIN=y +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_MQ_DEFAULT is not set +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=y +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_THIN_PROVISIONING is not set +# CONFIG_DM_CACHE is not set +# CONFIG_DM_ERA is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_RAID is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set +# CONFIG_DM_UEVENT is not set +# CONFIG_DM_FLAKEY is not set +# CONFIG_DM_VERITY is not set +# CONFIG_DM_SWITCH is not set +# CONFIG_DM_LOG_WRITES is not set +# CONFIG_DM_INTEGRITY is not set +# CONFIG_TARGET_CORE is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +CONFIG_DUMMY=y +# CONFIG_EQUALIZER is not set +# CONFIG_NET_FC is not set +# CONFIG_IFB is not set +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_VXLAN is not set +# CONFIG_GTP is not set +# CONFIG_MACSEC is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +CONFIG_TUN=y +# CONFIG_TUN_VNET_CROSS_LE is not set +# CONFIG_VETH is not set +# CONFIG_NLMON is not set +# CONFIG_VSOCKMON is not set +# CONFIG_ARCNET is not set + +# +# CAIF transport drivers +# + +# +# Distributed Switch Architecture drivers +# +CONFIG_ETHERNET=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_AGERE is not set +# CONFIG_NET_VENDOR_ALACRITECH is not set +# CONFIG_NET_VENDOR_ALTEON is not set +# CONFIG_ALTERA_TSE is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_AMD is not set +# CONFIG_NET_VENDOR_AQUANTIA is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_VENDOR_AURORA is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_VENDOR_CAVIUM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_EXAR is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_HP is not set +# CONFIG_NET_VENDOR_HUAWEI is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_JME is not set +CONFIG_NET_VENDOR_MARVELL=y +CONFIG_MVMDIO=y +# CONFIG_MVNETA is not set +CONFIG_MVPP2=y +CONFIG_MVPP2_FBX_FF=y +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_FEALNX is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_PACKET_ENGINE is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_REALTEK is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_RDC is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_BUS=y +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set +# CONFIG_MDIO_HISI_FEMAC is not set +CONFIG_MDIO_I2C=y +# CONFIG_MDIO_OCTEON is not set +# CONFIG_MDIO_THUNDER is not set +CONFIG_PHYLINK=y +CONFIG_PHYLIB=y +CONFIG_SWPHY=y +# CONFIG_LED_TRIGGER_PHY is not set + +# +# MII PHY device drivers +# +CONFIG_SFP=y +# CONFIG_AMD_PHY is not set +# CONFIG_AQUANTIA_PHY is not set +# CONFIG_AT803X_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_CORTINA_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +CONFIG_FIXED_PHY=y +# CONFIG_ICPLUS_PHY is not set +# CONFIG_INTEL_XWAY_PHY is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_MARVELL_10G_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_MICROCHIP_PHY is not set +# CONFIG_MICROSEMI_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_ROCKCHIP_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_TERANETICS_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_XILINX_GMII2RGMII is not set +# CONFIG_MICREL_KS8995MA is not set +CONFIG_PPP=y +# CONFIG_PPP_BSDCOMP is not set +# CONFIG_PPP_DEFLATE is not set +# CONFIG_PPP_FILTER is not set +CONFIG_PPP_MPPE=y +# CONFIG_PPP_MULTILINK is not set +CONFIG_PPPOE=y +CONFIG_PPTP=y +# CONFIG_PPP_ASYNC is not set +# CONFIG_PPP_SYNC_TTY is not set +# CONFIG_SLIP is not set +CONFIG_SLHC=y +CONFIG_USB_NET_DRIVERS=y +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_RTL8152 is not set +# CONFIG_USB_LAN78XX is not set +CONFIG_USB_USBNET=y +# CONFIG_USB_NET_AX8817X is not set +# CONFIG_USB_NET_AX88179_178A is not set +CONFIG_USB_NET_CDCETHER=y +# CONFIG_USB_NET_CDC_EEM is not set +# CONFIG_USB_NET_CDC_NCM is not set +# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set +# CONFIG_USB_NET_CDC_MBIM is not set +# CONFIG_USB_NET_DM9601 is not set +# CONFIG_USB_NET_SR9700 is not set +# CONFIG_USB_NET_SR9800 is not set +# CONFIG_USB_NET_SMSC75XX is not set +# CONFIG_USB_NET_SMSC95XX is not set +# CONFIG_USB_NET_GL620A is not set +# CONFIG_USB_NET_NET1080 is not set +# CONFIG_USB_NET_PLUSB is not set +# CONFIG_USB_NET_MCS7830 is not set +# CONFIG_USB_NET_RNDIS_HOST is not set +# CONFIG_USB_NET_CDC_SUBSET is not set +# CONFIG_USB_NET_ZAURUS is not set +# CONFIG_USB_NET_CX82310_ETH is not set +# CONFIG_USB_NET_KALMIA is not set +# CONFIG_USB_NET_QMI_WWAN is not set +# CONFIG_USB_NET_INT51X1 is not set +# CONFIG_USB_IPHETH is not set +# CONFIG_USB_SIERRA_NET is not set +# CONFIG_USB_VL600 is not set +# CONFIG_USB_NET_CH9200 is not set +CONFIG_WLAN=y +# CONFIG_WIRELESS_WDS is not set +# CONFIG_WLAN_VENDOR_ADMTEK is not set +CONFIG_ATH_COMMON=y +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_ATH_DEBUG is not set +CONFIG_ATH_REG_IGNORE=y +# CONFIG_ATH_REG_DYNAMIC_USER_REG_HINTS is not set +# CONFIG_ATH5K is not set +# CONFIG_ATH5K_PCI is not set +# CONFIG_ATH9K is not set +# CONFIG_ATH9K_HTC is not set +# CONFIG_CARL9170 is not set +# CONFIG_ATH6KL is not set +# CONFIG_AR5523 is not set +# CONFIG_WIL6210 is not set +CONFIG_ATH10K=y +CONFIG_ATH10K_PCI=m +# CONFIG_ATH10K_AHB is not set +# CONFIG_ATH10K_SDIO is not set +# CONFIG_ATH10K_USB is not set +CONFIG_ATH10K_DEBUG=y +CONFIG_ATH10K_DEBUGFS=y +CONFIG_ATH10K_DFS_CERTIFIED=y +# CONFIG_WCN36XX is not set +# CONFIG_WLAN_VENDOR_ATMEL is not set +# CONFIG_WLAN_VENDOR_BROADCOM is not set +# CONFIG_WLAN_VENDOR_CISCO is not set +# CONFIG_WLAN_VENDOR_INTEL is not set +# CONFIG_WLAN_VENDOR_INTERSIL is not set +CONFIG_WLAN_VENDOR_MARVELL=y +# CONFIG_LIBERTAS is not set +# CONFIG_LIBERTAS_THINFIRM is not set +# CONFIG_MWIFIEX is not set +CONFIG_MWL8K=m +# CONFIG_WLAN_VENDOR_MEDIATEK is not set +# CONFIG_WLAN_VENDOR_RALINK is not set +# CONFIG_WLAN_VENDOR_REALTEK is not set +# CONFIG_WLAN_VENDOR_RSI is not set +# CONFIG_WLAN_VENDOR_ST is not set +# CONFIG_WLAN_VENDOR_TI is not set +# CONFIG_WLAN_VENDOR_ZYDAS is not set +CONFIG_WLAN_VENDOR_QUANTENNA=y +CONFIG_QTNFMAC=m +CONFIG_QTNFMAC_PEARL_PCIE=m +# CONFIG_MAC80211_HWSIM is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_VMXNET3 is not set +# CONFIG_ISDN is not set +# CONFIG_NVM is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_LEDS is not set +# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_ATMEL_CAPTOUCH is not set +# CONFIG_INPUT_BMA150 is not set +# CONFIG_INPUT_E3X0_BUTTON is not set +# CONFIG_INPUT_MMA8450 is not set +# CONFIG_INPUT_GP2A is not set +# CONFIG_INPUT_GPIO_BEEPER is not set +# CONFIG_INPUT_GPIO_TILT_POLLED is not set +# CONFIG_INPUT_GPIO_DECODER is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_KXTJ9 is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +# CONFIG_INPUT_UINPUT is not set +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_ADXL34X is not set +# CONFIG_INPUT_IMS_PCU is not set +# CONFIG_INPUT_CMA3000 is not set +# CONFIG_INPUT_DRV260X_HAPTICS is not set +# CONFIG_INPUT_DRV2665_HAPTICS is not set +# CONFIG_INPUT_DRV2667_HAPTICS is not set +CONFIG_INPUT_SMSC_CAP1066=m +# CONFIG_RMI4_CORE is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +CONFIG_LDISC_AUTOLOAD=y +CONFIG_DEVMEM=y +# CONFIG_DEVPHYSMEM is not set + +# +# Serial drivers +# +CONFIG_SERIAL_EARLYCON=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +# CONFIG_SERIAL_8250_FINTEK is not set +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_PCI is not set +CONFIG_SERIAL_8250_NR_UARTS=6 +CONFIG_SERIAL_8250_RUNTIME_UARTS=6 +# CONFIG_SERIAL_8250_EXTENDED is not set +# CONFIG_SERIAL_8250_ASPEED_VUART is not set +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_8250_DW=y +# CONFIG_SERIAL_8250_RT288X is not set +# CONFIG_SERIAL_8250_MOXA is not set +CONFIG_SERIAL_OF_PLATFORM=y + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_RP2 is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +# CONFIG_SERIAL_MVEBU_UART is not set +# CONFIG_SERIAL_DEV_BUS is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +CONFIG_HW_RANDOM_OMAP=y +# CONFIG_HW_RANDOM_CAVIUM is not set +# CONFIG_APPLICOM is not set + +# +# PCMCIA character devices +# +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_DEVPORT is not set +# CONFIG_XILLYBUS is not set + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y + +# +# Multiplexer I2C Chip support +# +# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set +CONFIG_I2C_MUX_GPIO=y +# CONFIG_I2C_MUX_GPMUX is not set +# CONFIG_I2C_MUX_LTC4306 is not set +# CONFIG_I2C_MUX_PCA9541 is not set +# CONFIG_I2C_MUX_PCA954x is not set +# CONFIG_I2C_MUX_PINCTRL is not set +# CONFIG_I2C_MUX_REG is not set +# CONFIG_I2C_DEMUX_PINCTRL is not set +# CONFIG_I2C_MUX_MLXCPLD is not set +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=y + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_CADENCE is not set +# CONFIG_I2C_CBUS_GPIO is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_DESIGNWARE_PCI is not set +# CONFIG_I2C_EMEV2 is not set +CONFIG_I2C_GPIO=y +CONFIG_I2C_MV64XXX=y +# CONFIG_I2C_NOMADIK is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PXA is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_RK3X is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_THUNDERX is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_SLAVE is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_ARMADA_3700 is not set +# CONFIG_SPI_AXI_SPI_ENGINE is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_DESIGNWARE is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_OC_TINY is not set +CONFIG_SPI_ORION=y +# CONFIG_SPI_PL022 is not set +# CONFIG_SPI_PXA2XX is not set +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_ROCKCHIP is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_THUNDERX is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_LOOPBACK_TEST is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPI_SLAVE is not set +# CONFIG_SPMI is not set +# CONFIG_HSI is not set +# CONFIG_PPS is not set + +# +# PTP clock support +# +# CONFIG_PTP_1588_CLOCK is not set + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +CONFIG_PINCTRL=y + +# +# Pin controllers +# +CONFIG_PINMUX=y +CONFIG_PINCONF=y +CONFIG_GENERIC_PINCONF=y +# CONFIG_DEBUG_PINCTRL is not set +# CONFIG_PINCTRL_AMD is not set +# CONFIG_PINCTRL_MCP23S08 is not set +# CONFIG_PINCTRL_SINGLE is not set +# CONFIG_PINCTRL_SX150X is not set +CONFIG_PINCTRL_MVEBU=y +CONFIG_PINCTRL_ARMADA_AP806=y +CONFIG_PINCTRL_ARMADA_CP110=y +CONFIG_PINCTRL_ARMADA_37XX=y +CONFIG_GPIOLIB=y +CONFIG_OF_GPIO=y +CONFIG_GPIOLIB_IRQCHIP=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO drivers +# +# CONFIG_GPIO_74XX_MMIO is not set +# CONFIG_GPIO_ALTERA is not set +# CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_FTGPIO010 is not set +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_MOCKUP is not set +CONFIG_GPIO_MVEBU=y +# CONFIG_GPIO_PL061 is not set +# CONFIG_GPIO_SYSCON is not set +# CONFIG_GPIO_XGENE is not set +# CONFIG_GPIO_XILINX is not set + +# +# I2C GPIO expanders +# +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_ADNP is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +CONFIG_GPIO_PCA953X=y +# CONFIG_GPIO_PCA953X_IRQ is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_TPIC2810 is not set + +# +# MFD GPIO expanders +# + +# +# PCI GPIO expanders +# +# CONFIG_GPIO_BT8XX is not set +# CONFIG_GPIO_PCI_IDIO_16 is not set +# CONFIG_GPIO_RDC321X is not set + +# +# SPI GPIO expanders +# +# CONFIG_GPIO_74X164 is not set +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_PISOSR is not set +# CONFIG_GPIO_XRA1403 is not set + +# +# USB GPIO expanders +# +CONFIG_FREEBOX_GPIO=y +CONFIG_FREEBOX_GPIO_DT=y +CONFIG_FREEBOX_JTAG=m +# CONFIG_W1 is not set +# CONFIG_POWER_AVS is not set +CONFIG_POWER_RESET=y +# CONFIG_POWER_RESET_BRCMSTB is not set +# CONFIG_POWER_RESET_GPIO is not set +# CONFIG_POWER_RESET_GPIO_RESTART is not set +# CONFIG_POWER_RESET_LTC2952 is not set +# CONFIG_POWER_RESET_RESTART is not set +# CONFIG_POWER_RESET_XGENE is not set +# CONFIG_POWER_RESET_SYSCON is not set +# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set +# CONFIG_SYSCON_REBOOT_MODE is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_TEST_POWER is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_CHARGER_SBS is not set +# CONFIG_BATTERY_BQ27XXX is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_LTC3651 is not set +# CONFIG_CHARGER_DETECTOR_MAX14656 is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_BQ24257 is not set +# CONFIG_CHARGER_BQ24735 is not set +# CONFIG_CHARGER_BQ25890 is not set +# CONFIG_CHARGER_SMB347 is not set +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_CHARGER_RT9455 is not set +CONFIG_HWMON=y +CONFIG_HWMON_VID=y +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7314 is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7310 is not set +# CONFIG_SENSORS_ADT7410 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +CONFIG_SENSORS_ADT7475=y +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ASPEED is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS620 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_FTSTEUTATES is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_G762 is not set +# CONFIG_SENSORS_GPIO_FAN is not set +# CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_POWR1220 is not set +# CONFIG_SENSORS_LINEAGE is not set +# CONFIG_SENSORS_LTC2945 is not set +# CONFIG_SENSORS_LTC2990 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4222 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4260 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX1668 is not set +# CONFIG_SENSORS_MAX197 is not set +# CONFIG_SENSORS_MAX31722 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_MAX6697 is not set +# CONFIG_SENSORS_MAX31790 is not set +# CONFIG_SENSORS_MCP3021 is not set +# CONFIG_SENSORS_TC654 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LM95234 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_LM95245 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_NTC_THERMISTOR is not set +# CONFIG_SENSORS_NCT6683 is not set +# CONFIG_SENSORS_NCT6775 is not set +# CONFIG_SENSORS_NCT7802 is not set +# CONFIG_SENSORS_NCT7904 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_PMBUS is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_SHT21 is not set +# CONFIG_SENSORS_SHT3x is not set +# CONFIG_SENSORS_SHTC1 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC6W201 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SCH56XX_COMMON is not set +# CONFIG_SENSORS_SCH5627 is not set +# CONFIG_SENSORS_SCH5636 is not set +# CONFIG_SENSORS_STTS751 is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_ADC128D818 is not set +# CONFIG_SENSORS_ADS1015 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_INA209 is not set +# CONFIG_SENSORS_INA2XX is not set +# CONFIG_SENSORS_INA3221 is not set +# CONFIG_SENSORS_TC74 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP103 is not set +# CONFIG_SENSORS_TMP108 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83795 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +CONFIG_SENSORS_AP806=y +# CONFIG_THERMAL is not set +# CONFIG_FREEBOX_WATCHDOG is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +# CONFIG_WATCHDOG_NOWAYOUT is not set +CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y +CONFIG_WATCHDOG_SYSFS=y + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_GPIO_WATCHDOG is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_ZIIRAVE_WATCHDOG is not set +# CONFIG_ARM_SP805_WATCHDOG is not set +CONFIG_ARM_SBSA_WATCHDOG=m +# CONFIG_CADENCE_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_ALIM7101_WDT is not set +# CONFIG_I6300ESB_WDT is not set +# CONFIG_MEN_A21_WDT is not set + +# +# PCI-based Watchdog Cards +# +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_WDTPCI is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set + +# +# Watchdog Pretimeout Governors +# +# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_ACT8945A is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ATMEL_FLEXCOM is not set +# CONFIG_MFD_ATMEL_HLCDC is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_BD9571MWV is not set +# CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_CROS_EC is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_LPC_ICH is not set +# CONFIG_LPC_SCH is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77620 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RTSX_PCI is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RTSX_USB is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_RK808 is not set +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_STMPE is not set +CONFIG_MFD_SYSCON=y +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_TI_LMU is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TI_LP87565 is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +CONFIG_MFD_FBXGW7R_PANEL=y +# CONFIG_REGULATOR is not set +CONFIG_RC_CORE=y +# CONFIG_RC_MAP is not set +# CONFIG_RC_DECODERS is not set +# CONFIG_RC_DEVICES is not set +CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# +# CONFIG_MEDIA_CAMERA_SUPPORT is not set +# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +# CONFIG_MEDIA_RADIO_SUPPORT is not set +# CONFIG_MEDIA_SDR_SUPPORT is not set +# CONFIG_MEDIA_CEC_SUPPORT is not set +# CONFIG_MEDIA_CONTROLLER is not set +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_DVB_CORE=y +# CONFIG_DVB_NET is not set +# CONFIG_TTPCI_EEPROM is not set +CONFIG_DVB_MAX_ADAPTERS=8 +# CONFIG_DVB_DYNAMIC_MINORS is not set +# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set + +# +# Media drivers +# +CONFIG_MEDIA_USB_SUPPORT=y + +# +# Analog/digital TV USB devices +# +# CONFIG_VIDEO_AU0828 is not set + +# +# Digital TV USB devices +# +CONFIG_DVB_USB=y +# CONFIG_DVB_USB_DEBUG is not set +# CONFIG_DVB_USB_A800 is not set +# CONFIG_DVB_USB_DIBUSB_MB is not set +# CONFIG_DVB_USB_DIBUSB_MC is not set +CONFIG_DVB_USB_DIB0700=m +# CONFIG_DVB_USB_UMT_010 is not set +# CONFIG_DVB_USB_CXUSB is not set +# CONFIG_DVB_USB_M920X is not set +# CONFIG_DVB_USB_DIGITV is not set +# CONFIG_DVB_USB_VP7045 is not set +# CONFIG_DVB_USB_VP702X is not set +# CONFIG_DVB_USB_GP8PSK is not set +# CONFIG_DVB_USB_NOVA_T_USB2 is not set +# CONFIG_DVB_USB_TTUSB2 is not set +# CONFIG_DVB_USB_DTT200U is not set +# CONFIG_DVB_USB_OPERA1 is not set +# CONFIG_DVB_USB_AF9005 is not set +# CONFIG_DVB_USB_PCTV452E is not set +# CONFIG_DVB_USB_DW2102 is not set +# CONFIG_DVB_USB_CINERGY_T2 is not set +# CONFIG_DVB_USB_DTV5100 is not set +# CONFIG_DVB_USB_FRIIO is not set +# CONFIG_DVB_USB_AZ6027 is not set +# CONFIG_DVB_USB_TECHNISAT_USB2 is not set +CONFIG_DVB_USB_V2=y +# CONFIG_DVB_USB_AF9015 is not set +CONFIG_DVB_USB_AF9035=m +# CONFIG_DVB_USB_ANYSEE is not set +# CONFIG_DVB_USB_AU6610 is not set +# CONFIG_DVB_USB_AZ6007 is not set +# CONFIG_DVB_USB_CE6230 is not set +# CONFIG_DVB_USB_EC168 is not set +# CONFIG_DVB_USB_GL861 is not set +# CONFIG_DVB_USB_LME2510 is not set +# CONFIG_DVB_USB_MXL111SF is not set +# CONFIG_DVB_USB_RTL28XXU is not set +# CONFIG_DVB_USB_DVBSKY is not set +# CONFIG_DVB_USB_ZD1301 is not set +# CONFIG_DVB_TTUSB_BUDGET is not set +# CONFIG_DVB_TTUSB_DEC is not set +# CONFIG_SMS_USB_DRV is not set +# CONFIG_DVB_B2C2_FLEXCOP_USB is not set +# CONFIG_DVB_AS102 is not set + +# +# Webcam, TV (analog/digital) USB devices +# +# CONFIG_MEDIA_PCI_SUPPORT is not set +# CONFIG_DVB_PLATFORM_DRIVERS is not set + +# +# Supported MMC/SDIO adapters +# +# CONFIG_SMS_SDIO_DRV is not set +# CONFIG_CYPRESS_FIRMWARE is not set + +# +# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) +# +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set +CONFIG_MEDIA_ATTACH=y +CONFIG_MEDIA_TUNER=y + +# +# Customize TV tuners +# +# CONFIG_MEDIA_TUNER_SIMPLE is not set +# CONFIG_MEDIA_TUNER_TDA8290 is not set +# CONFIG_MEDIA_TUNER_TDA827X is not set +# CONFIG_MEDIA_TUNER_TDA18271 is not set +# CONFIG_MEDIA_TUNER_TDA9887 is not set +# CONFIG_MEDIA_TUNER_TEA5761 is not set +# CONFIG_MEDIA_TUNER_TEA5767 is not set +# CONFIG_MEDIA_TUNER_MT20XX is not set +# CONFIG_MEDIA_TUNER_MT2060 is not set +# CONFIG_MEDIA_TUNER_MT2063 is not set +# CONFIG_MEDIA_TUNER_MT2266 is not set +# CONFIG_MEDIA_TUNER_MT2131 is not set +# CONFIG_MEDIA_TUNER_QT1010 is not set +# CONFIG_MEDIA_TUNER_XC2028 is not set +# CONFIG_MEDIA_TUNER_XC5000 is not set +# CONFIG_MEDIA_TUNER_XC4000 is not set +# CONFIG_MEDIA_TUNER_MXL5005S is not set +# CONFIG_MEDIA_TUNER_MXL5007T is not set +# CONFIG_MEDIA_TUNER_MC44S803 is not set +# CONFIG_MEDIA_TUNER_MAX2165 is not set +# CONFIG_MEDIA_TUNER_TDA18218 is not set +# CONFIG_MEDIA_TUNER_FC0011 is not set +# CONFIG_MEDIA_TUNER_FC0012 is not set +# CONFIG_MEDIA_TUNER_FC0013 is not set +# CONFIG_MEDIA_TUNER_TDA18212 is not set +# CONFIG_MEDIA_TUNER_E4000 is not set +# CONFIG_MEDIA_TUNER_FC2580 is not set +# CONFIG_MEDIA_TUNER_M88RS6000T is not set +# CONFIG_MEDIA_TUNER_TUA9001 is not set +# CONFIG_MEDIA_TUNER_SI2157 is not set +CONFIG_MEDIA_TUNER_IT913X=m +# CONFIG_MEDIA_TUNER_R820T is not set +# CONFIG_MEDIA_TUNER_MXL301RF is not set +# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set + +# +# Customise DVB Frontends +# + +# +# Multistandard (satellite) frontends +# +# CONFIG_DVB_STB0899 is not set +# CONFIG_DVB_STB6100 is not set +# CONFIG_DVB_STV090x is not set +# CONFIG_DVB_STV0910 is not set +# CONFIG_DVB_STV6110x is not set +# CONFIG_DVB_STV6111 is not set +# CONFIG_DVB_MXL5XX is not set +# CONFIG_DVB_M88DS3103 is not set + +# +# Multistandard (cable + terrestrial) frontends +# +# CONFIG_DVB_DRXK is not set +# CONFIG_DVB_TDA18271C2DD is not set +# CONFIG_DVB_SI2165 is not set +# CONFIG_DVB_MN88472 is not set +# CONFIG_DVB_MN88473 is not set + +# +# DVB-S (satellite) frontends +# +# CONFIG_DVB_CX24110 is not set +# CONFIG_DVB_CX24123 is not set +# CONFIG_DVB_MT312 is not set +# CONFIG_DVB_ZL10036 is not set +# CONFIG_DVB_ZL10039 is not set +# CONFIG_DVB_S5H1420 is not set +# CONFIG_DVB_STV0288 is not set +# CONFIG_DVB_STB6000 is not set +# CONFIG_DVB_STV0299 is not set +# CONFIG_DVB_STV6110 is not set +# CONFIG_DVB_STV0900 is not set +# CONFIG_DVB_TDA8083 is not set +# CONFIG_DVB_TDA10086 is not set +# CONFIG_DVB_TDA8261 is not set +# CONFIG_DVB_VES1X93 is not set +# CONFIG_DVB_TUNER_ITD1000 is not set +# CONFIG_DVB_TUNER_CX24113 is not set +# CONFIG_DVB_TDA826X is not set +# CONFIG_DVB_TUA6100 is not set +# CONFIG_DVB_CX24116 is not set +# CONFIG_DVB_CX24117 is not set +# CONFIG_DVB_CX24120 is not set +# CONFIG_DVB_SI21XX is not set +# CONFIG_DVB_TS2020 is not set +# CONFIG_DVB_DS3000 is not set +# CONFIG_DVB_MB86A16 is not set +# CONFIG_DVB_TDA10071 is not set + +# +# DVB-T (terrestrial) frontends +# +# CONFIG_DVB_SP8870 is not set +# CONFIG_DVB_SP887X is not set +# CONFIG_DVB_CX22700 is not set +# CONFIG_DVB_CX22702 is not set +# CONFIG_DVB_S5H1432 is not set +# CONFIG_DVB_DRXD is not set +# CONFIG_DVB_L64781 is not set +# CONFIG_DVB_TDA1004X is not set +# CONFIG_DVB_NXT6000 is not set +# CONFIG_DVB_MT352 is not set +# CONFIG_DVB_ZL10353 is not set +# CONFIG_DVB_DIB3000MB is not set +# CONFIG_DVB_DIB3000MC is not set +CONFIG_DVB_DIB7000M=m +CONFIG_DVB_DIB7000P=m +# CONFIG_DVB_DIB9000 is not set +# CONFIG_DVB_TDA10048 is not set +# CONFIG_DVB_AF9013 is not set +# CONFIG_DVB_EC100 is not set +# CONFIG_DVB_STV0367 is not set +# CONFIG_DVB_CXD2820R is not set +# CONFIG_DVB_CXD2841ER is not set +# CONFIG_DVB_RTL2830 is not set +# CONFIG_DVB_RTL2832 is not set +# CONFIG_DVB_SI2168 is not set +# CONFIG_DVB_AS102_FE is not set +# CONFIG_DVB_ZD1301_DEMOD is not set +# CONFIG_DVB_GP8PSK_FE is not set + +# +# DVB-C (cable) frontends +# +# CONFIG_DVB_VES1820 is not set +# CONFIG_DVB_TDA10021 is not set +# CONFIG_DVB_TDA10023 is not set +# CONFIG_DVB_STV0297 is not set + +# +# ATSC (North American/Korean Terrestrial/Cable DTV) frontends +# +# CONFIG_DVB_NXT200X is not set +# CONFIG_DVB_OR51211 is not set +# CONFIG_DVB_OR51132 is not set +# CONFIG_DVB_BCM3510 is not set +# CONFIG_DVB_LGDT330X is not set +# CONFIG_DVB_LGDT3305 is not set +# CONFIG_DVB_LGDT3306A is not set +# CONFIG_DVB_LG2160 is not set +# CONFIG_DVB_S5H1409 is not set +# CONFIG_DVB_AU8522_DTV is not set +# CONFIG_DVB_S5H1411 is not set + +# +# ISDB-T (terrestrial) frontends +# +# CONFIG_DVB_S921 is not set +# CONFIG_DVB_DIB8000 is not set +# CONFIG_DVB_MB86A20S is not set + +# +# ISDB-S (satellite) & ISDB-T (terrestrial) frontends +# +# CONFIG_DVB_TC90522 is not set + +# +# Digital terrestrial only tuners/PLL +# +# CONFIG_DVB_PLL is not set +CONFIG_DVB_TUNER_DIB0070=m +# CONFIG_DVB_TUNER_DIB0090 is not set + +# +# SEC control devices for DVB-S +# +# CONFIG_DVB_DRX39XYJ is not set +# CONFIG_DVB_LNBH25 is not set +# CONFIG_DVB_LNBP21 is not set +# CONFIG_DVB_LNBP22 is not set +# CONFIG_DVB_ISL6405 is not set +# CONFIG_DVB_ISL6421 is not set +# CONFIG_DVB_ISL6423 is not set +# CONFIG_DVB_A8293 is not set +# CONFIG_DVB_SP2 is not set +# CONFIG_DVB_LGS8GL5 is not set +# CONFIG_DVB_LGS8GXX is not set +# CONFIG_DVB_ATBM8830 is not set +# CONFIG_DVB_TDA665x is not set +# CONFIG_DVB_IX2505V is not set +# CONFIG_DVB_M88RS2000 is not set +CONFIG_DVB_AF9033=m +# CONFIG_DVB_HORUS3A is not set +# CONFIG_DVB_ASCOT2E is not set +# CONFIG_DVB_HELENE is not set + +# +# Tools to develop new frontends +# +# CONFIG_DVB_DUMMY_FE is not set + +# +# Graphics support +# +# CONFIG_VGA_ARB is not set +# CONFIG_DRM is not set + +# +# ACP (Audio CoProcessor) Configuration +# +# CONFIG_DRM_LIB_RANDOM is not set + +# +# Frame buffer Devices +# +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +CONFIG_FB_CMDLINE=y +CONFIG_FB_NOTIFY=y +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_IMAGEBLIT=y +# CONFIG_FB_PROVIDE_GET_FB_UNMAPPED_AREA is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +CONFIG_FB_SYS_FOPS=y +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +CONFIG_FB_BACKLIGHT=y +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_ARMCLCD is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_I740 is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_IBM_GXT4500 is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_FB_AUO_K190X is not set +# CONFIG_FB_SIMPLE is not set +# CONFIG_FB_SSD1307 is not set +# CONFIG_FB_SM712 is not set +CONFIG_FB_SSD1327=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +# CONFIG_BACKLIGHT_PM8941_WLED is not set +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_LM3639 is not set +# CONFIG_BACKLIGHT_GPIO is not set +# CONFIG_BACKLIGHT_LV5207LP is not set +# CONFIG_BACKLIGHT_BD6107 is not set +# CONFIG_BACKLIGHT_ARCXCNN is not set +# CONFIG_VGASTATE is not set + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=25 +# CONFIG_FRAMEBUFFER_CONSOLE is not set +# CONFIG_LOGO is not set +CONFIG_SOUND=y +# CONFIG_SOUND_OSS_CORE is not set +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_HWDEP=y +CONFIG_SND_RAWMIDI=y +# CONFIG_SND_OSSEMUL is not set +CONFIG_SND_PCM_TIMER=y +# CONFIG_SND_HRTIMER is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_PROC_FS=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_ALOOP is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set +# CONFIG_SND_PCI is not set + +# +# HD-Audio +# +CONFIG_SND_HDA_PREALLOC_SIZE=64 +# CONFIG_SND_SPI is not set +CONFIG_SND_USB=y +CONFIG_SND_USB_AUDIO=y +# CONFIG_SND_USB_UA101 is not set +# CONFIG_SND_USB_CAIAQ is not set +# CONFIG_SND_USB_6FIRE is not set +# CONFIG_SND_USB_HIFACE is not set +# CONFIG_SND_BCD2000 is not set +# CONFIG_SND_USB_POD is not set +# CONFIG_SND_USB_PODHD is not set +# CONFIG_SND_USB_TONEPORT is not set +# CONFIG_SND_USB_VARIAX is not set +# CONFIG_SND_SOC is not set + +# +# HID support +# +CONFIG_HID=y +# CONFIG_HID_BATTERY_STRENGTH is not set +# CONFIG_HIDRAW is not set +# CONFIG_UHID is not set +# CONFIG_HID_GENERIC is not set + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_ACRUX is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_ASUS is not set +# CONFIG_HID_AUREAL is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CORSAIR is not set +# CONFIG_HID_PRODIKEYS is not set +# CONFIG_HID_CMEDIA is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_ELECOM is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_GEMBIRD is not set +# CONFIG_HID_GFRM is not set +# CONFIG_HID_KEYTOUCH is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_FBX_REMOTE_AUDIO is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_ICADE is not set +# CONFIG_HID_ITE is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LED is not set +# CONFIG_HID_LENOVO is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MAGICMOUSE is not set +# CONFIG_HID_MAYFLASH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NTI is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_PLANTRONICS is not set +# CONFIG_HID_PRIMAX is not set +# CONFIG_HID_SAITEK is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_STEELSERIES is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_RMI is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TIVO is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THINGM is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_UDRAW_PS3 is not set +# CONFIG_HID_WIIMOTE is not set +# CONFIG_HID_XINMO is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +# CONFIG_HID_SENSOR_HUB is not set +# CONFIG_HID_ALPS is not set + +# +# USB HID support +# +# CONFIG_USB_HID is not set +# CONFIG_HID_PID is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set + +# +# I2C HID support +# +# CONFIG_I2C_HID is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +# CONFIG_USB_PCI is not set +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_XHCI_HCD=m +CONFIG_USB_XHCI_PLATFORM=m +CONFIG_USB_XHCI_MVEBU=m +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_MAX3421_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=y +CONFIG_USB_PRINTER=y +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set +# CONFIG_USB_UAS is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_DWC3 is not set +# CONFIG_USB_DWC2 is not set +# CONFIG_USB_ISP1760 is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HUB_USB251XB is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_HSIC_USB4604 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set +# CONFIG_USB_CHAOSKEY is not set + +# +# USB Physical Layer drivers +# +# CONFIG_USB_PHY is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_ULPI is not set +# CONFIG_USB_GADGET is not set + +# +# USB Power Delivery and Type-C drivers +# +# CONFIG_TYPEC_UCSI is not set +# CONFIG_USB_LED_TRIG is not set +# CONFIG_USB_ULPI_BUS is not set +# CONFIG_UWB is not set +CONFIG_MMC=y +# CONFIG_PWRSEQ_EMMC is not set +# CONFIG_PWRSEQ_SIMPLE is not set +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_ARMMMCI is not set +CONFIG_MMC_SDHCI=y +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +# CONFIG_MMC_SDHCI_OF_ARASAN is not set +# CONFIG_MMC_SDHCI_OF_AT91 is not set +# CONFIG_MMC_SDHCI_CADENCE is not set +# CONFIG_MMC_SDHCI_PXAV3 is not set +# CONFIG_MMC_SDHCI_F_SDH30 is not set +# CONFIG_MMC_TIFM_SD is not set +# CONFIG_MMC_SPI is not set +# CONFIG_MMC_CB710 is not set +# CONFIG_MMC_VIA_SDMMC is not set +# CONFIG_MMC_CAVIUM_THUNDERX is not set +# CONFIG_MMC_DW is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MMC_USDHI6ROL0 is not set +# CONFIG_MMC_TOSHIBA_PCI is not set +# CONFIG_MMC_MTK is not set +CONFIG_MMC_SDHCI_XENON=y +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +# CONFIG_LEDS_CLASS_FLASH is not set +# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set + +# +# LED drivers +# +# CONFIG_LEDS_BCM6328 is not set +# CONFIG_LEDS_BCM6358 is not set +# CONFIG_LEDS_LM3530 is not set +# CONFIG_LEDS_LM3642 is not set +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_GPIO is not set +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_LP3952 is not set +# CONFIG_LEDS_LP5521 is not set +# CONFIG_LEDS_LP5523 is not set +# CONFIG_LEDS_LP5562 is not set +# CONFIG_LEDS_LP8501 is not set +# CONFIG_LEDS_LP8860 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_PCA963X is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set +# CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_TLC591XX is not set +# CONFIG_LEDS_LM355x is not set +# CONFIG_LEDS_IS31FL319X is not set +# CONFIG_LEDS_IS31FL32XX is not set + +# +# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) +# +# CONFIG_LEDS_BLINKM is not set +# CONFIG_LEDS_SYSCON is not set +# CONFIG_LEDS_USER is not set + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +# CONFIG_LEDS_TRIGGER_TIMER is not set +# CONFIG_LEDS_TRIGGER_ONESHOT is not set +# CONFIG_LEDS_TRIGGER_DISK is not set +# CONFIG_LEDS_TRIGGER_MTD is not set +# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_CPU is not set +# CONFIG_LEDS_TRIGGER_GPIO is not set +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_LEDS_TRIGGER_TRANSIENT is not set +# CONFIG_LEDS_TRIGGER_CAMERA is not set +# CONFIG_LEDS_TRIGGER_PANIC is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_EDAC_SUPPORT=y +CONFIG_EDAC=y +CONFIG_EDAC_LEGACY_SYSFS=y +# CONFIG_EDAC_DEBUG is not set +# CONFIG_EDAC_THUNDERX is not set +# CONFIG_EDAC_XGENE is not set +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set + +# +# DMABUF options +# +# CONFIG_SYNC_FILE is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_VIRT_DRIVERS is not set + +# +# Virtio drivers +# +# CONFIG_VIRTIO_PCI is not set +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +# CONFIG_HYPERV_TSCPAGE is not set +# CONFIG_STAGING is not set +# CONFIG_GOLDFISH is not set +# CONFIG_CHROME_PLATFORMS is not set +CONFIG_FBXGW7R_PLATFORM=y +CONFIG_FBXGW7R_SWITCH=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Common Clock Framework +# +# CONFIG_COMMON_CLK_VERSATILE is not set +# CONFIG_CLK_HSDK is not set +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI514 is not set +# CONFIG_COMMON_CLK_SI570 is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CDCE925 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_CLK_QORIQ is not set +CONFIG_COMMON_CLK_XGENE=y +# CONFIG_COMMON_CLK_NXP is not set +# CONFIG_COMMON_CLK_PXA is not set +# CONFIG_COMMON_CLK_PIC32 is not set +# CONFIG_COMMON_CLK_VC5 is not set +CONFIG_ARMADA_37XX_CLK=y +CONFIG_ARMADA_AP806_SYSCON=y +CONFIG_ARMADA_CP110_SYSCON=y +# CONFIG_HWSPINLOCK is not set + +# +# Clock Source drivers +# +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y +CONFIG_FSL_ERRATUM_A008585=y +CONFIG_HISILICON_ERRATUM_161010101=y +CONFIG_ARM64_ERRATUM_858921=y +# CONFIG_ARM_TIMER_SP804 is not set +# CONFIG_ATMEL_PIT is not set +# CONFIG_SH_TIMER_CMT is not set +# CONFIG_SH_TIMER_MTU2 is not set +# CONFIG_SH_TIMER_TMU is not set +# CONFIG_EM_TIMER_STI is not set +# CONFIG_MAILBOX is not set +# CONFIG_IOMMU_SUPPORT is not set + +# +# Remoteproc drivers +# +# CONFIG_REMOTEPROC is not set + +# +# Rpmsg drivers +# + +# +# SOC (System On Chip) specific Drivers +# + +# +# Amlogic SoC drivers +# + +# +# Broadcom SoC drivers +# +# CONFIG_SOC_BRCMSTB is not set + +# +# i.MX SoC drivers +# + +# +# Qualcomm SoC drivers +# +# CONFIG_SUNXI_SRAM is not set +# CONFIG_SOC_TI is not set +# CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +# CONFIG_MEMORY is not set +# CONFIG_IIO is not set +# CONFIG_NTB is not set +# CONFIG_VME_BUS is not set +# CONFIG_PWM is not set +CONFIG_IRQCHIP=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_MAX_NR=1 +CONFIG_ARM_GIC_V2M=y +CONFIG_ARM_GIC_V3=y +CONFIG_ARM_GIC_V3_ITS=y +CONFIG_MVEBU_GICP=y +CONFIG_MVEBU_ICU=y +CONFIG_MVEBU_ODMI=y +CONFIG_MVEBU_PIC=y +CONFIG_PARTITION_PERCPU=y +# CONFIG_IPACK_BUS is not set +CONFIG_RESET_CONTROLLER=y +# CONFIG_RESET_ATH79 is not set +# CONFIG_RESET_BERLIN is not set +# CONFIG_RESET_IMX7 is not set +# CONFIG_RESET_LANTIQ is not set +# CONFIG_RESET_LPC18XX is not set +# CONFIG_RESET_MESON is not set +# CONFIG_RESET_PISTACHIO is not set +# CONFIG_RESET_SOCFPGA is not set +# CONFIG_RESET_STM32 is not set +# CONFIG_RESET_SUNXI is not set +# CONFIG_RESET_TI_SYSCON is not set +# CONFIG_RESET_ZYNQ is not set +# CONFIG_RESET_TEGRA_BPMP is not set +# CONFIG_FMC is not set + +# +# PHY Subsystem +# +CONFIG_GENERIC_PHY=y +# CONFIG_PHY_XGENE is not set +# CONFIG_XDSL_PHY_API is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +CONFIG_PHY_MVEBU_CP110_COMPHY=y +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +CONFIG_PHY_UTMI_CP110=y +# CONFIG_POWERCAP is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +CONFIG_ARM_PMU=y +CONFIG_RAS=y + +# +# Android +# +# CONFIG_ANDROID is not set +# CONFIG_LIBNVDIMM is not set +CONFIG_DAX=y +CONFIG_NVMEM=y +# CONFIG_NVMEM_IGNORE_RO is not set +# CONFIG_STM is not set +# CONFIG_INTEL_TH is not set +# CONFIG_FPGA is not set + +# +# FSI support +# +# CONFIG_FSI is not set +CONFIG_TEE=y + +# +# TEE drivers +# +CONFIG_OPTEE=y + +# +# Firmware Drivers +# +CONFIG_ARM_PSCI_FW=y +# CONFIG_FIRMWARE_MEMMAP is not set +# CONFIG_FW_CFG_SYSFS is not set +CONFIG_HAVE_ARM_SMCCC=y +# CONFIG_GOOGLE_FIRMWARE is not set +# CONFIG_MESON_SM is not set + +# +# Tegra firmware driver +# +# CONFIG_ACPI is not set + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_FS_IOMAP=y +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +CONFIG_EXT4_FS=y +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set +# CONFIG_EXT4_ENCRYPTION is not set +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_XFS_FS=y +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_XFS_WARN is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_F2FS_FS is not set +# CONFIG_FS_DAX is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +# CONFIG_EXPORTFS_BLOCK_OPS is not set +CONFIG_FILE_LOCKING=y +CONFIG_MANDATORY_FILE_LOCKING=y +# CONFIG_FS_ENCRYPTION is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_FANOTIFY=y +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +# CONFIG_AUTOFS4_FS is not set +CONFIG_FUSE_FS=y +# CONFIG_CUSE is not set +# CONFIG_OVERLAY_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=850 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_DEFAULT_UTF8 is not set +CONFIG_NTFS_FS=y +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set +CONFIG_EXFAT_FS=y + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_PROC_CHILDREN is not set +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_TMPFS_XATTR is not set +# CONFIG_HUGETLBFS is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=y +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +CONFIG_HFS_FS=y +CONFIG_HFSPLUS_FS=y +# CONFIG_HFSPLUS_FS_POSIX_ACL is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +CONFIG_CRAMFS=y +CONFIG_SQUASHFS=y +# CONFIG_SQUASHFS_FILE_CACHE is not set +CONFIG_SQUASHFS_FILE_DIRECT=y +CONFIG_SQUASHFS_DECOMP_SINGLE=y +# CONFIG_SQUASHFS_DECOMP_MULTI is not set +# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set +# CONFIG_SQUASHFS_XATTR is not set +# CONFIG_SQUASHFS_ZLIB is not set +# CONFIG_SQUASHFS_LZ4 is not set +# CONFIG_SQUASHFS_LZO is not set +CONFIG_SQUASHFS_XZ=y +# CONFIG_SQUASHFS_ZSTD is not set +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_PSTORE=y +CONFIG_PSTORE_ZLIB_COMPRESS=y +# CONFIG_PSTORE_LZO_COMPRESS is not set +# CONFIG_PSTORE_LZ4_COMPRESS is not set +# CONFIG_PSTORE_CONSOLE is not set +# CONFIG_PSTORE_PMSG is not set +CONFIG_PSTORE_RAM=y +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V2=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_SWAP is not set +CONFIG_ROOT_NFS=y +CONFIG_NFSD=y +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set +CONFIG_NFSD_V4=y +# CONFIG_NFSD_BLOCKLAYOUT is not set +# CONFIG_NFSD_SCSILAYOUT is not set +# CONFIG_NFSD_FLEXFILELAYOUT is not set +# CONFIG_NFSD_FAULT_INJECTION is not set +CONFIG_GRACE_PERIOD=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set +CONFIG_HAVE_KVM_IRQCHIP=y +CONFIG_HAVE_KVM_IRQFD=y +CONFIG_HAVE_KVM_IRQ_ROUTING=y +CONFIG_HAVE_KVM_EVENTFD=y +CONFIG_KVM_MMIO=y +CONFIG_HAVE_KVM_MSI=y +CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y +CONFIG_KVM_VFIO=y +CONFIG_HAVE_KVM_ARCH_TLB_FLUSH_ALL=y +CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y +CONFIG_VIRTUALIZATION=y +CONFIG_KVM=y +CONFIG_KVM_ARM_HOST=y +CONFIG_KVM_ARM_PMU=y +CONFIG_VHOST_NET=y +CONFIG_VHOST_VSOCK=y +CONFIG_VHOST=y +# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_DYNAMIC_DEBUG is not set + +# +# Compile-time checks and compiler options +# +# CONFIG_DEBUG_INFO is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=2048 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_READABLE_ASM is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_PAGE_OWNER is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +CONFIG_ARCH_WANT_FRAME_POINTERS=y +CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_DEBUG_KERNEL=y + +# +# Memory Debugging +# +CONFIG_PAGE_EXTENSION=y +CONFIG_DEBUG_PAGEALLOC=y +CONFIG_DEBUG_PAGEALLOC_ENABLE_DEFAULT=y +CONFIG_PAGE_POISONING=y +CONFIG_PAGE_POISONING_NO_SANITY=y +# CONFIG_PAGE_POISONING_ZERO is not set +# CONFIG_DEBUG_RODATA_TEST is not set +CONFIG_DEBUG_OBJECTS=y +CONFIG_DEBUG_OBJECTS_SELFTEST=y +CONFIG_DEBUG_OBJECTS_FREE=y +CONFIG_DEBUG_OBJECTS_TIMERS=y +CONFIG_DEBUG_OBJECTS_WORK=y +CONFIG_DEBUG_OBJECTS_RCU_HEAD=y +CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER=y +CONFIG_DEBUG_OBJECTS_ENABLE_DEFAULT=1 +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_DEBUG_KMEMLEAK=y +CONFIG_DEBUG_KMEMLEAK_EARLY_LOG_SIZE=400 +# CONFIG_DEBUG_KMEMLEAK_TEST is not set +# CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF is not set +# CONFIG_DEBUG_STACK_USAGE is not set +CONFIG_DEBUG_VM=y +# CONFIG_DEBUG_VM_VMACACHE is not set +CONFIG_DEBUG_VM_RB=y +CONFIG_DEBUG_VM_PGFLAGS=y +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +# CONFIG_DEBUG_VIRTUAL is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_PER_CPU_MAPS is not set +CONFIG_HAVE_ARCH_KASAN=y +CONFIG_KASAN=y +CONFIG_KASAN_EXTRA=y +CONFIG_KASAN_OUTLINE=y +# CONFIG_KASAN_INLINE is not set +# CONFIG_TEST_KASAN is not set +CONFIG_ARCH_HAS_KCOV=y +# CONFIG_KCOV is not set +CONFIG_DEBUG_SHIRQ=y + +# +# Debug Lockups and Hangs +# +# CONFIG_SOFTLOCKUP_DETECTOR is not set +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 +CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=1 +# CONFIG_WQ_WATCHDOG is not set +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=10 +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHED_INFO is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_SCHED_STACK_END_CHECK is not set +CONFIG_DEBUG_TIMEKEEPING=y + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +CONFIG_DEBUG_ATOMIC_SLEEP=y +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_LOCK_TORTURE_TEST is not set +# CONFIG_WW_MUTEX_SELFTEST is not set +CONFIG_STACKTRACE=y +# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_KOBJECT_RELEASE is not set +CONFIG_HAVE_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_LIST=y +CONFIG_DEBUG_PI_LIST=y +CONFIG_DEBUG_SG=y +CONFIG_DEBUG_NOTIFIERS=y +# CONFIG_DEBUG_CREDENTIALS is not set + +# +# RCU Debugging +# +# CONFIG_PROVE_RCU is not set +# CONFIG_TORTURE_TEST is not set +# CONFIG_RCU_PERF_TEST is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=21 +# CONFIG_RCU_TRACE is not set +# CONFIG_RCU_EQS_DEBUG is not set +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_DMA_API_DEBUG is not set + +# +# Runtime Testing +# +# CONFIG_LKDTM is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_TEST_SORT is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_RBTREE_TEST is not set +# CONFIG_INTERVAL_TREE_TEST is not set +# CONFIG_PERCPU_TEST is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_ASYNC_RAID6_TEST is not set +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_BITMAP is not set +# CONFIG_TEST_UUID is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_HASH is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_USER_COPY is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_SYSCTL is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_TEST_STATIC_KEYS is not set +# CONFIG_TEST_KMOD is not set +CONFIG_MEMTEST=y +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +CONFIG_UBSAN=y +CONFIG_UBSAN_SANITIZE_ALL=y +# CONFIG_UBSAN_ALIGNMENT is not set +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y +# CONFIG_STRICT_DEVMEM is not set +# CONFIG_ARM64_PTDUMP_CORE is not set +# CONFIG_ARM64_PTDUMP_DEBUGFS is not set +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set +# CONFIG_DEBUG_WX is not set +# CONFIG_DEBUG_ALIGN_RODATA is not set +# CONFIG_ARM64_RELOC_TEST is not set +# CONFIG_CORESIGHT is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +# CONFIG_HARDENED_USERCOPY is not set +# CONFIG_FORTIFY_SOURCE is not set +# CONFIG_STATIC_USERMODEHELPER is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_XOR_BLOCKS=y +CONFIG_ASYNC_CORE=y +CONFIG_ASYNC_MEMCPY=y +CONFIG_ASYNC_XOR=y +CONFIG_ASYNC_PQ=y +CONFIG_ASYNC_RAID6_RECOV=y +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_KPP2=y +CONFIG_CRYPTO_KPP=y +CONFIG_CRYPTO_ACOMP2=y +# CONFIG_CRYPTO_RSA is not set +# CONFIG_CRYPTO_DH is not set +CONFIG_CRYPTO_ECDH=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_USER is not set +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +# CONFIG_CRYPTO_PCRYPT is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_MCRYPTD is not set +CONFIG_CRYPTO_AUTHENC=y +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_ECHAINIV=y + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTR=y +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_KEYWRAP is not set + +# +# Hash modes +# +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_CRCT10DIF is not set +CONFIG_CRYPTO_GHASH=y +# CONFIG_CRYPTO_POLY1305 is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_SHA3 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_AES_TI is not set +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_CHACHA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_DRBG_HMAC=y +# CONFIG_CRYPTO_DRBG_HASH is not set +# CONFIG_CRYPTO_DRBG_CTR is not set +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_JITTERENTROPY=y +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_AEAD is not set +# CONFIG_CRYPTO_HW is not set + +# +# Certificates for signature checking +# +# CONFIG_ARM64_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_RAID6_PQ=y +CONFIG_BITREVERSE=y +CONFIG_HAVE_ARCH_BITREVERSE=y +CONFIG_RATIONAL=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IO=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC4 is not set +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +# CONFIG_CRC8 is not set +CONFIG_AUDIT_GENERIC=y +CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_XZ_DEC=y +# CONFIG_XZ_DEC_X86 is not set +# CONFIG_XZ_DEC_POWERPC is not set +# CONFIG_XZ_DEC_IA64 is not set +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +# CONFIG_XZ_DEC_SPARC is not set +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_REED_SOLOMON=y +CONFIG_REED_SOLOMON_ENC8=y +CONFIG_REED_SOLOMON_DEC8=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +# CONFIG_DMA_NOOP_OPS is not set +# CONFIG_DMA_VIRT_OPS is not set +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_GLOB=y +# CONFIG_GLOB_SELFTEST is not set +CONFIG_NLATTR=y +# CONFIG_CORDIC is not set +# CONFIG_DDR is not set +# CONFIG_IRQ_POLL is not set +CONFIG_LIBFDT=y +CONFIG_OID_REGISTRY=y +# CONFIG_SG_SPLIT is not set +CONFIG_SG_POOL=y +CONFIG_ARCH_HAS_SG_CHAIN=y +CONFIG_STACKDEPOT=y +CONFIG_SBITMAP=y +# CONFIG_STRING_SELFTEST is not set +CONFIG_ARCH_HAS_FBXSERIAL=y +CONFIG_FBXSERIAL=y diff -Nruw linux-4.14.127-fbx/drivers/fbxgpio./Kconfig linux-4.14.127-fbx/drivers/fbxgpio/Kconfig --- linux-4.14.127-fbx/drivers/fbxgpio./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/drivers/fbxgpio/Kconfig 2019-01-14 15:16:32.266060582 +0100 @@ -0,0 +1,7 @@ +config FREEBOX_GPIO + tristate "Freebox GPIO control interface" + default n + +config FREEBOX_GPIO_DT + tristate "Freebox GPIO DT binding." + default n diff -Nruw linux-4.14.127-fbx/drivers/fbxgpio./Makefile linux-4.14.127-fbx/drivers/fbxgpio/Makefile --- linux-4.14.127-fbx/drivers/fbxgpio./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/drivers/fbxgpio/Makefile 2019-01-14 15:16:32.266060582 +0100 @@ -0,0 +1,2 @@ +obj-$(CONFIG_FREEBOX_GPIO) += fbxgpio_core.o +obj-$(CONFIG_FREEBOX_GPIO_DT) += fbxgpio_dt.o diff -Nruw linux-4.14.127-fbx/drivers/fbxgpio./fbxgpio_core.c linux-4.14.127-fbx/drivers/fbxgpio/fbxgpio_core.c --- linux-4.14.127-fbx/drivers/fbxgpio./fbxgpio_core.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/drivers/fbxgpio/fbxgpio_core.c 2019-02-15 14:29:37.730639363 +0100 @@ -0,0 +1,361 @@ +#include +#include +#include +#include +#include +#include +#include +#include + +#define PFX "fbxgpio_core: " + +/* #define DEBUG */ +#ifdef DEBUG +#define dprint(Fmt, Arg...) printk(PFX Fmt, Arg) +#else +#define dprint(Fmt, Arg...) do { } while (0) +#endif + +static struct class *fbxgpio_class; + +/* + * retrieval of a struct fbxgpio_pin from a phandle in the device + * tree. + */ +struct fbxgpio_of_mach_data { + struct fbxgpio_pin *match; + struct device_node *np; +}; + +static int match_fbxgpio_of_node(struct device *dev, void *data) +{ + struct fbxgpio_of_mach_data *md = data; + struct fbxgpio_pin *pin = dev_get_drvdata(dev); + + if (pin->of_node == md->np) { + md->match = pin; + return 1; + } + return 0; +} + +struct fbxgpio_pin *fbxgpio_of_get(struct device_node *np, const char *propname, + int index) +{ + struct fbxgpio_of_mach_data md; + + /* + * get the pin device_node. + */ + md.match = NULL; + md.np = of_parse_phandle(np, propname, index); + if (!md.np) + return ERR_PTR(-ENOENT); + + /* + * find the struct fbxgpio_pin behind that device_node. + */ + class_for_each_device(fbxgpio_class, NULL, &md, + match_fbxgpio_of_node); + + return md.match ? md.match : ERR_PTR(-ENOENT); +} +EXPORT_SYMBOL(fbxgpio_of_get); + +/* + * show direction in for gpio associated with class_device dev. + */ +static ssize_t show_direction(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fbxgpio_pin *p; + int dir, ret = 0; + + p = dev_get_drvdata(dev); + + if (p->ops->get_direction) + dir = p->ops->get_direction(p->pin_num); + else + dir = p->direction; + + switch (dir) { + case GPIO_DIR_IN: + ret += sprintf(buf, "input\n"); + break; + case GPIO_DIR_OUT: + ret += sprintf(buf, "output\n"); + break; + default: + ret += sprintf(buf, "unknown\n"); + break; + } + return ret; +} + +/* + * store direction. return -EINVAL if direction string is bad. return + * -EPERM if flag FBXGPIO_PIN_DIR_RW is set in flags. + */ +static ssize_t store_direction(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + int dir; + struct fbxgpio_pin *p; + int match_len = 0; + int i, ret; + static const char *word_match[] = { + [GPIO_DIR_IN] = "input", + [GPIO_DIR_OUT] = "output", + }; + + if (*buf == ' ' || *buf == '\t' || *buf == '\r' || *buf == '\n') + /* silently eat any spaces/tab/linefeed/carriagereturn */ + return 1; + + p = dev_get_drvdata(dev); + if (!(p->flags & FBXGPIO_PIN_DIR_RW)) { + dprint("pin %s direction is read only.\n", p->pin_name); + return -EPERM; + } + dir = 0; + for (i = 0; i < 2; ++i) { + if (size >= strlen(word_match[i]) && + !strncmp(buf, word_match[i], strlen(word_match[i]))) { + dir = i; + match_len = strlen(word_match[i]); + break ; + } + } + if (i == 2) + return -EINVAL; + + ret = p->ops->set_direction(p->pin_num, dir); + if (ret) + return ret; + p->direction = dir; + + return match_len; +} + +/* + * show input data for input gpio pins. + */ +static ssize_t show_datain(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int val; + struct fbxgpio_pin *p; + + p = dev_get_drvdata(dev); + if (p->direction == GPIO_DIR_OUT) + return -EINVAL; + val = p->ops->get_datain(p->pin_num); + + if (p->flags & FBXGPIO_PIN_REVERSE_POL) + val = 1 - val; + return sprintf(buf, "%i\n", val); +} + +/* + * show output data for output gpio pins. + */ +static ssize_t show_dataout(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int val; + struct fbxgpio_pin *p; + + p = dev_get_drvdata(dev); + if (p->direction == GPIO_DIR_IN) + return -EINVAL; + if (p->ops->get_dataout) + val = p->ops->get_dataout(p->pin_num); + else + val = p->cur_dataout; + + if (p->flags & FBXGPIO_PIN_REVERSE_POL) + val = 1 - val; + return sprintf(buf, "%i\n", val); +} + +/* + * store new dataout value for output gpio pins. + */ +static ssize_t store_dataout(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + int val; + struct fbxgpio_pin *p; + + if (*buf == ' ' || *buf == '\t' || *buf == '\r' || *buf == '\n') + /* silently eat any spaces/tab/linefeed/carriagereturn */ + return 1; + + p = dev_get_drvdata(dev); + + if (p->direction != GPIO_DIR_OUT) + return -EINVAL; + + switch (*buf) { + case '0': + val = 0; + break ; + case '1': + val = 1; + break ; + default: + return -EINVAL; + } + + p->cur_dataout = val; + + if (p->flags & FBXGPIO_PIN_REVERSE_POL) + val = 1 - val; + p->ops->set_dataout(p->pin_num, val); + return 1; +} + +/* + * show pin number associated with gpio pin. + */ +static ssize_t show_pinnum(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fbxgpio_pin *p; + + p = dev_get_drvdata(dev); + return sprintf(buf, "%i\n", p->pin_num); +} + +/* + * attribute list associated with each class device. + */ +static struct device_attribute gpio_attributes[] = { + __ATTR(direction, 0600, show_direction, store_direction), + __ATTR(data_in, 0400, show_datain, NULL), + __ATTR(data_out, 0600, show_dataout, store_dataout), + __ATTR(pin_num, 0400, show_pinnum, NULL), +}; + +static int fbxgpio_register_pin(struct platform_device *ppdev, + struct fbxgpio_pin *pin) +{ + struct device *dev; + int i, ret; + + dprint("registering pin %s\n", pin->pin_name); + + /* ensure ops is valid */ + if (!pin->ops) { + printk(KERN_ERR PFX "no operation set for pin %s\n", + pin->pin_name); + return -EINVAL; + } + + dev = device_create(fbxgpio_class, &ppdev->dev, 0, pin, + "%s", pin->pin_name); + if (IS_ERR(dev)) + return PTR_ERR(dev); + + for (i = 0; i < ARRAY_SIZE(gpio_attributes); i++) { + ret = device_create_file(dev, &gpio_attributes[i]); + if (ret) + goto err_out; + } + + /* ensure pin direction matches hardware state */ + if (pin->ops->get_direction && + pin->direction != pin->ops->get_direction(pin->pin_num)) { + printk(KERN_WARNING PFX "pin %s default direction does not " + "match current hardware state, fixing.\n", + pin->pin_name); + pin->ops->set_direction(pin->pin_num, pin->direction); + } + pin->dev = dev; + return 0; + +err_out: + for (; i >= 0; i--) + device_remove_file(dev, &gpio_attributes[i]); + device_unregister(dev); + return ret; +} + +static void fbxgpio_unregister_pin(struct fbxgpio_pin *pin) +{ + struct device *dev; + int i; + + dprint("unregistering pin %s\n", pin->pin_name); + dev = pin->dev; + pin->dev = NULL; + + for (i = 0; i < ARRAY_SIZE(gpio_attributes); i++) + device_remove_file(dev, &gpio_attributes[i]); + device_unregister(dev); +} + +static int fbxgpio_platform_probe(struct platform_device *pdev) +{ + struct fbxgpio_pin *p; + int err = 0; + + p = pdev->dev.platform_data; + while (p->pin_name) { + err = fbxgpio_register_pin(pdev, p); + if (err) + return err; + ++p; + } + return 0; +} + +static int fbxgpio_platform_remove(struct platform_device *pdev) +{ + struct fbxgpio_pin *p; + + p = pdev->dev.platform_data; + while (p->pin_name) { + fbxgpio_unregister_pin(p); + ++p; + } + return 0; +} + +static struct platform_driver fbxgpio_platform_driver = +{ + .probe = fbxgpio_platform_probe, + .remove = fbxgpio_platform_remove, + .driver = { + .name = "fbxgpio", + } +}; + +static int __init fbxgpio_init(void) +{ + int ret; + + fbxgpio_class = class_create(THIS_MODULE, "fbxgpio"); + if (IS_ERR(fbxgpio_class)) + return PTR_ERR(fbxgpio_class); + + ret = platform_driver_register(&fbxgpio_platform_driver); + if (ret) { + printk(KERN_ERR PFX "unable to register fbxgpio driver.\n"); + class_destroy(fbxgpio_class); + return ret; + } + return 0; +} + +static void __exit fbxgpio_exit(void) +{ + platform_driver_unregister(&fbxgpio_platform_driver); + class_destroy(fbxgpio_class); +} + +subsys_initcall(fbxgpio_init); +module_exit(fbxgpio_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Nicolas Schichan "); diff -Nruw linux-4.14.127-fbx/drivers/fbxgpio./fbxgpio_dt.c linux-4.14.127-fbx/drivers/fbxgpio/fbxgpio_dt.c --- linux-4.14.127-fbx/drivers/fbxgpio./fbxgpio_dt.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/drivers/fbxgpio/fbxgpio_dt.c 2019-02-15 14:29:37.730639363 +0100 @@ -0,0 +1,264 @@ +/* + * fbxgpio_dt.c for fbxgpio + * Created by on Tue Aug 1 14:01:01 2017 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static atomic_t last_id = ATOMIC_INIT(0); + +/* + * fbxgpio driver fetching gpios names and configuration from + * device-tree. + */ + +struct fbxgpio_dt_priv { + struct fbxgpio_pin *pins; + unsigned int npins; + + /* dynamically created platform_device for fbxgpio_core */ + struct platform_device *top_pdev; +}; + + +/* + * small shim layer for gpiolib <-> fbxgpio_operations. + * + * gpio direction change is unsupported, does userspace really need + * it? + */ +static int fbxgpio_dt_get_data(int gpio) +{ + return gpio_get_value_cansleep(gpio); +} + +static void fbxgpio_dt_set_dataout(int gpio, int value) +{ + gpio_set_value_cansleep(gpio, value); +} + +static int fbxgpio_dt_set_direction(int gpio, int dir) +{ + if (dir == GPIO_DIR_OUT) + return gpio_direction_output(gpio, 0); + else + return gpio_direction_input(gpio); +} + +static const struct fbxgpio_operations fbxgpio_dt_ops = { + .get_datain = fbxgpio_dt_get_data, + .get_dataout = fbxgpio_dt_get_data, + .set_dataout = fbxgpio_dt_set_dataout, + .set_direction = fbxgpio_dt_set_direction, +}; + +/* + * fill an fbxgpio_pin with the configuration found in a device tree + * node. + * + * required properties are: + * - gpio: a phandle to a standard linux gpio. + * + * - the name of the node: the name of the gpio as it will appear under + * /sys/class/fbxgpio/ + * + * - //: how to declare gpio and + * actually setup it unless no-claim is given + * + * - : just declare gpio, but don't request & setup it + */ +static int fbxgpio_dt_fill_gpio(struct platform_device *pdev, + struct device_node *np, + struct fbxgpio_pin *pin) +{ + enum of_gpio_flags flags; + int error; + + error = of_property_read_string(np, "name", &pin->pin_name); + if (error) { + dev_err(&pdev->dev, "gpio has no name.\n"); + return error; + } + + pin->pin_num = of_get_named_gpio_flags(np, "gpio", 0, &flags); + if (pin->pin_num < 0) { + if (pin->pin_num != -EPROBE_DEFER) + dev_err(&pdev->dev, + "unable to get gpio desc for %s: %d.\n", + pin->pin_name, pin->pin_num); + return pin->pin_num; + } + + if (of_property_read_bool(np, "input")) { + pin->direction = GPIO_DIR_IN; + } else if (of_property_read_bool(np, "output-low")) { + pin->direction = GPIO_DIR_OUT; + pin->cur_dataout = 0; + } else if (of_property_read_bool(np, "output-high")) { + pin->direction = GPIO_DIR_OUT; + pin->cur_dataout = 1; + } else { + dev_err(&pdev->dev, + "no state specified for %s\n", + pin->pin_name); + return -EINVAL; + } + + if (flags & OF_GPIO_ACTIVE_LOW) { + pin->flags |= FBXGPIO_PIN_REVERSE_POL; + if (pin->direction == GPIO_DIR_OUT) + pin->cur_dataout = 1 - pin->cur_dataout; + } + + if (!of_property_read_bool(np, "no-claim")) { + error = gpio_request(pin->pin_num, "fbxgpio-dt"); + if (error) { + dev_err(&pdev->dev, "unable to request gpio%d (%s): %d\n", + pin->pin_num, pin->pin_name, error); + return error; + } + pin->claimed = true; + + if (pin->direction == GPIO_DIR_OUT) + gpio_direction_output(pin->pin_num, pin->cur_dataout); + else + gpio_direction_input(pin->pin_num); + } + + if (of_property_read_bool(np, "bidir")) + pin->flags = FBXGPIO_PIN_DIR_RW; + + pin->of_node = np; + pin->ops = &fbxgpio_dt_ops; + return 0; +} + +static int fbxgpio_dt_probe(struct platform_device *pdev) +{ + struct fbxgpio_dt_priv *priv; + struct device_node *fbxgpio_node; + u32 cur_gpio; + int error = 0; + size_t priv_alloc_size; + int i; + + priv = devm_kzalloc(&pdev->dev, sizeof (*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + dev_set_drvdata(&pdev->dev, priv); + + /* + * first pass to get the number of struct fbxgpio_pin to + * allocate. + */ + for_each_available_child_of_node(pdev->dev.of_node, fbxgpio_node) { + ++priv->npins; + } + + /* + * allocate pins: use npins + 1 for zeroed end sentinel. + */ + priv_alloc_size = (priv->npins + 1) * sizeof (struct fbxgpio_pin); + priv->pins = devm_kzalloc(&pdev->dev, priv_alloc_size, GFP_KERNEL); + if (!priv->pins) + return -ENOMEM; + + /* + * second pass to fill the priv->pins array. + */ + cur_gpio = 0; + for_each_available_child_of_node(pdev->dev.of_node, fbxgpio_node) { + error = fbxgpio_dt_fill_gpio(pdev, fbxgpio_node, + &priv->pins[cur_gpio]); + if (error) + goto out_free_gpios; + ++cur_gpio; + } + + dev_info(&pdev->dev, "%u gpios.\n", priv->npins); + + /* + * create and register a platform device for fbxgpio_core. + */ + priv->top_pdev = platform_device_register_data(&pdev->dev, + "fbxgpio", + atomic_inc_return(&last_id), + priv->pins, + priv_alloc_size); + + if (IS_ERR(priv->top_pdev)) { + dev_err(&pdev->dev, "unable to register fbxgpio platform " + "device: %ld\n", PTR_ERR(priv->top_pdev)); + return PTR_ERR(priv->top_pdev); + } + + for (i = 0; i < priv->npins; i++) { + struct fbxgpio_pin *pin = &priv->pins[i]; + + if (pin->direction == GPIO_DIR_OUT) + dev_dbg(&pdev->dev, + "%sgpio %d (%s) is output, default %d\n", + pin->claimed ? "unclaimed " : "", + pin->pin_num, pin->pin_name, pin->cur_dataout); + else + dev_dbg(&pdev->dev, + "%sgpio %d (%s) is input\n", + pin->claimed ? "unclaimed " : "", + pin->pin_num, pin->pin_name); + } + + return 0; + +out_free_gpios: + while (cur_gpio) { + --cur_gpio; + if (priv->pins[cur_gpio].claimed) + gpio_free(priv->pins[cur_gpio].pin_num); + } + return error; +} + +static int fbxgpio_dt_remove(struct platform_device *pdev) +{ + struct fbxgpio_dt_priv *priv = dev_get_drvdata(&pdev->dev); + unsigned int i; + + platform_device_unregister(priv->top_pdev); + + for (i = 0; i < priv->npins; ++i) { + if (priv->pins[i].claimed) + gpio_free(priv->pins[i].pin_num); + } + + return 0; +} + +static const struct of_device_id fbxgpio_dt_of_match_table[] = { + { .compatible = "fbx,fbxgpio" }, + { }, +}; +MODULE_DEVICE_TABLE(of, fbxgpio_dt_of_match_table); + +static struct platform_driver fbxgpio_dt_platform_driver = { + .probe = fbxgpio_dt_probe, + .remove = fbxgpio_dt_remove, + .driver = { + .name = "fbxgpio-dt", + .of_match_table = fbxgpio_dt_of_match_table, + }, +}; + +module_platform_driver(fbxgpio_dt_platform_driver); + +MODULE_AUTHOR("Nicolas Schichan "); +MODULE_DESCRIPTION("DT Freebox GPIO Driver"); +MODULE_LICENSE("GPL v2"); diff -Nruw linux-4.14.127-fbx/drivers/fbxjtag./Kconfig linux-4.14.127-fbx/drivers/fbxjtag/Kconfig --- linux-4.14.127-fbx/drivers/fbxjtag./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/drivers/fbxjtag/Kconfig 2019-02-15 14:29:37.730639363 +0100 @@ -0,0 +1,3 @@ +config FREEBOX_JTAG + tristate "Freebox JTAG control interface" + default n diff -Nruw linux-4.14.127-fbx/drivers/fbxjtag./Makefile linux-4.14.127-fbx/drivers/fbxjtag/Makefile --- linux-4.14.127-fbx/drivers/fbxjtag./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/drivers/fbxjtag/Makefile 2019-02-15 14:29:37.730639363 +0100 @@ -0,0 +1 @@ +obj-$(CONFIG_FREEBOX_JTAG) += fbxjtag.o diff -Nruw linux-4.14.127-fbx/drivers/fbxjtag./fbxjtag.c linux-4.14.127-fbx/drivers/fbxjtag/fbxjtag.c --- linux-4.14.127-fbx/drivers/fbxjtag./fbxjtag.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/drivers/fbxjtag/fbxjtag.c 2019-02-15 14:29:37.730639363 +0100 @@ -0,0 +1,1122 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PFX "fbxjtag: " + +static struct class *fbxjtag_class; + +static enum jtag_state jtag_transitions[][2] = { + [JTAG_STATE_UNDEF] = { JTAG_STATE_UNDEF , JTAG_STATE_UNDEF }, + [JTAG_STATE_TEST_LOGIC_RESET] = { JTAG_STATE_RUN_TEST_IDLE , JTAG_STATE_TEST_LOGIC_RESET }, + [JTAG_STATE_RUN_TEST_IDLE] = { JTAG_STATE_RUN_TEST_IDLE , JTAG_STATE_SELECT_DR }, + + [JTAG_STATE_SELECT_DR] = { JTAG_STATE_CAPTURE_DR , JTAG_STATE_SELECT_IR }, + [JTAG_STATE_CAPTURE_DR] = { JTAG_STATE_SHIFT_DR , JTAG_STATE_EXIT1_DR }, + [JTAG_STATE_SHIFT_DR] = { JTAG_STATE_SHIFT_DR , JTAG_STATE_EXIT1_DR }, + [JTAG_STATE_EXIT1_DR] = { JTAG_STATE_PAUSE_DR , JTAG_STATE_UPDATE_DR }, + [JTAG_STATE_PAUSE_DR] = { JTAG_STATE_PAUSE_DR , JTAG_STATE_EXIT2_DR }, + [JTAG_STATE_EXIT2_DR] = { JTAG_STATE_SHIFT_DR , JTAG_STATE_UPDATE_DR }, + [JTAG_STATE_UPDATE_DR] = { JTAG_STATE_RUN_TEST_IDLE , JTAG_STATE_SELECT_DR }, + + [JTAG_STATE_SELECT_IR] = { JTAG_STATE_CAPTURE_IR , JTAG_STATE_TEST_LOGIC_RESET }, + [JTAG_STATE_CAPTURE_IR] = { JTAG_STATE_SHIFT_IR , JTAG_STATE_EXIT1_IR }, + [JTAG_STATE_SHIFT_IR] = { JTAG_STATE_SHIFT_IR , JTAG_STATE_EXIT1_IR }, + [JTAG_STATE_EXIT1_IR] = { JTAG_STATE_PAUSE_IR , JTAG_STATE_UPDATE_IR }, + [JTAG_STATE_PAUSE_IR] = { JTAG_STATE_PAUSE_IR , JTAG_STATE_EXIT2_IR }, + [JTAG_STATE_EXIT2_IR] = { JTAG_STATE_SHIFT_IR , JTAG_STATE_UPDATE_IR }, + [JTAG_STATE_UPDATE_IR] = { JTAG_STATE_RUN_TEST_IDLE , JTAG_STATE_SELECT_DR }, +}; + + +static char *debug_state_str[] = { + [JTAG_STATE_UNDEF] = "undef", + [JTAG_STATE_TEST_LOGIC_RESET] = "Test logic reset", + [JTAG_STATE_RUN_TEST_IDLE] = "Run test idle", + [JTAG_STATE_SELECT_DR] = "Select DR", + [JTAG_STATE_CAPTURE_DR] = "Capture DR", + [JTAG_STATE_SHIFT_DR] = "Shift DR", + [JTAG_STATE_EXIT1_DR] = "Exit 1 DR", + [JTAG_STATE_PAUSE_DR] = "Pause DR", + [JTAG_STATE_EXIT2_DR] = "Exit 2 DR", + [JTAG_STATE_UPDATE_DR] = "Update DR", + [JTAG_STATE_SELECT_IR] = "Select IR", + [JTAG_STATE_CAPTURE_IR] = "Capture IR", + [JTAG_STATE_SHIFT_IR] = "Shift IR", + [JTAG_STATE_EXIT1_IR] = "Exit 1 IR", + [JTAG_STATE_PAUSE_IR] = "Pause IR", + [JTAG_STATE_EXIT2_IR] = "Exit 2 IR", + [JTAG_STATE_UPDATE_IR] = "Update IR", +}; + +static char *jtag_state_str(enum jtag_state state) { + if (state < JTAG_STATE_UNDEF || state >= JTAG_STATE_MAX) + return "invalid"; + + return debug_state_str[state]; +} + +#define DEBUG_STATE(jtag) printk(KERN_INFO PFX "new state: %s\n", jtag_state_str((jtag)->state)) + +static void set_tms(struct fbxjtag_data *jtag, int val) +{ + struct fbxgpio_pin *tms; + + tms = jtag->gpios.tms; + tms->ops->set_dataout(tms->pin_num, val); + jtag->last_tms_dataout = val; +} + +static void set_tdi(struct fbxjtag_data *jtag, int val) +{ + struct fbxgpio_pin *tdi; + + tdi = jtag->gpios.tdi; + tdi->ops->set_dataout(tdi->pin_num, val); +} + +static int get_tdo(struct fbxjtag_data *jtag) +{ + struct fbxgpio_pin *tdo; + + tdo = jtag->gpios.tdo; + return tdo->ops->get_datain(tdo->pin_num); +} + +static void tck_pulse(struct fbxjtag_data *jtag) +{ + struct fbxgpio_pin *tck; + struct fbxgpio_pin *tms; + int tms_val, tdo_val; + + tms = jtag->gpios.tms; + tck = jtag->gpios.tck; + + + // rising edge + tck->ops->set_dataout(tck->pin_num, 1); + ndelay(jtag->clock_delay); + + // update state + tms_val = jtag->last_tms_dataout; + + // read tdo + if (jtag->state == JTAG_STATE_SHIFT_DR) { + tdo_val = get_tdo(jtag); + jtag->dr_buf[jtag->dr_w] = tdo_val + '0'; + jtag->dr_w = (jtag->dr_w + 1) % JTAG_BUF_SIZE; + } + + if (jtag->state == JTAG_STATE_UNDEF) { + if (tms_val == 1) { + jtag->nb_reset++; + if (jtag->nb_reset >= 5) { + jtag->state = JTAG_STATE_TEST_LOGIC_RESET; + } + } else { + jtag->nb_reset = 0; + } + } else { + jtag->state = jtag_transitions[jtag->state][tms_val]; + } + + // falling edge + tck->ops->set_dataout(tck->pin_num, 0); + ndelay(jtag->clock_delay); +} + +static void set_tms_pulse(struct fbxjtag_data *jtag, int tms) +{ + set_tms(jtag, tms); + tck_pulse(jtag); +} + +static void set_tms_tdi_pulse(struct fbxjtag_data *jtag, int tms, int tdi) +{ + set_tms(jtag, tms); + set_tdi(jtag, tdi); + tck_pulse(jtag); +} + +static int set_tms_get_tdo_pulse(struct fbxjtag_data *jtag, int tms) +{ + set_tms(jtag, tms); + tck_pulse(jtag); + return get_tdo(jtag); +} + +static void reset_state(struct fbxjtag_data *jtag) +{ + int i; + + for (i = 0; i < JTAG_RESET_STEPS; ++i) + set_tms_pulse(jtag, 1); + jtag->state = JTAG_STATE_TEST_LOGIC_RESET; +} + +static void goto_sub_state(struct fbxjtag_data *jtag, + enum jtag_state new_state) { + + enum jtag_sub_state cur_sub = jtag->state & JTAG_SUB_STATE_MASK; + enum jtag_sub_state new_sub = new_state & JTAG_SUB_STATE_MASK; + + switch(cur_sub) { + case JTAG_SUB_STATE_SELECT: + switch(new_sub) { + case JTAG_SUB_STATE_CAPTURE: + set_tms_pulse(jtag, 0); + // now in CAPTURE + break; + case JTAG_SUB_STATE_SHIFT: + set_tms_pulse(jtag, 0); + // now in CAPTURE + set_tms_pulse(jtag, 0); + // now in SHIFT + break; + case JTAG_SUB_STATE_EXIT1: + set_tms_pulse(jtag, 0); + // now in CAPTURE + set_tms_pulse(jtag, 1); + // now in EXIT1 + break; + case JTAG_SUB_STATE_PAUSE: + set_tms_pulse(jtag, 0); + // now in CAPTURE + set_tms_pulse(jtag, 1); + // now in EXIT1 + set_tms_pulse(jtag, 0); + // now in PAUSE + break; + case JTAG_SUB_STATE_EXIT2: + set_tms_pulse(jtag, 0); + // now in CAPTURE + set_tms_pulse(jtag, 1); + // now in EXIT1 + set_tms_pulse(jtag, 0); + // now in PAUSE + set_tms_pulse(jtag, 1); + // now in EXIT2 + break; + case JTAG_SUB_STATE_UPDATE: + set_tms_pulse(jtag, 0); + // now in CAPTURE + set_tms_pulse(jtag, 1); + // now in EXIT1 + set_tms_pulse(jtag, 1); + // now in UPDATE + break; + case JTAG_SUB_STATE_SELECT: + default: + // stay in SELECT + break; + } + break; + + case JTAG_SUB_STATE_CAPTURE: + case JTAG_SUB_STATE_SHIFT: + switch(new_sub) { + case JTAG_SUB_STATE_SELECT: + set_tms_pulse(jtag, 1); + // now in EXIT1 + set_tms_pulse(jtag, 1); + // now in UPDATE + set_tms_pulse(jtag, 1); + // now in SELECT-DR + if (JTAG_STATE_IN_IR(new_state)) { + // on more 1 to go to select IR + set_tms_pulse(jtag, 1); + // now in SELECT-IR + } + break; + case JTAG_SUB_STATE_SHIFT: + set_tms_pulse(jtag, 0); + // now in SHIFT + break; + case JTAG_SUB_STATE_EXIT1: + set_tms_pulse(jtag, 1); + // now in EXIT1 + break; + case JTAG_SUB_STATE_PAUSE: + set_tms_pulse(jtag, 1); + // now in EXIT1 + set_tms_pulse(jtag, 0); + // now in PAUSE + break; + case JTAG_SUB_STATE_EXIT2: + set_tms_pulse(jtag, 1); + // now in EXIT1 + set_tms_pulse(jtag, 0); + // now in PAUSE + set_tms_pulse(jtag, 1); + // now in EXIT2 + break; + case JTAG_SUB_STATE_UPDATE: + set_tms_pulse(jtag, 1); + // now in EXIT1 + set_tms_pulse(jtag, 1); + // now in UPDATE + break; + case JTAG_SUB_STATE_CAPTURE: + if (cur_sub == JTAG_SUB_STATE_SHIFT) { + goto_sub_state(jtag, + (new_state & JTAG_STATE_MASK) | JTAG_SUB_STATE_SELECT); + goto_sub_state(jtag, new_state); + } + break; + default: + // stay in current state + break; + } + break; + + case JTAG_SUB_STATE_EXIT1: + switch(new_sub) { + case JTAG_SUB_STATE_SELECT: + set_tms_pulse(jtag, 1); + // now in UPDATE + set_tms_pulse(jtag, 1); + // now in SELECT-DR + if (JTAG_STATE_IN_IR(new_state)) { + // on more 1 to go to select IR + set_tms_pulse(jtag, 1); + // now in SELECT-IR + } + break; + case JTAG_SUB_STATE_SHIFT: + set_tms_pulse(jtag, 0); + // now in PAUSE + set_tms_pulse(jtag, 1); + // now in EXIT2 + set_tms_pulse(jtag, 0); + // now in SHIFT + break; + case JTAG_SUB_STATE_PAUSE: + set_tms_pulse(jtag, 0); + // now in PAUSE + break; + case JTAG_SUB_STATE_EXIT2: + set_tms_pulse(jtag, 0); + // now in PAUSE + set_tms_pulse(jtag, 1); + // now in EXIT2 + break; + case JTAG_SUB_STATE_UPDATE: + set_tms_pulse(jtag, 1); + // now in UPDATE + break; + case JTAG_SUB_STATE_CAPTURE: + goto_sub_state(jtag, + (new_state & JTAG_STATE_MASK) | JTAG_SUB_STATE_SELECT); + goto_sub_state(jtag, new_state); + break; + default: + // stay in current state + break; + } + break; + + case JTAG_SUB_STATE_PAUSE: + switch(new_sub) { + case JTAG_SUB_STATE_SELECT: + set_tms_pulse(jtag, 1); + // now in EXIT2 + set_tms_pulse(jtag, 1); + // now in UPDATE + set_tms_pulse(jtag, 1); + // now in SELECT-DR + if (JTAG_STATE_IN_IR(new_state)) { + // on more 1 to go to select IR + set_tms_pulse(jtag, 1); + // now in SELECT-IR + } + break; + case JTAG_SUB_STATE_SHIFT: + set_tms_pulse(jtag, 1); + // now in EXIT2 + set_tms_pulse(jtag, 0); + // now in SHIFT + break; + case JTAG_SUB_STATE_PAUSE: + set_tms_pulse(jtag, 0); + // now in PAUSE + break; + case JTAG_SUB_STATE_EXIT2: + set_tms_pulse(jtag, 1); + // now in EXIT2 + break; + case JTAG_SUB_STATE_UPDATE: + set_tms_pulse(jtag, 1); + // now in EXIT2 + set_tms_pulse(jtag, 1); + // now in UPDATE + break; + case JTAG_SUB_STATE_CAPTURE: + goto_sub_state(jtag, + (new_state & JTAG_STATE_MASK) | JTAG_SUB_STATE_SELECT); + goto_sub_state(jtag, new_state); + break; + default: + // stay in current state + break; + } + break; + + case JTAG_SUB_STATE_EXIT2: + switch(new_sub) { + case JTAG_SUB_STATE_SELECT: + set_tms_pulse(jtag, 1); + // now in UPDATE + set_tms_pulse(jtag, 1); + // now in SELECT-DR + if (JTAG_STATE_IN_IR(new_state)) { + // on more 1 to go to select IR + set_tms_pulse(jtag, 1); + // now in SELECT-IR + } + break; + case JTAG_SUB_STATE_SHIFT: + set_tms_pulse(jtag, 0); + // now in SHIFT + break; + case JTAG_SUB_STATE_PAUSE: + set_tms_pulse(jtag, 0); + // now in SHIFT + set_tms_pulse(jtag, 1); + // now in EXIT 1 + set_tms_pulse(jtag, 0); + // now in PAUSE + break; + case JTAG_SUB_STATE_UPDATE: + set_tms_pulse(jtag, 1); + // now in UPDATE + break; + case JTAG_SUB_STATE_CAPTURE: + goto_sub_state(jtag, + (new_state & JTAG_STATE_MASK) | JTAG_SUB_STATE_SELECT); + goto_sub_state(jtag, new_state); + break; + default: + // stay in current state + break; + } + break; + + case JTAG_SUB_STATE_UPDATE: + switch(new_sub) { + case JTAG_SUB_STATE_SELECT: + set_tms_pulse(jtag, 1); + // now in SELECT-DR + if (JTAG_STATE_IN_IR(new_state)) { + // on more 1 to go to select IR + set_tms_pulse(jtag, 1); + // now in SELECT-IR + } + break; + case JTAG_SUB_STATE_UPDATE: + // stay in current state + break; + default: + goto_sub_state(jtag, + (new_state & JTAG_STATE_MASK) | JTAG_SUB_STATE_SELECT); + goto_sub_state(jtag, new_state); + break; + } + break; + + default: + BUG(); + break; + } +} + +static void goto_state(struct fbxjtag_data *jtag, enum jtag_state new_state) { + + enum jtag_main_state main_state, cur_main_state; + + if (jtag->state == JTAG_STATE_UNDEF) { + reset_state(jtag); + } + + main_state = new_state & JTAG_STATE_MASK; + cur_main_state = jtag->state & JTAG_STATE_MASK; + + if (main_state != cur_main_state) { + switch(cur_main_state) { + case JTAG_STATE_DR_MASK: + case JTAG_STATE_IR_MASK: + goto_state(jtag, (jtag->state & JTAG_STATE_MASK) | JTAG_SUB_STATE_UPDATE); + // now in UPDATE_DR or UPDATE_IR + + switch(main_state) { + case JTAG_STATE_TEST_MASK: + set_tms_pulse(jtag, 1); + // now in SELECT_DR + set_tms_pulse(jtag, 1); + // now in SELECT_IR + set_tms_pulse(jtag, 1); + // now in TEST_LOGIC_RESET + break; + + case JTAG_STATE_RUN_MASK: + set_tms_pulse(jtag, 0); + // now in RUN_TEST_IDLE + break; + + case JTAG_STATE_IR_MASK: + set_tms_pulse(jtag, 1); + // now in SELECT_DR + set_tms_pulse(jtag, 1); + // now in SELECT_IR + break; + + case JTAG_STATE_DR_MASK: + set_tms_pulse(jtag, 1); + // now in SELECT_DR + break; + } + break; + + case JTAG_STATE_TEST_MASK: + switch(main_state) { + case JTAG_STATE_RUN_MASK: + set_tms_pulse(jtag, 0); + // now in RUN_TEST_IDLE + break; + + case JTAG_STATE_DR_MASK: + set_tms_pulse(jtag, 0); + // now in RUN_TEST_IDLE + set_tms_pulse(jtag, 1); + // now in SELECT_DR + break; + + case JTAG_STATE_IR_MASK: + set_tms_pulse(jtag, 0); + // now in RUN_TEST_IDLE + set_tms_pulse(jtag, 1); + // now in SELECT_DR + set_tms_pulse(jtag, 1); + // now in SELECT_IR + break; + default: + BUG(); + break; + } + break; + + case JTAG_STATE_RUN_MASK: + switch(main_state) { + case JTAG_STATE_DR_MASK: + set_tms_pulse(jtag, 1); + // now in SELECT_DR + break; + + case JTAG_STATE_IR_MASK: + set_tms_pulse(jtag, 1); + // now in SELECT_DR + set_tms_pulse(jtag, 1); + // now in SELECT_IR + break; + + case JTAG_STATE_TEST_MASK: + set_tms_pulse(jtag, 1); + // now in SELECT_DR + set_tms_pulse(jtag, 1); + // now in SELECT_IR + set_tms_pulse(jtag, 1); + // now in TEST_LOGIC_RESET + break; + default: + printk(KERN_ERR PFX "JTAG TRANSITION ERROR :'( %s:%d", __FILE__, __LINE__); + BUG(); + break; + } + break; + + default: + printk(KERN_ERR PFX "JTAG TRANSITION ERROR :'( %s:%d", __FILE__, __LINE__); + BUG(); + break; + } + + if ((jtag->state & JTAG_STATE_MASK) != main_state) { + printk(KERN_ERR PFX "JTAG error : state %x != %x", + (jtag->state & JTAG_STATE_MASK), + main_state); + } + BUG_ON((jtag->state & JTAG_STATE_MASK) != main_state); + + if (new_state == JTAG_STATE_TEST_LOGIC_RESET + || new_state == JTAG_STATE_RUN_TEST_IDLE) + return; // we're done + } + + // now main_state == cur_main_state + + switch(new_state) { + case JTAG_STATE_TEST_LOGIC_RESET: + // stay in TEST_LOGIC_RESET + set_tms_pulse(jtag, 1); + return; + case JTAG_STATE_RUN_TEST_IDLE: + // stay in JTAG_STATE_RUN_TEST_IDLE + set_tms_pulse(jtag, 0); + return; + default: + break; + } + + // move inside IR or DR + goto_sub_state(jtag, new_state); + if (jtag->state != new_state) { + printk(KERN_ERR PFX "JTAG Error: state is %s instead of %s", + jtag_state_str(jtag->state), + jtag_state_str(new_state)); + } + BUG_ON(jtag->state != new_state); +} + +static ssize_t show_state(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct fbxjtag_data *jtag; + jtag = dev_get_drvdata(dev); + return sprintf(buf, "%s\n", jtag_state_str(jtag->state)); +} + +static ssize_t write_state(struct device *dev, struct device_attribute *attr, + const char *buf, size_t size) +{ + struct fbxjtag_data *jtag; + unsigned long new_state = simple_strtoul(buf, NULL, 10); + jtag = dev_get_drvdata(dev); + + switch(new_state) { + case JTAG_STATE_TEST_LOGIC_RESET: + case JTAG_STATE_RUN_TEST_IDLE: + case JTAG_STATE_SELECT_DR: + case JTAG_STATE_CAPTURE_DR: + case JTAG_STATE_SHIFT_DR: + case JTAG_STATE_EXIT1_DR: + case JTAG_STATE_PAUSE_DR: + case JTAG_STATE_EXIT2_DR: + case JTAG_STATE_UPDATE_DR: + case JTAG_STATE_SELECT_IR: + case JTAG_STATE_CAPTURE_IR: + case JTAG_STATE_SHIFT_IR: + case JTAG_STATE_EXIT1_IR: + case JTAG_STATE_PAUSE_IR: + case JTAG_STATE_EXIT2_IR: + case JTAG_STATE_UPDATE_IR: + goto_state(jtag, new_state); + return size; + + default: + printk(KERN_ERR PFX "Trying to set an invalid state: %lx\n", new_state); + return -EINVAL; + } +} + + +static ssize_t show_tck(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct fbxjtag_data *jtag; + + jtag = dev_get_drvdata(dev); + return sprintf(buf, "%i\n", jtag->gpios.tck->pin_num); +} + +static ssize_t show_tms(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct fbxjtag_data *jtag; + + jtag = dev_get_drvdata(dev); + return sprintf(buf, "%i\n", jtag->gpios.tms->pin_num); +} + +static ssize_t show_tdi(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct fbxjtag_data *jtag; + + jtag = dev_get_drvdata(dev); + return sprintf(buf, "%i\n", jtag->gpios.tdi->pin_num); +} + +static ssize_t show_tdo(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct fbxjtag_data *jtag; + + jtag = dev_get_drvdata(dev); + return sprintf(buf, "%i\n", jtag->gpios.tdo->pin_num); +} + +static ssize_t write_reset(struct device *dev, struct device_attribute *attr, + const char *buf, size_t size) +{ + struct fbxjtag_data *jtag; + + jtag = dev_get_drvdata(dev); + reset_state(jtag); + + return size; +} + +static ssize_t read_data(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fbxjtag_data *jtag; + size_t len; + + jtag = dev_get_drvdata(dev); + len = jtag->dr_w - jtag->dr_r; + if (len < 0) + len += JTAG_BUF_SIZE; + + memcpy(buf, jtag->dr_buf, len); + buf[len] = '\0'; + return len + 1; +} + +static ssize_t write_data(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct fbxjtag_data *jtag; + size_t real_size = 0; + int i; + + if (!size) + return size; + + for (i = 0; i < size; ++i) + if ((buf[i] == '0') || (buf[i] == '1')) + real_size++; + + if (!real_size) + return size; + + jtag = dev_get_drvdata(dev); + + // reset read buffer + jtag->dr_r = 0; + jtag->dr_w = 0; + goto_state(jtag, JTAG_STATE_SHIFT_DR); + for (i = 0; real_size > 0; ++i) { + if ((buf[i] == '0') || (buf[i] == '1')) { + if (real_size-- > 1) + /* stay in shift */ + set_tms_tdi_pulse(jtag, 0, buf[i] - '0'); + else + /* exit */ + set_tms_tdi_pulse(jtag, 1, buf[i] - '0'); + } + } + BUG_ON(jtag->state != JTAG_STATE_EXIT1_DR); + goto_state(jtag, JTAG_STATE_UPDATE_DR); + + return size; +} + +static ssize_t read_instruction(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fbxjtag_data *jtag; + size_t len; + + jtag = dev_get_drvdata(dev); + len = jtag->ir_w - jtag->ir_r; + if (len < 0) + len += JTAG_BUF_SIZE; + + memcpy(buf, jtag->ir_buf, len); + buf[len] = '\0'; + return len + 1; +} + +static ssize_t write_instruction(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct fbxjtag_data *jtag; + size_t real_size = 0; + int i; + + if (!size) + return size; + + for (i = 0; i < size; ++i) + if ((buf[i] == '0') || (buf[i] == '1')) + real_size++; + + if (!real_size) + return size; + + jtag = dev_get_drvdata(dev); + + // reset read buffer + jtag->ir_r = 0; + jtag->ir_w = 0; + goto_state(jtag, JTAG_STATE_SHIFT_IR); + for (i = 0; real_size > 0; ++i) { + if ((buf[i] == '0') || (buf[i] == '1')) { + if (real_size-- > 1) + /* stay in shift */ + set_tms_tdi_pulse(jtag, 0, buf[i] - '0'); + else + /* exit */ + set_tms_tdi_pulse(jtag, 1, buf[i] - '0'); + } + } + BUG_ON(jtag->state != JTAG_STATE_EXIT1_IR); + goto_state(jtag, JTAG_STATE_UPDATE_IR); + + return size; +} + +static ssize_t show_clock_delay(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct fbxjtag_data *jtag; + + jtag = dev_get_drvdata(dev); + + return sprintf(buf, "%u\n", jtag->clock_delay); +} + +static ssize_t write_clock_delay(struct device *dev, struct device_attribute *attr, + const char *buf, size_t size) +{ + struct fbxjtag_data *jtag; + + jtag = dev_get_drvdata(dev); + + jtag->clock_delay = simple_strtoul(buf, NULL, 10); + + return size; +} + +static ssize_t show_wait_tms(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct fbxjtag_data *jtag; + + jtag = dev_get_drvdata(dev); + + return sprintf(buf, "%u\n", jtag->wait_tms); +} + +static ssize_t write_wait_tms(struct device *dev, struct device_attribute *attr, + const char *buf, size_t size) +{ + struct fbxjtag_data *jtag; + + if (!size) + return size; + + jtag = dev_get_drvdata(dev); + + switch (*buf) { + case '0': + jtag->wait_tms = 0; + break ; + case '1': + jtag->wait_tms = 1; + break ; + default: + return -EINVAL; + } + + return size; +} + +static ssize_t write_wait_time(struct device *dev, struct device_attribute *attr, + const char *buf, size_t size) +{ + struct fbxjtag_data *jtag; + int i; + unsigned long val; + + val = simple_strtoul(buf, NULL, 10); + + if (!val) + return -EINVAL; + + jtag = dev_get_drvdata(dev); + + for (i = 0; i < val; ++i) { + set_tms_pulse(jtag, jtag->wait_tms); + } + + return size; +} + +static ssize_t show_data_read_size(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fbxjtag_data *jtag; + + jtag = dev_get_drvdata(dev); + + return sprintf(buf, "%u\n", jtag->data_read_size); +} + +static ssize_t write_data_read_size(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct fbxjtag_data *jtag; + unsigned long val; + + val = simple_strtoul(buf, NULL, 10); + + if (!val) + return -EINVAL; + + jtag = dev_get_drvdata(dev); + jtag->data_read_size = val; + + return size; +} + +static ssize_t show_instruction_read_size(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct fbxjtag_data *jtag; + + jtag = dev_get_drvdata(dev); + + return sprintf(buf, "%u\n", jtag->instruction_read_size); +} + +static ssize_t write_instruction_read_size(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct fbxjtag_data *jtag; + unsigned long val; + + val = simple_strtoul(buf, NULL, 10); + + if (!val) + return -EINVAL; + + jtag = dev_get_drvdata(dev); + jtag->instruction_read_size = val; + + return size; +} + +static struct device_attribute jtag_attributes[] = { + __ATTR(tck, 0400, show_tck, NULL), + __ATTR(tms, 0400, show_tms, NULL), + __ATTR(tdi, 0400, show_tdi, NULL), + __ATTR(tdo, 0400, show_tdo, NULL), + __ATTR(clock_delay, 0600, show_clock_delay, write_clock_delay), + __ATTR(wait_tms, 0600, show_wait_tms, write_wait_tms), + __ATTR(wait_time, 0200, NULL, write_wait_time), + __ATTR(data_read_size, 0600, show_data_read_size, write_data_read_size), + __ATTR(instruction_read_size, 0600, show_instruction_read_size, + write_instruction_read_size), + __ATTR(data, 0600, read_data, write_data), + __ATTR(instruction, 0600, read_instruction, write_instruction), + __ATTR(reset, 0200, NULL, write_reset), + __ATTR(state, 0600, show_state, write_state), +}; + +static int fbxjtag_register_jtag(struct platform_device *ppdev, + struct fbxjtag_data *jtag) +{ + struct device *dev; + int i, ret; + + printk(KERN_INFO PFX "registering jtag %s\n", jtag->name); + + if (!jtag->gpios.tck || !jtag->gpios.tms || + !jtag->gpios.tdi || !jtag->gpios.tdo) { + printk(KERN_ERR PFX "a gpio is not set\n"); + return -ENODEV; + } + + dev = device_create(fbxjtag_class, &ppdev->dev, 0, jtag, + "%s", jtag->name); + + if (IS_ERR(dev)) + return PTR_ERR(dev); + + for (i = 0; i < ARRAY_SIZE(jtag_attributes); ++i) { + ret = device_create_file(dev, &jtag_attributes[i]); + if (ret) + goto err_out; + } + + jtag->dev = dev; + jtag->nb_reset = 0; + jtag->state = JTAG_STATE_UNDEF; + jtag->dr_r = 0; + jtag->dr_w = 0; + jtag->ir_r = 0; + jtag->ir_w = 0; + return 0; + +err_out: + for (; i >= 0; --i) + device_remove_file(dev, &jtag_attributes[i]); + device_unregister(dev); + return ret; +} + +static void fbxjtag_unregister_jtag(struct fbxjtag_data *jtag) +{ + struct device *dev; + int i; + + printk(KERN_INFO PFX "unregistering jtag %s\n", jtag->name); + dev = jtag->dev; + jtag->dev = NULL; + + for (i = 0; i < ARRAY_SIZE(jtag_attributes); ++i) + device_remove_file(dev, &jtag_attributes[i]); + device_unregister(dev); +} + +static int fbxjtag_from_of(struct fbxjtag_data *jtag, + struct platform_device *pdev) +{ + int error; + + error = of_property_read_string(pdev->dev.of_node, "name", + &jtag->name); + if (error) + return error; + + error = of_property_read_u32(pdev->dev.of_node, "clock-delay", + &jtag->clock_delay); + if (error) + return error; + + error = of_property_read_u32(pdev->dev.of_node, "wait-tms", + &jtag->wait_tms); + if (error) + return error; + + error = of_property_read_u32(pdev->dev.of_node, "data-read-size", + &jtag->data_read_size); + if (error) + return error; + + error = of_property_read_u32(pdev->dev.of_node, "inst-read-size", + &jtag->instruction_read_size); + if (error) + return error; + + jtag->gpios.tck = fbxgpio_of_get(pdev->dev.of_node, "fbxgpio-tck", 0); + if (IS_ERR(jtag->gpios.tck)) + return PTR_ERR(jtag->gpios.tck); + + jtag->gpios.tdi = fbxgpio_of_get(pdev->dev.of_node, "fbxgpio-tdi", 0); + if (IS_ERR(jtag->gpios.tdi)) + return PTR_ERR(jtag->gpios.tdi); + + jtag->gpios.tdo = fbxgpio_of_get(pdev->dev.of_node, "fbxgpio-tdo", 0); + if (IS_ERR(jtag->gpios.tdo)) + return PTR_ERR(jtag->gpios.tdo); + + jtag->gpios.tms = fbxgpio_of_get(pdev->dev.of_node, "fbxgpio-tms", 0); + if (IS_ERR(jtag->gpios.tms)) + return PTR_ERR(jtag->gpios.tms); + + return 0; +} + +static int fbxjtag_platform_probe(struct platform_device *pdev) +{ + struct fbxjtag_data *jtag; + + jtag = pdev->dev.platform_data; + if (!jtag) { + int error; + jtag = devm_kzalloc(&pdev->dev, sizeof (*jtag), GFP_KERNEL); + if (!jtag) + return -ENOMEM; + error = fbxjtag_from_of(jtag, pdev); + if (error) + return error; + + dev_set_drvdata(&pdev->dev, jtag); + } + if (jtag && jtag->name) + return fbxjtag_register_jtag(pdev, jtag); + + return -EINVAL; +} + +static int fbxjtag_platform_remove(struct platform_device *pdev) +{ + struct fbxjtag_data *jtag; + + jtag = pdev->dev.platform_data; + if (!jtag) + jtag = dev_get_drvdata(&pdev->dev); + if (jtag->name) + fbxjtag_unregister_jtag(jtag); + + return 0; +} + +static const struct of_device_id fbxjtag_of_match_table[] = { + { .compatible = "fbx,fbxjtag" }, + { }, +}; +MODULE_DEVICE_TABLE(of, fbxjtag_of_match_table); + +static struct platform_driver fbxjtag_platform_driver = +{ + .probe = fbxjtag_platform_probe, + .remove = fbxjtag_platform_remove, + .driver = { + .name = "fbxjtag", + .of_match_table = fbxjtag_of_match_table, + }, +}; + +static int __init fbxjtag_init(void) +{ + int ret; + + fbxjtag_class = class_create(THIS_MODULE, "fbxjtag"); + if (IS_ERR(fbxjtag_class)) + return PTR_ERR(fbxjtag_class); + + ret = platform_driver_register(&fbxjtag_platform_driver); + if (ret) { + printk(KERN_ERR PFX "unable to register fbxjtag driver.\n"); + class_destroy(fbxjtag_class); + } + + return ret; +} + +static void __exit fbxjtag_exit(void) +{ + printk(KERN_DEBUG PFX "exit fbxjtag\n"); + platform_driver_unregister(&fbxjtag_platform_driver); + class_destroy(fbxjtag_class); +} + +module_init(fbxjtag_init); +module_exit(fbxjtag_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Arnaud de Turckheim +#include +#include +#include +#include +#include +#include +#include + +#include + +#define PFX "fbxprocfs: " + + +static struct list_head clients; +static struct mutex clients_mutex; + +static struct proc_dir_entry *root; + +/* + * register a fbxprocfs client with given dirname, caller should + * consider returned struct opaque + */ +struct fbxprocfs_client *fbxprocfs_add_client(const char *dirname, + struct module *owner) +{ + struct fbxprocfs_client *ret, *p; + + ret = NULL; + mutex_lock(&clients_mutex); + + /* check for duplicate */ + list_for_each_entry(p, &clients, list) { + if (!strcmp(dirname, p->dirname)) + goto out; + } + + if (!(ret = kmalloc(sizeof (*ret), GFP_KERNEL))) { + printk(KERN_ERR PFX "kmalloc failed\n"); + goto out; + } + + /* try to create client directory */ + if (!(ret->dir = proc_mkdir(dirname, root))) { + printk(KERN_ERR PFX "can't create %s dir\n", dirname); + kfree(ret); + ret = NULL; + goto out; + } + + atomic_set(&ret->refcount, 1); + ret->dirname = dirname; + list_add(&ret->list, &clients); + +out: + mutex_unlock(&clients_mutex); + return ret; +} + +/* + * unregister a fbxprocfs client, make sure usage count is zero + */ +int fbxprocfs_remove_client(struct fbxprocfs_client *client) +{ + int ret; + + mutex_lock(&clients_mutex); + + ret = 0; + if (atomic_read(&client->refcount) > 1) { + ret = -EBUSY; + goto out; + } + + remove_proc_entry(client->dirname, root); + list_del(&client->list); + kfree(client); + +out: + mutex_unlock(&clients_mutex); + return ret; +} + +/* + * remove given entries from client directory + */ +static int +__remove_entries(struct fbxprocfs_client *client, + const struct fbxprocfs_desc *ro_desc, + const struct fbxprocfs_desc *rw_desc) +{ + int i; + + for (i = 0; ro_desc && ro_desc[i].name; i++) { + remove_proc_entry(ro_desc[i].name, client->dir); + atomic_dec(&client->refcount); + } + + for (i = 0; rw_desc && rw_desc[i].name; i++) { + remove_proc_entry(rw_desc[i].name, client->dir); + atomic_dec(&client->refcount); + } + + return 0; +} + +/* + * replacement for NULL rfunc. + */ +static int bad_rfunc(struct seq_file *m, void *ptr) +{ + return -EACCES; +} + +/* + * fbxprocfs write path is now handled by seq_file code. this + * simplifies client code greatly. + */ +static int fbxprocfs_open(struct inode *inode, struct file *file) +{ + const struct fbxprocfs_desc *desc = PDE_DATA(inode); + + return single_open(file, desc->rfunc ? desc->rfunc : bad_rfunc, + (void*)desc->id); +} + +/* + * no particular help from kernel in the write path, fetch user buffer + * in a kernel buffer and call write func. + */ +static ssize_t fbxprocfs_write(struct file *file, const char __user *ubuf, + size_t len, loff_t *off) +{ + /* + * get fbxprocfs desc via the proc_dir_entry in file inode + */ + struct fbxprocfs_desc *d = PDE_DATA(file_inode(file)); + char *kbuf; + int ret; + + /* + * must have a wfunc callback. + */ + if (!d->wfunc) + return -EACCES; + + /* + * allow up to SZ_4K bytes to be written. + */ + if (len > SZ_4K) + return -EOVERFLOW; + + /* + * alloc and fetch kernel buffer containing user data. + */ + kbuf = kmalloc(SZ_4K, GFP_KERNEL); + if (!kbuf) + return -ENOMEM; + + ret = -EFAULT; + if (copy_from_user(kbuf, ubuf, len)) + goto kfree; + + ret = d->wfunc(file, kbuf, len, (void*)d->id); + +kfree: + kfree(kbuf); + return ret; +} + +/* + * fbxprocfs file operations, read stuff is handled by seq_file code. + */ +static const struct file_operations fbxprocfs_fops = { + .open = fbxprocfs_open, + .llseek = seq_lseek, + .read = seq_read, + .release = single_release, + .write = fbxprocfs_write, +}; + +/* + * replaces create_proc_read_entry removed in latest kernels. + */ +static struct proc_dir_entry *__create_proc_read_entry( + const struct fbxprocfs_desc *desc, + struct proc_dir_entry *base) +{ + return proc_create_data(desc->name, 0, base, &fbxprocfs_fops, + (void*)desc); +} + +/* + * replaces create_proc_entry removed in latest kernels. + */ +static struct proc_dir_entry *__create_proc_entry( + const struct fbxprocfs_desc *desc, + struct proc_dir_entry *base) +{ + return proc_create_data(desc->name, S_IFREG | S_IWUSR | S_IRUGO, + base, &fbxprocfs_fops, (void*)desc); +} + +/* + * create given entries in client directory + */ +static int +__create_entries(struct fbxprocfs_client *client, + const struct fbxprocfs_desc *ro_desc, + const struct fbxprocfs_desc *rw_desc) +{ + struct proc_dir_entry *proc; + int i; + + for (i = 0; ro_desc && ro_desc[i].name; i++) { + if (!(proc = __create_proc_read_entry(&ro_desc[i], + client->dir))) { + printk(KERN_ERR PFX "can't create %s/%s entry\n", + client->dirname, ro_desc[i].name); + goto err; + } + atomic_inc(&client->refcount); + } + + for (i = 0; rw_desc && rw_desc[i].name; i++) { + if (!(proc = __create_proc_entry(&rw_desc[i], client->dir))) { + printk(KERN_ERR PFX "can't create %s/%s entry\n", + client->dirname, ro_desc[i].name); + goto err; + } + atomic_inc(&client->refcount); + } + + return 0; + +err: + __remove_entries(client, ro_desc, rw_desc); + return -1; +} + +int +fbxprocfs_create_entries(struct fbxprocfs_client *client, + const struct fbxprocfs_desc *ro_desc, + const struct fbxprocfs_desc *rw_desc) +{ + int ret; + + ret = __create_entries(client, ro_desc, rw_desc); + return ret; +} + +int +fbxprocfs_remove_entries(struct fbxprocfs_client *client, + const struct fbxprocfs_desc *ro_desc, + const struct fbxprocfs_desc *rw_desc) +{ + int ret; + + ret = __remove_entries(client, ro_desc, rw_desc); + return ret; +} + + +static int __init +fbxprocfs_init(void) +{ + INIT_LIST_HEAD(&clients); + mutex_init(&clients_mutex); + + /* create freebox directory */ + if (!(root = proc_mkdir("freebox", NULL))) { + printk(KERN_ERR PFX "can't create freebox/ dir\n"); + return -EIO; + } + return 0; +} + +static void __exit +fbxprocfs_exit(void) +{ + remove_proc_entry("freebox", NULL); +} + +module_init(fbxprocfs_init); +module_exit(fbxprocfs_exit); + +EXPORT_SYMBOL(fbxprocfs_create_entries); +EXPORT_SYMBOL(fbxprocfs_remove_entries); +EXPORT_SYMBOL(fbxprocfs_add_client); +EXPORT_SYMBOL(fbxprocfs_remove_client); + +MODULE_LICENSE("GPL"); +MODULE_VERSION("1.0"); +MODULE_AUTHOR("Maxime Bizon "); + diff -Nruw linux-4.14.127-fbx/drivers/fbxwatchdog./Kconfig linux-4.14.127-fbx/drivers/fbxwatchdog/Kconfig --- linux-4.14.127-fbx/drivers/fbxwatchdog./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/drivers/fbxwatchdog/Kconfig 2019-02-15 14:29:37.734639379 +0100 @@ -0,0 +1,24 @@ +menuconfig FREEBOX_WATCHDOG + tristate "Freebox Watchdog" + default n + +if FREEBOX_WATCHDOG + +config FREEBOX_WATCHDOG_CHAR + bool "Freebox Watchdog char device interface." + default n + +config FREEBOX_WATCHDOG_ORION + tristate "Marvell Orion support" + depends on PLAT_ORION + +config FREEBOX_WATCHDOG_BCM63XX + tristate "Broadcom 63xx Freebox Watchdog support" + depends on BCM63XX + default n + +config FREEBOX_WATCHDOG_BCM63XX_OF + tristate "Broadcom 63xx Freebox Watchdog support (generic)" + depends on OF && !FREEBOX_WATCHDOG_BCM63XX + +endif diff -Nruw linux-4.14.127-fbx/drivers/fbxwatchdog./Makefile linux-4.14.127-fbx/drivers/fbxwatchdog/Makefile --- linux-4.14.127-fbx/drivers/fbxwatchdog./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/drivers/fbxwatchdog/Makefile 2019-02-15 14:29:37.734639379 +0100 @@ -0,0 +1,10 @@ +obj-$(CONFIG_FREEBOX_WATCHDOG) += fbxwatchdog.o + +fbxwatchdog-objs = fbxwatchdog_core.o +ifeq ($(CONFIG_FREEBOX_WATCHDOG_CHAR),y) +fbxwatchdog-objs += fbxwatchdog_char.o +endif + +obj-$(CONFIG_FREEBOX_WATCHDOG_ORION) += fbxwatchdog_orion.o +obj-$(CONFIG_FREEBOX_WATCHDOG_BCM63XX) += fbxwatchdog_bcm63xx.o +obj-$(CONFIG_FREEBOX_WATCHDOG_BCM63XX_OF) += fbxwatchdog_bcm63xx_of.o --- /dev/null 2019-09-30 09:50:43.919599165 +0200 +++ linux-4.14.127-fbx/drivers/hwmon/ap806-hwmon.c 2019-02-15 14:29:38.686643152 +0100 @@ -0,0 +1,284 @@ +/* + * ap806.c for ap806-hwmon + * Created by on Tue Oct 3 15:43:07 2017 + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define AP806_SENSOR_CTRL 0x0 +# define AP806_SENSOR_CTRL_START BIT(0) +# define AP806_SENSOR_CTRL_RESET BIT(1) +# define AP806_SENSOR_CTRL_ENABLE BIT(2) + +#define CP110_TSEN_CONTROL 0x4 +# define CP110_TSEN_CONTROL_HW_RESET BIT(8) + +#define AP806_SENSOR_STATUS 0x8 +# define AP806_SENSOR_STATUS_READOUT_MASK (0x3ff) + +#define CP110_SENSOR_VALID_BIT 10 +#define AP806_SENSOR_VALID_BIT 16 + +#define SENSOR_READ_SMC ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_OEM, 0) + +#define SENSOR_WRITE_SMC ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_OEM, 1) + +struct ap806_hwmon_priv { + void __iomem *regs; + struct device *hwmon_dev; + const struct sensor_data *data; + + bool requires_smc; + unsigned long io_phys_base; + struct device *dev; + +}; + +struct sensor_data { + u32 readout_valid_bit; + bool two_complement; + unsigned long coef_b; + unsigned long coef_m; + unsigned long coef_div; + int (*init_sensor)(struct ap806_hwmon_priv *priv); +}; + +/* + * SMC/IO accessors for sensors. on A8K, sensors registers lie in the + * DFX space which may have to be configured to reject non secure + * accesses (fuses block are on the DFX space). + * + * Freebox ATF implements IO accessors for sensor registers via SMC + * call to the secure monitor. + * + * Ideally we should put these details in a regmap but this will do + * for now. + */ +static int sensor_read(u32 *v, struct ap806_hwmon_priv *priv, u32 reg_off) +{ + if (!priv->requires_smc) { + *v = readl(priv->regs + reg_off); + return 0; + } else { + struct arm_smccc_res smc_res; + + arm_smccc_smc(SENSOR_READ_SMC, priv->io_phys_base + reg_off, + 0, 0, 0, 0, 0, 0, &smc_res); + if (smc_res.a0) { + dev_err(priv->dev, "read SMC failed.\n"); + return -ENXIO; + } else { + *v = smc_res.a1; + return 0; + } + } +} + +static int sensor_write(u32 value, struct ap806_hwmon_priv *priv, u32 reg_off) +{ + if (!priv->requires_smc) { + writel(value, priv->regs + reg_off); + return 0; + } else { + struct arm_smccc_res smc_res; + + arm_smccc_smc(SENSOR_WRITE_SMC, value, + priv->io_phys_base + reg_off, + 0, 0, 0, 0, 0, &smc_res); + + if (smc_res.a0) { + dev_err(priv->dev, "write SMC failed.\n"); + return -ENXIO; + } + return 0; + } +} + +static int ap806_init_sensor(struct ap806_hwmon_priv *priv) +{ + u32 reg; + int error; + + /* + * dereset and start sensor. + */ + error = sensor_read(®, priv, AP806_SENSOR_CTRL); + if (error) + return error; + + reg &= ~AP806_SENSOR_CTRL_RESET; + reg |= AP806_SENSOR_CTRL_ENABLE; + reg |= AP806_SENSOR_CTRL_START; + + return sensor_write(reg, priv, AP806_SENSOR_CTRL); +} + +static int cp110_init_sensor(struct ap806_hwmon_priv *priv) +{ + u32 reg; + int error; + /* + * dereset sensor. + */ + error = sensor_read(®, priv, CP110_TSEN_CONTROL); + if (error) + return error; + + reg |= CP110_TSEN_CONTROL_HW_RESET; + + return sensor_write(reg, priv, CP110_TSEN_CONTROL); +} + +static const struct sensor_data ap806_sensor_data = { + .readout_valid_bit = AP806_SENSOR_VALID_BIT, + .coef_b = 153400, + .coef_m = 425, + .coef_div = 1, + .two_complement = true, + .init_sensor = ap806_init_sensor, +}; + +static const struct sensor_data cp110_sensor_data = { + .readout_valid_bit = CP110_SENSOR_VALID_BIT, + .coef_b = -2791000UL, + .coef_m = 4761UL, + .coef_div = 10, + .two_complement = false, + .init_sensor = cp110_init_sensor, +}; + +static ssize_t ap806_show_temp(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct ap806_hwmon_priv *priv = dev_get_drvdata(dev); + const struct sensor_data *data = priv->data; + u32 reg; + int value; + int error; + + error = sensor_read(®, priv, AP806_SENSOR_STATUS); + if (error) + return -ENXIO; + + if ((reg & (1 << data->readout_valid_bit)) == 0) + return -EIO; + + reg &= AP806_SENSOR_STATUS_READOUT_MASK; + + if (data->two_complement && reg >= 512) + reg = reg - 1024; + + value = (data->coef_m * (long)reg + data->coef_b) / + data->coef_div; + return sprintf(buf, "%d\n", value); +} + +static SENSOR_DEVICE_ATTR_2(temp0_input, S_IRUGO, ap806_show_temp, NULL, 0, 0); + +static struct attribute *temp_attrs[] = { + &sensor_dev_attr_temp0_input.dev_attr.attr, + NULL +}; + +static const struct attribute_group ap806_temperature_attr_group = { + .attrs = temp_attrs, +}; + +static const struct of_device_id ap806_hwmon_of_match[] = { + { .compatible = "marvell,ap806-hwmon", .data = &ap806_sensor_data }, + { .compatible = "marvell,cp110-hwmon", .data = &cp110_sensor_data }, + { }, +}; +MODULE_DEVICE_TABLE(of, ap806_hwmon_of_match); + +static int ap806_hwmon_probe(struct platform_device *pdev) +{ + struct ap806_hwmon_priv *priv; + struct resource *reg_resource; + int error; + const struct of_device_id *match; + + match = of_match_device(ap806_hwmon_of_match, &pdev->dev); + if (!match) + return -ENODEV; + + priv = devm_kzalloc(&pdev->dev, sizeof (*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + dev_set_drvdata(&pdev->dev, priv); + priv->dev = &pdev->dev; + + reg_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!reg_resource) + return -EINVAL; + + if (of_property_read_bool(pdev->dev.of_node, "fbx,requires-smc")) { + dev_info(&pdev->dev, "using SMC to access registers.\n"); + priv->requires_smc = true; + priv->io_phys_base = reg_resource->start; + } else { + priv->regs = devm_ioremap_resource(&pdev->dev, reg_resource); + if (!priv->regs) + return -ENOMEM; + } + + priv->data = match->data; + + error = priv->data->init_sensor(priv); + if (error) + return error; + + error = sysfs_create_group(&pdev->dev.kobj, &ap806_temperature_attr_group); + if (error) + return error; + + priv->hwmon_dev = hwmon_device_register(&pdev->dev); + if (IS_ERR(priv->hwmon_dev)) { + error = PTR_ERR(priv->hwmon_dev); + goto sysfs_remove_group; + } + + return 0; + +sysfs_remove_group: + sysfs_remove_group(&pdev->dev.kobj, &ap806_temperature_attr_group); + return error; +} + +static int ap806_hwmon_remove(struct platform_device *pdev) +{ + struct ap806_hwmon_priv *priv = dev_get_drvdata(&pdev->dev); + + hwmon_device_unregister(priv->hwmon_dev); + sysfs_remove_group(&pdev->dev.kobj, &ap806_temperature_attr_group); + return 0; +} + +struct platform_driver ap806_hwmon_driver = { + .probe = ap806_hwmon_probe, + .remove = ap806_hwmon_remove, + .driver = { + .name = "ap806-hwmon", + .owner = THIS_MODULE, + .of_match_table = ap806_hwmon_of_match, + }, +}; + +module_platform_driver(ap806_hwmon_driver); + +MODULE_AUTHOR("Nicolas Schichan "); +MODULE_LICENSE("GPL"); --- /dev/null 2019-09-30 09:50:43.919599165 +0200 +++ linux-4.14.127-fbx/drivers/input/misc/smsc_cap1066.c 2019-02-15 14:29:38.966644262 +0100 @@ -0,0 +1,1117 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PFX "cap1066: " + +/* + * list of registers + */ +#define SMSC_REG_MAIN_CTRL 0x00 +#define SMSC_REG_BTN_STATUS1 0x03 +#define SMSC_REG_DATA_SENSITIVITY 0x1f +#define SMSC_REG_CFG 0x20 +#define SMSC_REG_SENS_CFG 0x22 +#define SMSC_REG_MTOUCH_CFG_REG 0x2a +#define SMSC_REG_CFG2 0x44 +#define SMSC_REG_LED_OUT_TYPE 0x71 +#define SMSC_REG_LED_LINK 0x72 +#define SMSC_REG_LED_OUTPUT_CTL 0x74 +#define SMSC_REG_LED_BEHAVIOUR1 0x81 +#define SMSC_REG_LED_BEHAVIOUR2 0x82 +#define SMSC_REG_LED_DIRECT_DCYCLE 0x93 +#define SMSC_REG_LED_DIRECT_RAMP_RATE 0x94 +#define SMSC_REG_LED_OFF_DELAY 0x95 +#define SMSC_REG_DID 0xfd +#define SMSC_REG_VID 0xfe + +/* + * used in cap1066_init_hw and during priv initialization. + */ +#define DEFAULT_DUTY_CYCLE_MIN 0x4 +#define DEFAULT_DUTY_CYCLE_MAX 0xf +#define DEFAULT_RAMP_TIME_FALL 0x1 +#define DEFAULT_RAMP_TIME_RISE 0x2 + +/* + * vendor id / device id + */ +#define SMSC_CAP1066_VID 0x5d +#define SMSC_CAP1066_DID 0x41 +#define SMSC_CAP1166_DID 0x51 + +static const unsigned short normal_i2c[] = { 0x28, I2C_CLIENT_END }; + +static const struct i2c_device_id cap1066_id[] = { + { "cap1066", 0 }, + { } +}; + +/* + * private context + */ +static u32 default_map[CAP1066_MAX_BTNS] = { + BTN_0, + BTN_1, + BTN_2, + BTN_3, + BTN_4, + BTN_5, +}; + +struct led_btn_name +{ + int code; + const char *name; +}; + +/* + * whenever possible symlinks will be created from led_btn_X to + * led_key_y, depending on user provided keymap. add entries here as + * you see fit. + */ +static const struct led_btn_name led_btn_names[] = { + { KEY_UP, "led_key_up", }, + { KEY_DOWN, "led_key_down", }, + { KEY_LEFT, "led_key_left", }, + { KEY_RIGHT, "led_key_right", }, + { KEY_ENTER, "led_key_enter", }, +}; + +enum { + E_SMSC_CAP1066_LED_MODE_AUTO, + E_SMSC_CAP1066_LED_MODE_ON, + E_SMSC_CAP1066_LED_MODE_OFF, +}; + +struct cap1066_led_dev +{ + struct cap1066_priv *parent_priv; + struct device dev; + int led_mode; + int led_index; + const char *btn_link; +}; + +struct cap1066_priv { + struct input_polled_dev *poll_dev; + struct i2c_client *client; + u32 keymap[CAP1066_MAX_BTNS]; + struct cap1066_led_dev *led_devices[CAP1066_MAX_BTNS]; + + u8 duty_cycle_min; + u8 duty_cycle_max; + u8 raw_ramp_time_fall; + u8 raw_ramp_time_rise; + + struct gpio_desc *irq_gpio; +}; + +static const char *get_keycode_btn_name(int key_code) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(led_btn_names); ++i) { + if (key_code == led_btn_names[i].code) + return led_btn_names[i].name; + } + return NULL; +} + +/* + * single register read + */ +static int cap1066_read_reg(struct i2c_client *client, u8 reg, u8 *val) +{ + int ret; + + ret = i2c_smbus_read_byte_data(client, reg); + if (ret < 0) { + printk(KERN_ERR PFX "read failed: %d\n", ret); + return ret; + } + + *val = (u8)ret; + return 0; +} + +/* + * single register write + */ +static int cap1066_write_reg(struct i2c_client *client, u8 reg, u8 val) +{ + int ret; + + ret = i2c_smbus_write_byte_data(client, reg, val); + if (ret < 0) { + printk(KERN_ERR PFX "write failed: %d\n", ret); + return ret; + } + return 0; +} + +/* + * called when an smbus device is detected, make sure it's a cap1066 + */ +static int cap1066_detect(struct i2c_client *client, + struct i2c_board_info *info) + +{ + int ret; + u8 vid, did; + const char *name = NULL; + + ret = cap1066_read_reg(client, SMSC_REG_VID, &vid); + if (ret) + return ret; + + ret = cap1066_read_reg(client, SMSC_REG_DID, &did); + if (ret) + return ret; + + if (vid != SMSC_CAP1066_VID) + goto no_dev; + + switch (did) { + case SMSC_CAP1066_DID: + name = "cap1066"; + break; + case SMSC_CAP1166_DID: + name = "cap1166"; + break; + default: + goto no_dev; + } + + printk(KERN_INFO PFX "detected SMSC %s chip\n", name); + if (info) + strlcpy(info->type, name, I2C_NAME_SIZE); + return 0; + +no_dev: + printk(KERN_ERR PFX "bad vid/did: 0x%04x/0x%04x\n", vid, did); + return -ENODEV; +} + +/* + * reset registers value + */ +static int cap1066_init_hw(struct i2c_client *client) +{ + unsigned int i; + u8 did; + int ret; + + static const u8 init_regs[] = { + /* power on */ + SMSC_REG_MAIN_CTRL, 0x0, + + /* default sensitivity */ + SMSC_REG_DATA_SENSITIVITY, 0x2f, + + /* max duration */ + SMSC_REG_SENS_CFG, 0xf4, + + /* default configuration */ + SMSC_REG_CFG, 0x38, + + /* open drain output on all gpios */ + SMSC_REG_LED_OUT_TYPE, 0x00, + + /* link leds with sensors */ + SMSC_REG_LED_LINK, 0x3f, + + /* setup direct mode */ + SMSC_REG_LED_BEHAVIOUR1, 0x00, + SMSC_REG_LED_BEHAVIOUR2, 0x00, + + /* set led duty cycle min/max to 10% => 100% */ + SMSC_REG_LED_DIRECT_DCYCLE, + (DEFAULT_DUTY_CYCLE_MAX << 4) | + (DEFAULT_DUTY_CYCLE_MIN), + + /* set ramp rate time to 500ms/250ms */ + SMSC_REG_LED_DIRECT_RAMP_RATE, + (DEFAULT_RAMP_TIME_RISE << 3) | + (DEFAULT_RAMP_TIME_FALL), + }; + + static const u8 init_cap11_regs[] = { + /* default configuration2 */ + SMSC_REG_CFG2, 0x44, + }; + + for (i = 0; i < ARRAY_SIZE(init_regs); i += 2) { + int ret; + + ret = cap1066_write_reg(client, + init_regs[i], init_regs[i + 1]); + if (ret) + return ret; + } + + ret = cap1066_read_reg(client, SMSC_REG_DID, &did); + if (ret) + return ret; + + if (did != SMSC_CAP1166_DID) + return 0; + + for (i = 0; i < ARRAY_SIZE(init_cap11_regs); i += 2) { + int ret; + + ret = cap1066_write_reg(client, + init_cap11_regs[i], + init_cap11_regs[i + 1]); + if (ret) + return ret; + } + + return 0; +} + +/* + * input core poll callback + */ +static void cap1066_input_poll(struct input_polled_dev *dev) +{ + struct cap1066_priv *priv = dev->private; + struct input_dev *input = dev->input; + unsigned int i; + int ret; + u8 stat; + + if (priv->irq_gpio && gpiod_get_value(priv->irq_gpio)) + return; + + /* clear interrupt flag */ + cap1066_write_reg(priv->client, SMSC_REG_MAIN_CTRL, 0); + + ret = cap1066_read_reg(priv->client, SMSC_REG_BTN_STATUS1, &stat); + if (ret) { + printk(KERN_ERR PFX "unable to read status\n"); + return; + } + + for (i = 0; i < CAP1066_MAX_BTNS; i++) + input_report_key(input, priv->keymap[i], + (stat & (1 << i)) ? 1 : 0); + input_sync(input); +} + +#define to_cap1066_led_dev(Dev) container_of(Dev, struct cap1066_led_dev, dev) + +/* + * called when all sysfs references to the cap1066_led_dev are gone. + */ +static void cap1066_led_dev_release(struct device *dev) +{ + struct cap1066_led_dev *led_dev; + + led_dev = to_cap1066_led_dev(dev); + kfree(led_dev); +} + +static int is_white(int c) +{ + return c == '\0' || c == ' ' || c == '\t' || c == '\n' || c == '\r'; +} + +/* + * store a new control value for a given cap1066_led_dev: + * - auto means that the led is linked to the capacitive keys + * - on means that the led is always on + * - off means that the led is always off + */ +static ssize_t store_control(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct cap1066_led_dev *led_dev; + int new_mode; + int read_len = 0; + const char *end; + int key; + u8 reg; + struct i2c_client *client; + static const char *valid_keys[] = { + [E_SMSC_CAP1066_LED_MODE_AUTO] = "auto", + [E_SMSC_CAP1066_LED_MODE_ON] = "on", + [E_SMSC_CAP1066_LED_MODE_OFF] = "off", + }; + + + led_dev = to_cap1066_led_dev(dev); + client = led_dev->parent_priv->client; + + if (is_white(*buf)) + /* + * eat white spaces silently, upper layer will call us + * again. + */ + return 1; + + for (key = 0; key < ARRAY_SIZE(valid_keys); ++key) { + if (count < strlen(valid_keys[key])) + continue ; + if (!strncmp(buf, valid_keys[key], strlen(valid_keys[key]))) { + break; + } + } + + if (key == ARRAY_SIZE(valid_keys)) { + /* + * end of valid_keys array reached and nothing valid + * was recognized. + */ + printk(KERN_ERR PFX "invalid control value.\n"); + return -EINVAL; + } + new_mode = key; + read_len = strlen(valid_keys[key]); + + /* + * check that no garbage is present at end of input. + */ + end = buf + read_len; + if (end < buf + count && !is_white(*end)) { + /* + * garbage at end of input. + */ + printk(KERN_ERR PFX "garbage at end of value for led " + "control.\n"); + return -EINVAL; + } + + if (new_mode == led_dev->led_mode) + return read_len; + + if (new_mode == E_SMSC_CAP1066_LED_MODE_AUTO) { + cap1066_read_reg(client, SMSC_REG_LED_LINK, ®); + reg |= (1 << led_dev->led_index); + cap1066_write_reg(client, SMSC_REG_LED_LINK, reg); + } else { + cap1066_read_reg(client, SMSC_REG_LED_LINK, ®); + reg &= ~(1 << led_dev->led_index); + cap1066_write_reg(client, SMSC_REG_LED_LINK, reg); + + cap1066_read_reg(client, SMSC_REG_LED_OUTPUT_CTL, ®); + if (new_mode == E_SMSC_CAP1066_LED_MODE_ON) + reg |= (1 << led_dev->led_index); + else + reg &= ~(1 << led_dev->led_index); + cap1066_write_reg(client, SMSC_REG_LED_OUTPUT_CTL, reg); + } + led_dev->led_mode = new_mode; + + return read_len; +} + +static ssize_t show_control(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct cap1066_led_dev *led_dev; + const char *str; + + led_dev = to_cap1066_led_dev(dev); + switch (led_dev->led_mode) { + case E_SMSC_CAP1066_LED_MODE_AUTO: + str = "auto"; + break; + + case E_SMSC_CAP1066_LED_MODE_ON: + str = "on"; + break; + + case E_SMSC_CAP1066_LED_MODE_OFF: + str = "off"; + break; + + default: + str = "invalid"; + break; + } + + return sprintf(buf, "%s\n", str); +} + +static DEVICE_ATTR(control, S_IWUSR | S_IRUSR, show_control, store_control); + +static struct device_attribute *cap1066_led_dev_attrs[] = { + &dev_attr_control, +}; + +/* + * helper used to create all attributes given in the attr array. + * + * if something goes wrong during creation, remove attributes that + * have already been created. + */ +static int create_sysfs_files(struct device *dev, + struct device_attribute **attrs, + size_t count) +{ + int created; + int error = 0; + + for (created = 0; created < count; ++created) { + error = device_create_file(dev, attrs[created]); + if (error) + break; + } + + if (!error) + /* + * no errors, can return. + */ + return 0; + + /* + * errors during creation, remove already created + * files. + */ + while (--created >= 0) + device_remove_file(dev, attrs[created]); + + return error; +} + +/* + * create a led device. This will create a new directory in the sysfs + * base of the parent. a symlink will be created if a button name is + * found via get_keycode_btn_name(). + */ +static struct cap1066_led_dev *cap1066_create_led_dev(struct device *parent, + struct cap1066_priv *priv, + int index, int key_code) +{ + struct cap1066_led_dev *dev; + int error = 0; + + dev = kzalloc(sizeof (*dev), GFP_KERNEL); + if (!dev) + return NULL; + + dev->led_index = index; + dev->parent_priv = priv; + dev_set_name(&dev->dev, "led_btn_%i", index); + dev->dev.release = cap1066_led_dev_release; + dev->dev.parent = parent; + if (device_register(&dev->dev) < 0) { + kfree(dev); + return NULL; + } + + /* + * create sysfs attributes. + */ + error = create_sysfs_files(&dev->dev, cap1066_led_dev_attrs, + ARRAY_SIZE(cap1066_led_dev_attrs)); + if (error) { + device_unregister(&dev->dev); + return NULL; + } + + /* + * create sysfs symlinks to friendly names, wherever possible. + */ + dev->btn_link = get_keycode_btn_name(key_code); + if (dev->btn_link) { + error = sysfs_create_link(&parent->kobj, &dev->dev.kobj, + dev->btn_link); + if (error) + dev->btn_link = NULL; + } + return dev; +} + +static void cap1066_remove_led_dev(struct cap1066_led_dev *dev) +{ + int i; + + if (dev->btn_link) + sysfs_remove_link(&dev->dev.parent->kobj, dev->btn_link); + + for (i = 0; i < ARRAY_SIZE(cap1066_led_dev_attrs); ++i) + device_remove_file(&dev->dev, cap1066_led_dev_attrs[i]); + device_unregister(&dev->dev); + + /* + * dev->release() kfree the cap1066_led_dev struct + */ +} + +/* + * helper to exctract an unsigned long from the buffer given in + * parameter. + * + * first store buf in a zero terminated string and strtoul() it. + */ +static int get_ulong(const char *buf, size_t count, unsigned long *ret) +{ + char local_buf[32]; + unsigned long val; + const char *end; + + strncpy(local_buf, buf, min(count , sizeof (local_buf))); + local_buf[min(count, sizeof (local_buf) - 1)] = 0; + + val = simple_strtoul(local_buf, (char**)&end, 0); + if (!is_white(*end)) + /* + * garbage after end of input. + */ + return -EINVAL; + + *ret = val; + + return 0; +} + +/* + * duty cycle sysfs callbacks: things may not work as expected if + * duty_cycle_min is >= duty_cycle_max. + * + * values that can be written in duty_cycle_max/duty_cycle_min + * attributes can be on the range [0, 16 [. + * + * 0 means the lowest possible pwm duty cycle. + * 1 means the highest possible pwm duty cycle. + */ + +static ssize_t store_duty_cycle_min(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + unsigned long val; + struct i2c_client *client; + struct cap1066_priv *priv; + int error; + u8 reg; + + client = to_i2c_client(dev); + priv = i2c_get_clientdata(client); + + if (is_white(*buf)) + return 1; + + error = get_ulong(buf, count, &val); + if (error) + return error; + + if (val > 0xf) + return -ERANGE; + + cap1066_read_reg(client, SMSC_REG_LED_DIRECT_DCYCLE, ®); + reg &= ~0xf; + reg |= val; + cap1066_write_reg(client, SMSC_REG_LED_DIRECT_DCYCLE, reg); + + priv->duty_cycle_min = val; + + pr_debug(PFX "store_duty_cycle_min: reg = 0x%02x\n", reg); + return count; +} + +static ssize_t show_duty_cycle_min(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct i2c_client *client; + struct cap1066_priv *priv; + + client = to_i2c_client(dev); + priv = i2c_get_clientdata(client); + + return sprintf(buf, "%u\n", priv->duty_cycle_min); +} + +static ssize_t store_duty_cycle_max(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + unsigned long val; + struct i2c_client *client; + struct cap1066_priv *priv; + int error; + u8 reg; + + client = to_i2c_client(dev); + priv = i2c_get_clientdata(client); + + if (is_white(*buf)) + return 1; + + error = get_ulong(buf, count, &val); + if (error) + return error; + + if (val > 0xf) + return -ERANGE; + + cap1066_read_reg(client, SMSC_REG_LED_DIRECT_DCYCLE, ®); + reg &= ~0xf0; + reg |= val << 4; + cap1066_write_reg(client, SMSC_REG_LED_DIRECT_DCYCLE, reg); + + priv->duty_cycle_max = val; + + pr_debug(PFX "store_duty_cycle_max: reg = 0x%02x\n", reg); + return count; +} + +static ssize_t show_duty_cycle_max(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct i2c_client *client; + struct cap1066_priv *priv; + + client = to_i2c_client(dev); + priv = i2c_get_clientdata(client); + + return sprintf(buf, "%u\n", priv->duty_cycle_max); +} + +/* + * convert millisecond value to a "raw" value ready to be written to + * the register. + */ +static u8 msec_to_raw_ramp_time(unsigned long msec) +{ + u8 ret; + + if (msec <= 1500) + /* + * register handles 250 msec increments if below 1500 + * msec. + */ + ret = msec / 250; + else + /* + * there is no 1750 msec step, and 2000 msec is + * encoded as 0x7. + */ + ret = 0x7; + + return ret; +} + +/* + * convert raw register value to a millisecond value. + */ +static unsigned long raw_ramp_time_to_msec(u8 raw) +{ + unsigned long ret; + + if (raw < 7) + ret = 250 * raw; + else + ret = 2000; + + return ret; +} + +/* + * ramp time sysfs callbacks. delays are not reliable if programmed + * want time is higher than 1000 msec. + * + * values that can be written are on the range [0, 2000] and are given + * in milliseconds. Values higher than 2000 are clamped to 2000. shown + * values are rounded up to the next value supported by the hardware. + */ + +static ssize_t store_ramp_time_rise(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + unsigned long val; + u8 raw_val; + struct i2c_client *client; + struct cap1066_priv *priv; + int error; + u8 reg; + + client = to_i2c_client(dev); + priv = i2c_get_clientdata(client); + + if (is_white(*buf)) + return 1; + + error = get_ulong(buf, count, &val); + if (error) + return error; + + raw_val = msec_to_raw_ramp_time(val); + + cap1066_read_reg(client, SMSC_REG_LED_DIRECT_RAMP_RATE, ®); + reg &= ~(0x7 << 3); + reg |= raw_val << 3; + cap1066_write_reg(client, SMSC_REG_LED_DIRECT_RAMP_RATE, reg); + + priv->raw_ramp_time_rise = raw_val; + + pr_debug(PFX "store_ramp_time_rise: reg = %02x\n", reg); + return count; +} + +static ssize_t show_ramp_time_rise(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct i2c_client *client; + struct cap1066_priv *priv; + unsigned long msec; + + client = to_i2c_client(dev); + priv = i2c_get_clientdata(client); + + msec = raw_ramp_time_to_msec(priv->raw_ramp_time_rise); + + return sprintf(buf, "%lu\n", msec); +} + +static ssize_t store_ramp_time_fall(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + unsigned long val; + u8 raw_val; + struct i2c_client *client; + struct cap1066_priv *priv; + int error; + u8 reg; + + client = to_i2c_client(dev); + priv = i2c_get_clientdata(client); + + if (is_white(*buf)) + return 1; + + error = get_ulong(buf, count, &val); + if (error) + return error; + + raw_val = msec_to_raw_ramp_time(val); + + cap1066_read_reg(client, SMSC_REG_LED_DIRECT_RAMP_RATE, ®); + reg &= ~0x7; + reg |= raw_val; + cap1066_write_reg(client, SMSC_REG_LED_DIRECT_RAMP_RATE, reg); + + priv->raw_ramp_time_fall = raw_val; + + pr_debug(PFX "store_ramp_time_rise: reg = %02x\n", reg); + return count; +} + +static ssize_t show_ramp_time_fall(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct i2c_client *client; + struct cap1066_priv *priv; + unsigned long msec; + + client = to_i2c_client(dev); + priv = i2c_get_clientdata(client); + + msec = raw_ramp_time_to_msec(priv->raw_ramp_time_fall); + + return sprintf(buf, "%lu\n", msec); +} + +#define MTOUCH_ENABLE (1 << 7) +#define MTOUCH_COUNT_MASK (3 << 2) +#define MTOUCH_COUNT_SHIFT (2) + +/* + * touch limit handling: the hardware can report at most 1 to 4 key + * press event or no limit at all. + * + * Accepted values in touch_limit attribte: + * 0 -> no limit + * [1, 4] -> limit to the indicated count + * [4, +inf [ -> invalid + */ +static ssize_t store_touch_limit(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + struct i2c_client *client; + unsigned long limit; + int err; + u8 mtouch_reg; + + client = to_i2c_client(dev); + + if (is_white(*buf)) + return 1; + + err = get_ulong(buf, count, &limit); + if (err) + return err; + + if (limit > 4) + return -EINVAL; + + if (limit == 0) { + mtouch_reg = 0; + } else { + mtouch_reg = MTOUCH_ENABLE | + ((limit - 1) << MTOUCH_COUNT_SHIFT); + } + cap1066_write_reg(client, SMSC_REG_MTOUCH_CFG_REG, mtouch_reg); + + return count; +} + +static ssize_t show_touch_limit(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct i2c_client *client; + u8 mtouch_reg; + + client = to_i2c_client(dev); + + cap1066_read_reg(client, SMSC_REG_MTOUCH_CFG_REG, &mtouch_reg); + + if (mtouch_reg & MTOUCH_ENABLE) { + u8 count = (mtouch_reg & MTOUCH_COUNT_MASK) >> + MTOUCH_COUNT_SHIFT; + return sprintf(buf, "%d\n", count + 1); + } else { + return sprintf(buf, "0\n"); + } +} + +static DEVICE_ATTR(duty_cycle_min, S_IRUSR | S_IWUSR, show_duty_cycle_min, + store_duty_cycle_min); + +static DEVICE_ATTR(duty_cycle_max, S_IRUSR | S_IWUSR, show_duty_cycle_max, + store_duty_cycle_max); + +static DEVICE_ATTR(ramp_time_rise, S_IRUSR | S_IWUSR, show_ramp_time_rise, + store_ramp_time_rise); + +static DEVICE_ATTR(ramp_time_fall, S_IRUSR | S_IWUSR, show_ramp_time_fall, + store_ramp_time_fall); + +static DEVICE_ATTR(touch_limit, S_IWUSR | S_IRUSR, show_touch_limit, + store_touch_limit); + +static struct device_attribute *cap1066_base_attributes[] = { + &dev_attr_duty_cycle_min, + &dev_attr_duty_cycle_max, + &dev_attr_ramp_time_rise, + &dev_attr_ramp_time_fall, + &dev_attr_touch_limit, +}; + +/* + * i2c core probe callback, called after sucessful detect + */ +static int cap1066_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct device_node *np = client->dev.of_node; + struct input_polled_dev *poll_dev; + struct input_dev *input; + struct cap1066_priv *priv; + struct reset_control *reset; + int ret, i; + + priv = devm_kzalloc(&client->dev, sizeof (*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->irq_gpio = devm_gpiod_get_optional(&client->dev, + "irq", + GPIOD_IN); + if (IS_ERR(priv->irq_gpio)) { + ret = PTR_ERR(priv->irq_gpio); + if (ret != -EPROBE_DEFER) + dev_err(&client->dev, + "failed to get irq gpio :%d", ret); + return ret; + } + + if (np) { + ret = of_property_read_u32_array(np, + "keymap", + priv->keymap, + ARRAY_SIZE(priv->keymap)); + if (ret < 0) { + dev_err(&client->dev, + "bad/missing keymap property: %d", ret); + return ret; + } + } else + memcpy(priv->keymap, default_map, sizeof (priv->keymap)); + + /* un-reset if needed */ + reset = devm_reset_control_get_shared_by_index(&client->dev, 0); + if (IS_ERR(reset)) { + ret = PTR_ERR(reset); + if (ret == -ENOENT) + reset = NULL; + else if (ret != -EPROBE_DEFER){ + dev_err(&client->dev, "failed to get reset: %d\n", + ret); + return ret; + } + } + + if (reset && reset_control_status(reset)) { + reset_control_deassert(reset); + msleep(10); + } + + ret = cap1066_detect(client, NULL); + if (ret) { + if (ret != -ENODEV) + return ret; + + dev_warn(&client->dev, "unknown cap1x66 device, try anyway.\n"); + } + + /* initialize controller */ + ret = cap1066_init_hw(client); + if (ret) + return ret; + + /* allocate context */ + poll_dev = input_allocate_polled_device(); + if (!priv || !poll_dev) { + ret = -ENOMEM; + goto out_fail; + } + + /* + * must match what has been setup in cap1066_init_hw(). + */ + priv->duty_cycle_min = DEFAULT_DUTY_CYCLE_MIN; + priv->duty_cycle_max = DEFAULT_DUTY_CYCLE_MAX; + priv->raw_ramp_time_rise = DEFAULT_RAMP_TIME_RISE; + priv->raw_ramp_time_fall = DEFAULT_RAMP_TIME_FALL; + + priv->poll_dev = poll_dev; + priv->client = client; + + poll_dev->private = priv; + poll_dev->poll = cap1066_input_poll; + poll_dev->poll_interval = 50 /* ms */; + + input = poll_dev->input; + input->name = "smsc_cap1066"; + input->phys = "smsc_cap1066/input0"; + input->id.bustype = BUS_I2C; + input->dev.parent = &client->dev; + + input->keycode = priv->keymap; + input->keycodemax = ARRAY_SIZE(priv->keymap); + input->keycodesize = sizeof (unsigned short); + + set_bit(EV_REP, input->evbit); + set_bit(EV_KEY, input->evbit); + for (i = 0; i < ARRAY_SIZE(priv->keymap); i++) + set_bit(priv->keymap[i], input->keybit); + + i2c_set_clientdata(client, priv); + + ret = input_register_polled_device(poll_dev); + if (ret) + goto out_fail; + + for (i = 0; i < ARRAY_SIZE(priv->keymap); ++i) { + if (!priv->keymap[i]) + continue; + priv->led_devices[i] = + cap1066_create_led_dev(&client->dev, + priv, i, priv->keymap[i]); + } + + if (create_sysfs_files(&client->dev, cap1066_base_attributes, + ARRAY_SIZE(cap1066_base_attributes)) < 0) + goto out_free_led_devs; + + return 0; + +out_free_led_devs: + for (i = 0; i < ARRAY_SIZE(priv->keymap); ++i) + if (priv->led_devices[i]) + cap1066_remove_led_dev(priv->led_devices[i]); +out_fail: + input_free_polled_device(poll_dev); + i2c_set_clientdata(client, NULL); + return ret; +} + +/* + * i2c core remove callback + */ +static int cap1066_remove(struct i2c_client *client) +{ + int i; + struct cap1066_priv *priv = i2c_get_clientdata(client); + + for (i = 0; i < ARRAY_SIZE(cap1066_base_attributes); ++i) + device_remove_file(&client->dev, cap1066_base_attributes[i]); + + for (i = 0; i < ARRAY_SIZE(priv->keymap); ++i) { + if (priv->led_devices[i]) + cap1066_remove_led_dev(priv->led_devices[i]); + } + + input_unregister_polled_device(priv->poll_dev); + input_free_polled_device(priv->poll_dev); + + return 0; +} + +static const struct of_device_id cap1066_of_table[] = { + { .compatible = "smsc,smsc_cap1066" }, + { } +}; +MODULE_DEVICE_TABLE(of, cap1066_of_table); + +static struct i2c_driver cap1066_driver = { + .driver = { + .name = "cap1066", + .of_match_table = of_match_ptr(cap1066_of_table), + }, + .probe = cap1066_probe, + .remove = cap1066_remove, + .id_table = cap1066_id, + + .detect = cap1066_detect, + .class = I2C_CLASS_HWMON, + .address_list = normal_i2c, +}; + +static int __init cap1066_init(void) +{ + return i2c_add_driver(&cap1066_driver); +} + +static void __exit cap1066_exit(void) +{ + i2c_del_driver(&cap1066_driver); +} + + +MODULE_AUTHOR("Maxime Bizon "); +MODULE_DESCRIPTION("SMSC CAP1066 driver"); +MODULE_LICENSE("GPL"); + +module_init(cap1066_init); +module_exit(cap1066_exit); --- /dev/null 2019-09-30 09:50:43.919599165 +0200 +++ linux-4.14.127-fbx/drivers/mfd/fbxgw7r-panel.c 2019-02-15 14:29:39.570646656 +0100 @@ -0,0 +1,980 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * uc registers & commands + */ +#define UC_CMD_WRITE 0x1 +#define UC_CMD_READ 0x2 + +#define UC_REG_LEDx_MATRIX(x) (0x0 + (x)) +#define UC_REG_LED_MATRIX_BRIGHTNESS 0x20 +#define UC_REG_LED_MATRIX_REFRESH 0x21 +#define UC_REG_KEY_STATUS 0x30 +#define UC_REG_PROXIMITY_STATUS 0x31 +#define UC_REG_PROXIMITY_THRESH 0x32 +#define UC_REG_PROXIMITY_HYSTERESIS 0x33 +#define UC_REG_IRQ_STAT 0x40 +#define UC_IRQ_KEYPAD_MASK (1 << 0) +#define UC_IRQ_PROXIMITY_MASK (1 << 1) +#define UC_REG_IRQ_MASK 0x41 +#define UC_REG_LEDx_MODE(x) (0x50 + (x) * 0x10) +#define UC_REG_LEDx_MIN_BRIGHT(x) (0x51 + (x) * 0x10) +#define UC_REG_LEDx_MAX_BRIGHT(x) (0x52 + (x) * 0x10) +#define UC_REG_LEDx_BLINK_RATE(x) (0x53 + (x) * 0x10) +#define UC_REG_LEDx_TRANS_RATE(x) (0x54 + (x) * 0x10) +#define UC_REG_VERSION 0x90 +#define UC_REG_LED_MATRIX_TEST_TYPE 0xa0 +#define UC_REG_LED_MATRIX_TEST_CTRL 0xa1 +#define UC_REG_LEDx_MATRIX_TEST_RES(x) (0xa8 + (x)) +#define UC_REG_LED_MATRIX_THERM_ERR 0xbe +#define UC_REG_LIFETIME 0xC0 + +#define PANEL_COLS 24 +#define PANEL_ROWS 7 +#define PANEL_RAM_SIZE (PANEL_COLS * PANEL_ROWS / 8) +#define PANEL_KEY_COUNT 4 + +/* + * private context + */ +struct fbx_panel { + struct spi_device *spi; + unsigned long spi_last_xfer_jiffies; + struct timespec spi_last_xfer_ts; + struct gpio_desc *irq_gpio; + + /* + * input related + */ + struct input_polled_dev *poll_dev; + u32 keymap[PANEL_KEY_COUNT]; + bool key_was_pressed; + + /* + * frame buffer related + */ + + /* data ram, 8 bits per pixel */ + u8 *vmem; + unsigned int vmem_size; + + struct fb_info *fb; +}; + +/* + * fbinfo + */ +static struct fb_fix_screeninfo fbx_panel_fb_fix = { + .id = "fbxgw7r-panel", + .type = FB_TYPE_PACKED_PIXELS, + .visual = FB_VISUAL_STATIC_PSEUDOCOLOR, + .xpanstep = 0, + .ypanstep = 1, + .ywrapstep = 0, + .accel = FB_ACCEL_NONE, +}; + +static struct fb_var_screeninfo fbx_panel_fb_var = { + .bits_per_pixel = 8, + .grayscale = 1, + .nonstd = 1, + .red.length = 8, + .green.length = 8, + .blue.length = 8, +}; + +/* + * ensure proper spacing of SPI command + * uc needs at least 150us between them + */ +static void uc_spi_pre_delay(struct fbx_panel *priv) +{ + struct timespec ts, delta; + unsigned int sleep; + + /* rough measurement first */ + if (jiffies - priv->spi_last_xfer_jiffies >= 2) + return; + + getrawmonotonic(&ts); + delta = timespec_sub(ts, priv->spi_last_xfer_ts); + + if (delta.tv_sec) + return; + + if (delta.tv_nsec > 150 * 1000) + return; + + sleep = DIV_ROUND_UP((150 * 1000 - delta.tv_nsec), 1000); + udelay(sleep); +} + +static void uc_spi_post_delay(struct fbx_panel *priv) +{ + priv->spi_last_xfer_jiffies = jiffies; + getrawmonotonic(&priv->spi_last_xfer_ts); +} + +/* + * issue read command to device + */ +static int uc_read(struct fbx_panel *priv, u8 reg, u8 size, u8 *buf) +{ + u8 cmd[3] = { UC_CMD_READ, reg, size }; + int ret; + uc_spi_pre_delay(priv); + ret = spi_write_then_read(priv->spi, + cmd, ARRAY_SIZE(cmd), + buf, size); + uc_spi_post_delay(priv); + return ret; +} + +static int uc_read8(struct fbx_panel *priv, u8 reg, u8 *val) +{ + return uc_read(priv, reg, 1, val); +} + +static int uc_read32(struct fbx_panel *priv, u8 reg, u32 *val) +{ + return uc_read(priv, reg, 4, (u8 *)val); +} + +/* + * issue write command to device + */ +static int uc_write8(struct fbx_panel *priv, u8 reg, u8 val) +{ + u8 cmd[4] = { UC_CMD_WRITE, reg, 1, val }; + int ret; + uc_spi_pre_delay(priv); + ret = spi_write(priv->spi, cmd, ARRAY_SIZE(cmd)); + uc_spi_post_delay(priv); + return ret; +} + +/* + * update area + */ +static int fbx_panel_fb_update(struct fbx_panel *priv) +{ + u8 cmd[3 + (PANEL_COLS * PANEL_ROWS / 8)]; + unsigned int i; + u8 *vmem; + + vmem = priv->vmem + PANEL_COLS * priv->fb->var.yoffset; + memset(cmd, 0, sizeof (cmd)); + cmd[0] = UC_CMD_WRITE; + cmd[1] = 0; + cmd[2] = (PANEL_COLS * PANEL_ROWS) / 8; + + for (i = 0; i < 24 * 7; i++) { + cmd[3 + (i / 8)] |= (!!vmem[i] << (i % 8)); + } + + uc_spi_pre_delay(priv); + spi_write(priv->spi, cmd, ARRAY_SIZE(cmd)); + uc_spi_post_delay(priv); + + return 0; +} + +/* + * frame buffer fill rect callback + */ +static void fbx_panel_fb_fillrect(struct fb_info *info, + const struct fb_fillrect *rect) +{ + struct fbx_panel *priv = info->par; + sys_fillrect(info, rect); + fbx_panel_fb_update(priv); +} + +/* + * frame buffer copy area callback + */ +static void fbx_panel_fb_copyarea(struct fb_info *info, + const struct fb_copyarea *area) +{ + struct fbx_panel *priv = info->par; + sys_copyarea(info, area); + fbx_panel_fb_update(priv); +} + +/* + * frame buffer image blit + */ +static void fbx_panel_fb_imageblit(struct fb_info *info, + const struct fb_image *image) +{ + struct fbx_panel *priv = info->par; + sys_imageblit(info, image); + fbx_panel_fb_update(priv); +} + +/* + * frame buffer pan callback + */ +static int fbx_panel_fb_pan(struct fb_var_screeninfo *var, struct fb_info *info) +{ + struct fbx_panel *priv = info->par; + priv->fb->var.xoffset = var->xoffset; + priv->fb->var.yoffset = var->yoffset; + fbx_panel_fb_update(priv); + return 0; +} + +/* + * fram buffer set_par callback, set videomode + */ +static int fbx_panel_fb_set_par(struct fb_info *info) +{ + struct fbx_panel *priv = info->par; + fbx_panel_fb_update(priv); + return 0; +} + +static int fbx_panel_fb_check_var(struct fb_var_screeninfo *var, + struct fb_info *info) +{ + unsigned int rotate; + + rotate = var->rotate; + if (rotate != 0 && rotate != 90 && rotate != 180 && rotate != 270) + rotate = 0; + *var = info->var; + var->rotate = rotate; + return 0; +} + +/* + * frame buffer blank callback + */ +static int fbx_panel_fb_blank(int blank, struct fb_info *info) +{ + return 0; +} + +/* + * frame buffer write from userspace + */ +static ssize_t fbx_panel_fb_write(struct fb_info *info, const char __user *buf, + size_t count, loff_t *ppos) +{ + struct fbx_panel *priv = info->par; + unsigned long p = *ppos; + void *dst; + int err = 0; + unsigned long total_size; + + if (info->state != FBINFO_STATE_RUNNING) + return -EPERM; + + total_size = info->fix.smem_len; + + if (p > total_size) + return -EFBIG; + + if (count > total_size) { + err = -EFBIG; + count = total_size; + } + + if (count + p > total_size) { + if (!err) + err = -ENOSPC; + + count = total_size - p; + } + + dst = (void __force *)(info->screen_base + p); + + if (copy_from_user(dst, buf, count)) + err = -EFAULT; + + if (!err) + *ppos += count; + + fbx_panel_fb_update(priv); + + return (err) ? err : count; +} + +static struct fb_ops fbx_panel_fb_ops = { + .owner = THIS_MODULE, + .fb_write = fbx_panel_fb_write, + .fb_fillrect = fbx_panel_fb_fillrect, + .fb_copyarea = fbx_panel_fb_copyarea, + .fb_imageblit = fbx_panel_fb_imageblit, + .fb_pan_display = fbx_panel_fb_pan, + .fb_blank = fbx_panel_fb_blank, + .fb_check_var = fbx_panel_fb_check_var, + .fb_set_par = fbx_panel_fb_set_par, +}; + +/* + * input core poll callback + */ +static void fbx_panel_input_poll(struct input_polled_dev *dev) +{ + struct fbx_panel *priv = dev->private; + struct input_dev *input = dev->input; + unsigned int i; + int ret; + u8 val; + + if (priv->irq_gpio) { + if (gpiod_get_value(priv->irq_gpio)) { + /* no IRQ pending, if any key was previously + * pressed, we need to poll to maintain key + * repeat */ + if (!priv->key_was_pressed) + return; + } + + /* clear interrupt */ + uc_write8(priv, UC_REG_IRQ_STAT, 3); + } + + ret = uc_read8(priv, UC_REG_KEY_STATUS, &val); + if (ret) { + dev_err(&priv->spi->dev, "unable to read keypad status\n"); + return; + } + + for (i = 0; i < ARRAY_SIZE(priv->keymap); i++) + input_report_key(input, priv->keymap[i], + val & (1 << i)); + + input_sync(input); + priv->key_was_pressed = val; +} + +static ssize_t panel_gen_reg_show(struct device *dev, u8 reg, char *buf) +{ + struct fbx_panel *priv = dev_get_drvdata(dev); + u8 val; + int ret; + + ret = uc_read8(priv, reg, &val); + if (ret) + return ret; + return sprintf(buf, "%u\n", val); +} + +static ssize_t panel_gen_reg32_show(struct device *dev, u8 reg, char *buf) +{ + struct fbx_panel *priv = dev_get_drvdata(dev); + u32 val; + int ret; + + ret = uc_read32(priv, reg, &val); + if (ret) + return ret; + return sprintf(buf, "%u\n", val); +} + +static ssize_t panel_gen_reg_store(struct device *dev, u8 reg, + const char *buf, size_t len) +{ + struct fbx_panel *priv = dev_get_drvdata(dev); + unsigned long value; + int ret; + + ret = kstrtoul(buf, 0, &value); + if (ret) + return ret; + + if (value > 255) + return -EINVAL; + + ret = uc_write8(priv, reg, value); + if (ret) + return ret; + + return len; +} + +static ssize_t panel_matrix_brightness_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return panel_gen_reg_show(dev, UC_REG_LED_MATRIX_BRIGHTNESS, buf); +} + +static ssize_t panel_matrix_brightness_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + return panel_gen_reg_store(dev, UC_REG_LED_MATRIX_BRIGHTNESS, + buf, len); +} + +static ssize_t panel_matrix_refresh_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return panel_gen_reg_show(dev, UC_REG_LED_MATRIX_REFRESH, buf); +} + +static ssize_t panel_matrix_refresh_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + return panel_gen_reg_store(dev, UC_REG_LED_MATRIX_REFRESH, + buf, len); +} + +static ssize_t panel_proximity_status_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return panel_gen_reg_show(dev, UC_REG_PROXIMITY_STATUS, buf); +} + +static ssize_t panel_proximity_thresh_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return panel_gen_reg_show(dev, UC_REG_PROXIMITY_THRESH, buf); +} + +static ssize_t panel_proximity_thresh_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + return panel_gen_reg_store(dev, UC_REG_PROXIMITY_THRESH, + buf, len); +} + +static ssize_t panel_proximity_hysteresis_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return panel_gen_reg_show(dev, UC_REG_PROXIMITY_HYSTERESIS, buf); +} + +static ssize_t panel_proximity_hysteresis_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + return panel_gen_reg_store(dev, UC_REG_PROXIMITY_HYSTERESIS, + buf, len); +} + +static ssize_t panel_version_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return panel_gen_reg_show(dev, UC_REG_VERSION, buf); +} + +static ssize_t panel_lifetime_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return panel_gen_reg32_show(dev, UC_REG_LIFETIME, buf); +} + +static ssize_t panel_matrix_test_type_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return panel_gen_reg_show(dev, UC_REG_LED_MATRIX_TEST_TYPE, buf); +} + +static ssize_t panel_matrix_test_type_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + return panel_gen_reg_store(dev, UC_REG_LED_MATRIX_TEST_TYPE, + buf, len); +} + +static ssize_t panel_matrix_test_control_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return panel_gen_reg_show(dev, UC_REG_LED_MATRIX_TEST_CTRL, buf); +} + +static ssize_t panel_matrix_test_control_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + return panel_gen_reg_store(dev, UC_REG_LED_MATRIX_TEST_CTRL, + buf, len); +} + +static ssize_t panel_matrix_test_results_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct fbx_panel *priv = dev_get_drvdata(dev); + u8 results[(PANEL_COLS * PANEL_ROWS) / 8]; + size_t i, len; + int ret; + + ret = uc_read(priv, UC_REG_LEDx_MATRIX_TEST_RES(0), + sizeof (results), results); + if (ret) + return ret; + + len = 0; + for (i = 0; i < sizeof (results); i++) + len += sprintf(buf + len, "%02x", results[i]); + len += sprintf(buf + len, "\n"); + return len; +} + +static ssize_t panel_matrix_test_thermal_err_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return panel_gen_reg_show(dev, UC_REG_LED_MATRIX_THERM_ERR, buf); +} + +static ssize_t panel_key_status_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return panel_gen_reg_show(dev, UC_REG_KEY_STATUS, buf); +} + +static DEVICE_ATTR_RW(panel_matrix_brightness); +static DEVICE_ATTR_RW(panel_matrix_refresh); +static DEVICE_ATTR_RW(panel_matrix_test_type); +static DEVICE_ATTR_RW(panel_matrix_test_control); +static DEVICE_ATTR_RO(panel_matrix_test_results); +static DEVICE_ATTR_RO(panel_matrix_test_thermal_err); +static DEVICE_ATTR_RO(panel_key_status); + +static DEVICE_ATTR_RO(panel_proximity_status); +static DEVICE_ATTR_RW(panel_proximity_thresh); +static DEVICE_ATTR_RW(panel_proximity_hysteresis); +static DEVICE_ATTR_RO(panel_version); +static DEVICE_ATTR_RO(panel_lifetime); + +static ssize_t panel_led_gen_reg_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct dev_ext_attribute *eattr; + unsigned int reg; + eattr = container_of(attr, struct dev_ext_attribute, attr); + reg = (unsigned long)eattr->var; + return panel_gen_reg_show(dev, reg, buf); +} + +static ssize_t panel_led_gen_reg_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + struct dev_ext_attribute *eattr; + unsigned int reg; + eattr = container_of(attr, struct dev_ext_attribute, attr); + reg = (unsigned long)eattr->var; + return panel_gen_reg_store(dev, reg, buf, len); +} + +static struct { + u8 val; + const char *mode; +} led_modes[] = { + { 0, "off" }, + { 1, "min" }, + { 2, "max" }, + { 3, "blink" }, + { 4, "auto" }, +}; + +static ssize_t panel_led_mode_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct fbx_panel *priv = dev_get_drvdata(dev); + struct dev_ext_attribute *eattr; + unsigned int led; + const char *str; + size_t i; + int ret; + u8 val; + + eattr = container_of(attr, struct dev_ext_attribute, attr); + led = (unsigned long)eattr->var; + ret = uc_read8(priv, UC_REG_LEDx_MODE(led), &val); + if (ret) + return ret; + + str = NULL; + for (i = 0; i < ARRAY_SIZE(led_modes); i++) { + if (led_modes[i].val == val) { + str = led_modes[i].mode; + break; + } + } + + if (!str) + str = "unknown"; + + return sprintf(buf, "%s\n", str); +} + + +static int is_white(int c) +{ + return c == '\0' || c == ' ' || c == '\t' || c == '\n' || c == '\r'; +} + +static ssize_t panel_led_mode_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + struct fbx_panel *priv = dev_get_drvdata(dev); + struct dev_ext_attribute *eattr; + unsigned int led; + size_t i, read_len; + int ret; + u8 val; + + /* ignore leading whitespaces */ + if (is_white(*buf)) + return 1; + + eattr = container_of(attr, struct dev_ext_attribute, attr); + led = (unsigned long)eattr->var; + + read_len = 0; + for (i = 0; i < ARRAY_SIZE(led_modes); i++) { + size_t mode_len = strlen(led_modes[i].mode); + + if (len < mode_len) + continue; + + if (!strncmp(buf, led_modes[i].mode, mode_len) && + is_white(buf[mode_len])) { + read_len = mode_len; + break; + } + } + + if (!read_len) { + dev_err(dev, "invalid led mode value"); + return -EINVAL; + } + + ret = uc_read8(priv, UC_REG_LEDx_MODE(led), &val); + if (ret) + return ret; + + if (val == led_modes[i].val) + return read_len; + + ret = uc_write8(priv, UC_REG_LEDx_MODE(led), led_modes[i].val); + if (ret) + return ret; + + return read_len; +} + +#define PANEL_LED_ATTR(_name, _func, _led) \ + struct dev_ext_attribute \ + dev_attr_panel_led_ ## _name ## _ ## _func = { \ + .attr = __ATTR(panel_led_ ## _name ## _ ## _func, \ + S_IRUGO | S_IWUSR, \ + panel_led_ ## _func ## _show, \ + panel_led_ ## _func ## _store \ + ), \ + .var = (void *) _led, \ + } + +#define PANEL_LED_REG_ATTR(_name, _func, _ledreg) \ + struct dev_ext_attribute \ + dev_attr_panel_led_ ## _name ## _ ## _func = { \ + .attr = __ATTR(panel_led_ ## _name ## _ ## _func, \ + S_IRUGO | S_IWUSR, \ + panel_led_gen_reg_show, \ + panel_led_gen_reg_store \ + ), \ + .var = (void *) _ledreg, \ + } + +static PANEL_LED_REG_ATTR(up, min_brightness, UC_REG_LEDx_MIN_BRIGHT(1)); +static PANEL_LED_REG_ATTR(up, max_brightness, UC_REG_LEDx_MAX_BRIGHT(1)); +static PANEL_LED_REG_ATTR(up, blink_rate, UC_REG_LEDx_BLINK_RATE(1)); +static PANEL_LED_REG_ATTR(up, trans_rate, UC_REG_LEDx_TRANS_RATE(1)); +static PANEL_LED_ATTR(up, mode, 1); + +static PANEL_LED_REG_ATTR(down, min_brightness, UC_REG_LEDx_MIN_BRIGHT(3)); +static PANEL_LED_REG_ATTR(down, max_brightness, UC_REG_LEDx_MAX_BRIGHT(3)); +static PANEL_LED_REG_ATTR(down, blink_rate, UC_REG_LEDx_BLINK_RATE(3)); +static PANEL_LED_REG_ATTR(down, trans_rate, UC_REG_LEDx_TRANS_RATE(3)); +static PANEL_LED_ATTR(down, mode, 3); + +static PANEL_LED_REG_ATTR(cancel, min_brightness, UC_REG_LEDx_MIN_BRIGHT(2)); +static PANEL_LED_REG_ATTR(cancel, max_brightness, UC_REG_LEDx_MAX_BRIGHT(2)); +static PANEL_LED_REG_ATTR(cancel, blink_rate, UC_REG_LEDx_BLINK_RATE(2)); +static PANEL_LED_REG_ATTR(cancel, trans_rate, UC_REG_LEDx_TRANS_RATE(2)); +static PANEL_LED_ATTR(cancel, mode, 2); + +static PANEL_LED_REG_ATTR(ok, min_brightness, UC_REG_LEDx_MIN_BRIGHT(0)); +static PANEL_LED_REG_ATTR(ok, max_brightness, UC_REG_LEDx_MAX_BRIGHT(0)); +static PANEL_LED_REG_ATTR(ok, blink_rate, UC_REG_LEDx_BLINK_RATE(0)); +static PANEL_LED_REG_ATTR(ok, trans_rate, UC_REG_LEDx_TRANS_RATE(0)); +static PANEL_LED_ATTR(ok, mode, 0); + + +static struct attribute *sysfs_attrs_ctrl[] = { + &dev_attr_panel_matrix_brightness.attr, + &dev_attr_panel_matrix_refresh.attr, + &dev_attr_panel_matrix_test_type.attr, + &dev_attr_panel_matrix_test_control.attr, + &dev_attr_panel_matrix_test_results.attr, + &dev_attr_panel_matrix_test_thermal_err.attr, + + &dev_attr_panel_key_status.attr, + + &dev_attr_panel_proximity_status.attr, + &dev_attr_panel_proximity_thresh.attr, + &dev_attr_panel_proximity_hysteresis.attr, + &dev_attr_panel_version.attr, + &dev_attr_panel_lifetime.attr, + + &dev_attr_panel_led_up_min_brightness.attr.attr, + &dev_attr_panel_led_up_max_brightness.attr.attr, + &dev_attr_panel_led_up_blink_rate.attr.attr, + &dev_attr_panel_led_up_trans_rate.attr.attr, + &dev_attr_panel_led_up_mode.attr.attr, + + &dev_attr_panel_led_down_min_brightness.attr.attr, + &dev_attr_panel_led_down_max_brightness.attr.attr, + &dev_attr_panel_led_down_blink_rate.attr.attr, + &dev_attr_panel_led_down_trans_rate.attr.attr, + &dev_attr_panel_led_down_mode.attr.attr, + + &dev_attr_panel_led_cancel_min_brightness.attr.attr, + &dev_attr_panel_led_cancel_max_brightness.attr.attr, + &dev_attr_panel_led_cancel_blink_rate.attr.attr, + &dev_attr_panel_led_cancel_trans_rate.attr.attr, + &dev_attr_panel_led_cancel_mode.attr.attr, + + &dev_attr_panel_led_ok_min_brightness.attr.attr, + &dev_attr_panel_led_ok_max_brightness.attr.attr, + &dev_attr_panel_led_ok_blink_rate.attr.attr, + &dev_attr_panel_led_ok_trans_rate.attr.attr, + &dev_attr_panel_led_ok_mode.attr.attr, + NULL +}; + +static const struct attribute_group panel_attribute_group[] = { + {.attrs = sysfs_attrs_ctrl }, +}; + +/* + * SPI device probe callback + */ +static int fbxgw7r_panel_spi_probe(struct spi_device *spi) +{ + struct input_dev *input; + struct fbx_panel *priv; + struct fb_info *fb = NULL; + unsigned int i; + u8 version; + int ret; + + priv = devm_kzalloc(&spi->dev, sizeof (*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->spi = spi; + + priv->irq_gpio = devm_gpiod_get_optional(&spi->dev, "irq", GPIOD_IN); + if (IS_ERR(priv->irq_gpio)) { + ret = PTR_ERR(priv->irq_gpio); + if (ret != -EPROBE_DEFER) + dev_err(&spi->dev, + "failed to get irq gpio :%d", ret); + return ret; + } + + ret = sysfs_create_group(&spi->dev.kobj, + panel_attribute_group); + if (ret < 0) { + dev_err(&spi->dev, "Sysfs registration failed\n"); + goto fail; + } + + /* + * setup input + */ + priv->keymap[0] = KEY_OK; + priv->keymap[1] = KEY_UP; + priv->keymap[2] = KEY_CANCEL; + priv->keymap[3] = KEY_DOWN; + + priv->poll_dev = devm_input_allocate_polled_device(&spi->dev); + if (!priv->poll_dev) { + ret = -ENOMEM; + goto fail; + } + + priv->poll_dev->private = priv; + priv->poll_dev->poll = fbx_panel_input_poll; + priv->poll_dev->poll_interval = 100 /* ms */; + + input = priv->poll_dev->input; + input->name = "fbxgw7r_panel"; + input->phys = "fbxgw7r_panel/input0"; + input->id.bustype = BUS_SPI; + input->dev.parent = &spi->dev; + + input->keycode = priv->keymap; + input->keycodemax = ARRAY_SIZE(priv->keymap); + input->keycodesize = sizeof (unsigned short); + + set_bit(EV_REP, input->evbit); + set_bit(EV_KEY, input->evbit); + for (i = 0; i < ARRAY_SIZE(priv->keymap); i++) + set_bit(priv->keymap[i], input->keybit); + + ret = input_register_polled_device(priv->poll_dev); + if (ret) + goto fail; + + /* + * setup framebuffer + */ + fb = framebuffer_alloc(0, &spi->dev); + if (!fb) { + ret = -ENOMEM; + goto fail; + } + + priv->fb = fb; + fb->par = priv; + + /* setup framebuffer */ + fb->fbops = &fbx_panel_fb_ops; + fb->flags = FBINFO_FLAG_DEFAULT | FBINFO_HWACCEL_YPAN; + fb->var = fbx_panel_fb_var; + fb->fix = fbx_panel_fb_fix; + + fb->var.xres = PANEL_COLS; + fb->var.yres = PANEL_ROWS; + fb->var.xres_virtual = PANEL_COLS; + fb->var.yres_virtual = PANEL_ROWS * 2; + + /* twice lcd size so we can pan in one direction */ + fb->fix.smem_len = (PANEL_COLS * PANEL_ROWS) * 2; + fb->fix.line_length = PANEL_COLS; + fb->var.rotate = 0; + + /* allocate video memory */ + priv->vmem_size = PAGE_ALIGN(fb->fix.smem_len); + priv->vmem = vmalloc(priv->vmem_size); + if (!priv->vmem) { + ret = -ENOMEM; + goto fail; + } + memset(priv->vmem, 0, priv->vmem_size); + fb->screen_base = (char __iomem *)priv->vmem; + + /* register frame buffer */ + ret = register_framebuffer(fb); + if (ret < 0) + goto fail; + + ret = uc_read8(priv, UC_REG_VERSION, &version); + if (ret < 0) { + dev_err(&spi->dev, "spi read error: %d", ret); + goto fail; + } + + dev_info(&spi->dev, + "fb%d: Freebox v7 panel device, version 0x%02x\n", + fb->node, version); + + /* unmask irq */ + if (priv->irq_gpio) + uc_write8(priv, UC_REG_IRQ_MASK, UC_IRQ_KEYPAD_MASK); + + dev_set_drvdata(&spi->dev, priv); + return 0; + +fail: + sysfs_remove_group(&spi->dev.kobj, panel_attribute_group); + if (priv->vmem) + vfree(priv->vmem); + if (fb) + framebuffer_release(fb); + return ret; +} + +/* + * spi device remove callback + */ +static int fbxgw7r_panel_spi_remove(struct spi_device *spi) +{ + struct fbx_panel *priv; + + priv = dev_get_drvdata(&spi->dev); + sysfs_remove_group(&spi->dev.kobj, panel_attribute_group); + unregister_framebuffer(priv->fb); + vfree(priv->vmem); + framebuffer_release(priv->fb); + return 0; +} + +const struct of_device_id fbxgw7r_panel_match[] = { + { .compatible = "freebox,fbxgw7r-panel" }, + { }, +}; + +static struct spi_driver fbxgw7r_panel_spi_driver = { + .driver = { + .name = "fbxgw7r_panel", + .of_match_table = of_match_ptr(fbxgw7r_panel_match), + }, + + .probe = fbxgw7r_panel_spi_probe, + .remove = fbxgw7r_panel_spi_remove, +}; + +static int __init fbxgw7r_panel_spi_init(void) +{ + int ret; + + ret = spi_register_driver(&fbxgw7r_panel_spi_driver); + if (ret != 0) + pr_err("Failed to register WM831x SPI driver: %d\n", ret); + + return 0; +} + +static void __exit fbxgw7r_panel_spi_exit(void) +{ + spi_unregister_driver(&fbxgw7r_panel_spi_driver); +} + +module_init(fbxgw7r_panel_spi_init); +module_exit(fbxgw7r_panel_spi_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Maxime Bizon"); --- /dev/null 2019-09-30 09:50:43.919599165 +0200 +++ linux-4.14.127-fbx/drivers/misc/eeprom/ee1004_raw.c 2019-02-15 14:29:39.594646751 +0100 @@ -0,0 +1,351 @@ +/* + * ee1004 - driver for DDR4 SPD EEPROMs, without smbus + */ + +#include +#include +#include +#include +#include +#include +#include + +#define EE1004_ADDR_SET_PAGE 0x36 +#define EE1004_EEPROM_SIZE 512 +#define EE1004_PAGE_SIZE 256 +#define EE1004_PAGE_SHIFT 8 + +/* + * Mutex protects ee1004_set_page and ee1004_dev_count, and must be held + * from page selection to end of read. + */ +static DEFINE_MUTEX(ee1004_bus_lock); +static struct i2c_client *ee1004_set_page[2]; +static unsigned int ee1004_dev_count; +static int ee1004_current_page; + +static unsigned write_timeout = 25; +module_param(write_timeout, uint, 0); +MODULE_PARM_DESC(write_timeout, "Time (in ms) to try writes (default 25)"); + +static const struct i2c_device_id ee1004_ids[] = { + { "ee1004", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, ee1004_ids); + +#define loop_until_timeout(tout, op_time) \ + for (tout = jiffies + msecs_to_jiffies(write_timeout), op_time = 0; \ + op_time ? time_before(op_time, tout) : true; \ + usleep_range(1000, 1500), op_time = jiffies) + +/*-------------------------------------------------------------------------*/ + +static ssize_t ee1004_eeprom_read(struct i2c_client *client, char *buf, + unsigned int offset, size_t count) +{ + int status; + + if (count > I2C_SMBUS_BLOCK_MAX) + count = I2C_SMBUS_BLOCK_MAX; + /* Can't cross page boundaries */ + if (unlikely(offset + count > EE1004_PAGE_SIZE)) + count = EE1004_PAGE_SIZE - offset; + + status = i2c_smbus_read_i2c_block_data_or_emulated(client, offset, + count, buf); + dev_dbg(&client->dev, "read %zu@%d --> %d\n", count, offset, status); + + return status; +} + +static ssize_t ee1004_read(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count) +{ + struct device *dev = kobj_to_dev(kobj); + struct i2c_client *client = to_i2c_client(dev); + size_t requested = count; + int page; + + if (unlikely(!count)) + return count; + + page = off >> EE1004_PAGE_SHIFT; + if (unlikely(page > 1)) + return 0; + off &= (1 << EE1004_PAGE_SHIFT) - 1; + + /* + * Read data from chip, protecting against concurrent access to + * other EE1004 SPD EEPROMs on the same adapter. + */ + mutex_lock(&ee1004_bus_lock); + + while (count) { + int status; + + /* Select page */ + if (page != ee1004_current_page) { + struct i2c_msg msg; + char buf[2]; + + memset(&msg, 0, sizeof (msg)); + msg.addr = ee1004_set_page[page]->addr; + msg.flags = I2C_M_IGNORE_NAK; + msg.len = 2; + msg.buf = buf; + + status = i2c_transfer(client->adapter, &msg, 1); + if (status < 0) { + dev_err(dev, "Failed to select page %d (%d)\n", + page, status); + mutex_unlock(&ee1004_bus_lock); + return status; + } + dev_dbg(dev, "Selected page %d\n", page); + ee1004_current_page = page; + } + + status = ee1004_eeprom_read(client, buf, off, count); + if (status < 0) { + mutex_unlock(&ee1004_bus_lock); + return status; + } + buf += status; + off += status; + count -= status; + + if (off == EE1004_PAGE_SIZE) { + page++; + off = 0; + } + } + + mutex_unlock(&ee1004_bus_lock); + + return requested; +} + +static ssize_t ee1004_eeprom_write(struct i2c_client *client, char *buf, + unsigned int offset, size_t count) +{ + unsigned long timeout, write_time; + int status; + + /* Can't cross page boundaries */ + if (unlikely(offset + count > EE1004_PAGE_SIZE)) + count = EE1004_PAGE_SIZE - offset; + + loop_until_timeout(timeout, write_time) { + status = i2c_smbus_write_byte_data(client, offset, buf[0]); + if (status == 0) + status = 1; + + dev_dbg(&client->dev, "write %zu@%d --> %d\n", count, offset, status); + if (status == 1) + return 1; + } + + return -ETIMEDOUT; +} + +static ssize_t ee1004_write(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count) +{ + struct device *dev = kobj_to_dev(kobj); + struct i2c_client *client = to_i2c_client(dev); + size_t requested = count; + int page; + + if (unlikely(!count)) + return count; + + page = off >> EE1004_PAGE_SHIFT; + if (unlikely(page > 1)) + return 0; + off &= (1 << EE1004_PAGE_SHIFT) - 1; + + mutex_lock(&ee1004_bus_lock); + + while (count) { + int status; + + /* Select page */ + if (page != ee1004_current_page) { + struct i2c_msg msg; + char buf[2]; + + memset(&msg, 0, sizeof (msg)); + msg.addr = ee1004_set_page[page]->addr; + msg.flags = I2C_M_IGNORE_NAK; + msg.len = 2; + msg.buf = buf; + + status = i2c_transfer(client->adapter, &msg, 1); + if (status < 0) { + dev_err(dev, "Failed to select page %d (%d)\n", + page, status); + mutex_unlock(&ee1004_bus_lock); + return status; + } + dev_dbg(dev, "Selected page %d\n", page); + ee1004_current_page = page; + } + + status = ee1004_eeprom_write(client, buf, off, count); + if (status < 0) { + mutex_unlock(&ee1004_bus_lock); + return status; + } + buf += status; + off += status; + count -= status; + + if (off == EE1004_PAGE_SIZE) { + page++; + off = 0; + } + } + + mutex_unlock(&ee1004_bus_lock); + + return requested; +} + +static const struct bin_attribute eeprom_attr = { + .attr = { + .name = "eeprom", + .mode = 0600, + }, + .size = EE1004_EEPROM_SIZE, + .read = ee1004_read, + .write = ee1004_write, +}; + +static int ee1004_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int err, cnr = 0; + unsigned char buf[4]; + struct i2c_msg msg; + + if (!i2c_check_functionality(client->adapter, + I2C_FUNC_PROTOCOL_MANGLING)) + return -EPFNOSUPPORT; + + /* Use 2 dummy devices for page select command */ + mutex_lock(&ee1004_bus_lock); + if (++ee1004_dev_count == 1) { + for (cnr = 0; cnr < 2; cnr++) { + ee1004_set_page[cnr] = i2c_new_dummy(client->adapter, + EE1004_ADDR_SET_PAGE + cnr); + if (!ee1004_set_page[cnr]) { + dev_err(&client->dev, + "address 0x%02x unavailable\n", + EE1004_ADDR_SET_PAGE + cnr); + err = -EADDRINUSE; + goto err_clients; + } + } + } else if (i2c_adapter_id(client->adapter) != + i2c_adapter_id(ee1004_set_page[0]->adapter)) { + dev_err(&client->dev, + "Driver only supports devices on a single I2C bus\n"); + err = -EOPNOTSUPP; + goto err_clients; + } + + memset(&msg, 0, sizeof (msg)); + msg.addr = ee1004_set_page[0]->addr; + msg.flags = I2C_M_RD | I2C_M_NO_RD_ACK; + msg.len = 1; + msg.buf = buf; + + /* Remember current page to avoid unneeded page select */ + err = i2c_transfer(client->adapter, &msg, 1); + if (err == -ENXIO) { + /* Nack means page 1 is selected */ + ee1004_current_page = 1; + } else if (err < 0) { + /* Anything else is a real error, bail out */ + goto err_clients; + } else { + /* Ack means page 0 is selected, returned value meaningless */ + ee1004_current_page = 0; + } + dev_dbg(&client->dev, "Currently selected page: %d\n", + ee1004_current_page); + mutex_unlock(&ee1004_bus_lock); + + /* Create the sysfs eeprom file */ + err = sysfs_create_bin_file(&client->dev.kobj, &eeprom_attr); + if (err) + goto err_clients_lock; + + dev_info(&client->dev, + "%u byte EE1004-compliant SPD EEPROM, read-only\n", + EE1004_EEPROM_SIZE); + + return 0; + + err_clients_lock: + mutex_lock(&ee1004_bus_lock); + err_clients: + if (--ee1004_dev_count == 0) { + for (cnr--; cnr >= 0; cnr--) { + i2c_unregister_device(ee1004_set_page[cnr]); + ee1004_set_page[cnr] = NULL; + } + } + mutex_unlock(&ee1004_bus_lock); + + return err; +} + +static int ee1004_remove(struct i2c_client *client) +{ + int i; + + sysfs_remove_bin_file(&client->dev.kobj, &eeprom_attr); + + /* Remove page select clients if this is the last device */ + mutex_lock(&ee1004_bus_lock); + if (--ee1004_dev_count == 0) { + for (i = 0; i < 2; i++) { + i2c_unregister_device(ee1004_set_page[i]); + ee1004_set_page[i] = NULL; + } + } + mutex_unlock(&ee1004_bus_lock); + + return 0; +} + +/*-------------------------------------------------------------------------*/ + +static struct i2c_driver ee1004_raw_driver = { + .driver = { + .name = "ee1004_raw", + }, + .probe = ee1004_probe, + .remove = ee1004_remove, + .id_table = ee1004_ids, +}; + +static int __init ee1004_raw_init(void) +{ + return i2c_add_driver(&ee1004_raw_driver); +} +module_init(ee1004_raw_init); + +static void __exit ee1004_raw_exit(void) +{ + i2c_del_driver(&ee1004_raw_driver); +} +module_exit(ee1004_raw_exit); + +MODULE_DESCRIPTION("Driver for EE1004-compliant DDR4 SPD EEPROMs raw mode"); +MODULE_AUTHOR("Maxime Bizon"); +MODULE_LICENSE("GPL"); --- /dev/null 2019-09-30 09:50:43.919599165 +0200 +++ linux-4.14.127-fbx/drivers/misc/fbxserial_of.c 2019-02-15 14:29:39.598646767 +0100 @@ -0,0 +1,38 @@ +#include +#include +#include +#include + +static struct fbx_serial serial_info; + +const struct fbx_serial *arch_get_fbxserial(void) +{ + return &serial_info; +} + +EXPORT_SYMBOL(arch_get_fbxserial); + +/* + * + */ +static __init int fbxserial_of_read(void) +{ + struct device_node *np; + const void *fbxserial_data; + int len; + + np = of_find_node_by_path("/chosen"); + if (!np) + return 0; + + fbxserial_data = of_get_property(np, "fbx,serialinfo", &len); + if (!fbxserial_data) + return 0; + + fbxserialinfo_read(fbxserial_data, &serial_info); + add_device_randomness(&serial_info, sizeof (serial_info)); + + return 0; +} + +arch_initcall(fbxserial_of_read); diff -Nruw linux-4.14.127-fbx/drivers/misc/hdmi-cec./Kconfig linux-4.14.127-fbx/drivers/misc/hdmi-cec/Kconfig --- linux-4.14.127-fbx/drivers/misc/hdmi-cec./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/drivers/misc/hdmi-cec/Kconfig 2019-02-15 14:29:39.598646767 +0100 @@ -0,0 +1,15 @@ +menu "HDMI CEC support" + +config HDMI_CEC + tristate "HDMI CEC (Consumer Electronics Control) support" + ---help--- + HDMI Consumer Electronics Control support. + +config HDMI_CEC_REMOTI + tristate "RemoTI CEC driver" + depends on HDMI_CEC + select REMOTI + ---help--- + HDMI CEC driver using RemoTI IPCs. + +endmenu diff -Nruw linux-4.14.127-fbx/drivers/misc/hdmi-cec./Makefile linux-4.14.127-fbx/drivers/misc/hdmi-cec/Makefile --- linux-4.14.127-fbx/drivers/misc/hdmi-cec./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/drivers/misc/hdmi-cec/Makefile 2019-02-15 14:29:39.598646767 +0100 @@ -0,0 +1,6 @@ +obj-$(CONFIG_HDMI_CEC) += hdmi-cec.o +hdmi-cec-objs += core.o dev.o + +# drivers +obj-$(CONFIG_HDMI_CEC_REMOTI) += remoti-cec.o +remoti-cec-objs := remoti.o diff -Nruw linux-4.14.127-fbx/drivers/misc/remoti./Kconfig linux-4.14.127-fbx/drivers/misc/remoti/Kconfig --- linux-4.14.127-fbx/drivers/misc/remoti./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/drivers/misc/remoti/Kconfig 2019-02-15 14:29:39.614646830 +0100 @@ -0,0 +1,26 @@ +menu "RemoTI support" + +config REMOTI + tristate "RemoTI support" + depends on FBX6HD + ---help--- + Texas Instruments RemoTI stack. + +config REMOTI_LEDS + tristate "RemoTI LEDS support" + depends on REMOTI + depends on LEDS_CLASS + ---help--- + RemoTI LEDS class driver support. + +config REMOTI_GPIO + tristate "RemoTI gpio support" + depends on REMOTI + ---help--- + gpiochip driver for the RemoTI RNP + +config REMOTI_USER + tristate "RemoTI userspace access" + depends on REMOTI + +endmenu diff -Nruw linux-4.14.127-fbx/drivers/misc/remoti./Makefile linux-4.14.127-fbx/drivers/misc/remoti/Makefile --- linux-4.14.127-fbx/drivers/misc/remoti./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/drivers/misc/remoti/Makefile 2019-02-15 14:29:39.614646830 +0100 @@ -0,0 +1,9 @@ +obj-$(CONFIG_REMOTI) += remoti.o +obj-$(CONFIG_REMOTI_GPIO) += remoti-gpio.o +obj-$(CONFIG_REMOTI_LEDS) += remoti-leds.o +obj-$(CONFIG_REMOTI_USER) += remoti-user.o + +remoti-objs := core.o core-sysfs.o +remoti-gpio-objs := gpio.o +remoti-leds-objs := leds.o +remoti-user-objs := user.o diff -Nruw linux-4.14.127-fbx/drivers/net/ethernet/broadcom/bcm63xx_enet_runner./Makefile linux-4.14.127-fbx/drivers/net/ethernet/broadcom/bcm63xx_enet_runner/Makefile --- linux-4.14.127-fbx/drivers/net/ethernet/broadcom/bcm63xx_enet_runner./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/drivers/net/ethernet/broadcom/bcm63xx_enet_runner/Makefile 2019-02-15 14:29:39.810647607 +0100 @@ -0,0 +1,5 @@ +obj-$(CONFIG_BCM63XX_ENET_RUNNER) += bcm63xx_enet_runner_mod.o +obj-$(CONFIG_BCM63XX_ENET_RUNNER) += bcm63xx_sf2.o + +bcm63xx_enet_runner_mod-y += bcm63xx_enet_runner.o +bcm63xx_enet_runner_mod-$(CONFIG_DEBUG_FS) += bcm63xx_enet_runner_debug.o diff -Nruw linux-4.14.127-fbx/drivers/net/ethernet/wintegra./Kconfig linux-4.14.127-fbx/drivers/net/ethernet/wintegra/Kconfig --- linux-4.14.127-fbx/drivers/net/ethernet/wintegra./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/drivers/net/ethernet/wintegra/Kconfig 2019-02-15 14:29:40.238649303 +0100 @@ -0,0 +1,10 @@ +config NET_VENDOR_WINTEGRA + bool + +config WINTEGRA_WINPATH3_ETH + tristate "Wintegra Winpath3 internal mac support" + depends on WINTEGRA_WINPATH3 + select NET_VENDOR_WINTEGRA + select NET_CORE + select MII + select PHYLIB diff -Nruw linux-4.14.127-fbx/drivers/net/ethernet/wintegra./Makefile linux-4.14.127-fbx/drivers/net/ethernet/wintegra/Makefile --- linux-4.14.127-fbx/drivers/net/ethernet/wintegra./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/drivers/net/ethernet/wintegra/Makefile 2019-02-15 14:29:40.238649303 +0100 @@ -0,0 +1 @@ +obj-$(CONFIG_WINTEGRA_WINPATH3_ETH) += wp3_eth.o --- /dev/null 2019-09-30 09:50:43.919599165 +0200 +++ linux-4.14.127-fbx/drivers/of/configfs.c 2019-02-15 14:29:40.706651158 +0100 @@ -0,0 +1,312 @@ +/* + * Configfs entries for device-tree + * + * Copyright (C) 2013 - Pantelis Antoniou + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "of_private.h" + +struct cfs_overlay_item { + struct config_item item; + + char path[PATH_MAX]; + + const struct firmware *fw; + struct device_node *overlay; + int ov_id; + + void *dtbo; + int dtbo_size; +}; + +static int create_overlay(struct cfs_overlay_item *overlay, void *blob) +{ + int err; + + /* unflatten the tree */ + of_fdt_unflatten_tree(blob, NULL, &overlay->overlay); + if (overlay->overlay == NULL) { + pr_err("%s: failed to unflatten tree\n", __func__); + err = -EINVAL; + goto out_err; + } + pr_debug("%s: unflattened OK\n", __func__); + + /* mark it as detached */ + of_node_set_flag(overlay->overlay, OF_DETACHED); + + /* perform resolution */ + err = of_resolve_phandles(overlay->overlay); + if (err != 0) { + pr_err("%s: Failed to resolve tree\n", __func__); + goto out_err; + } + pr_debug("%s: resolved OK\n", __func__); + + err = of_overlay_create(overlay->overlay); + if (err < 0) { + pr_err("%s: Failed to create overlay (err=%d)\n", + __func__, err); + goto out_err; + } + overlay->ov_id = err; + return 0; + +out_err: + return err; +} + +static inline struct cfs_overlay_item *to_cfs_overlay_item( + struct config_item *item) +{ + return item ? container_of(item, struct cfs_overlay_item, item) : NULL; +} + +static ssize_t cfs_overlay_item_path_show(struct config_item *item, + char *page) +{ + struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); + return sprintf(page, "%s\n", overlay->path); +} + +static ssize_t cfs_overlay_item_path_store(struct config_item *item, + const char *page, size_t count) +{ + struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); + const char *p = page; + char *s; + int err; + + /* if it's set do not allow changes */ + if (overlay->path[0] != '\0' || overlay->dtbo_size > 0) + return -EPERM; + + /* copy to path buffer (and make sure it's always zero terminated */ + count = snprintf(overlay->path, sizeof(overlay->path) - 1, "%s", p); + overlay->path[sizeof(overlay->path) - 1] = '\0'; + + /* strip trailing newlines */ + s = overlay->path + strlen(overlay->path); + while (s > overlay->path && *--s == '\n') + *s = '\0'; + + pr_debug("%s: path is '%s'\n", __func__, overlay->path); + + err = request_firmware(&overlay->fw, overlay->path, NULL); + if (err != 0) + goto out_err; + + err = create_overlay(overlay, (void *)overlay->fw->data); + if (err != 0) + goto out_err; + + return count; + +out_err: + + release_firmware(overlay->fw); + overlay->fw = NULL; + + overlay->path[0] = '\0'; + return err; +} + +static ssize_t cfs_overlay_item_status_show(struct config_item *item, + char *page) +{ + struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); + + return sprintf(page, "%s\n", + overlay->ov_id >= 0 ? "applied" : "unapplied"); +} + +CONFIGFS_ATTR(cfs_overlay_item_, path); +CONFIGFS_ATTR_RO(cfs_overlay_item_, status); + +static struct configfs_attribute *cfs_overlay_attrs[] = { + &cfs_overlay_item_attr_path, + &cfs_overlay_item_attr_status, + NULL, +}; + +ssize_t cfs_overlay_item_dtbo_read(struct config_item *item, + void *buf, size_t max_count) +{ + struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); + + pr_debug("%s: buf=%p max_count=%zu\n", __func__, + buf, max_count); + + if (overlay->dtbo == NULL) + return 0; + + /* copy if buffer provided */ + if (buf != NULL) { + /* the buffer must be large enough */ + if (overlay->dtbo_size > max_count) + return -ENOSPC; + + memcpy(buf, overlay->dtbo, overlay->dtbo_size); + } + + return overlay->dtbo_size; +} + +ssize_t cfs_overlay_item_dtbo_write(struct config_item *item, + const void *buf, size_t count) +{ + struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); + int err; + + /* if it's set do not allow changes */ + if (overlay->path[0] != '\0' || overlay->dtbo_size > 0) + return -EPERM; + + /* copy the contents */ + overlay->dtbo = kmemdup(buf, count, GFP_KERNEL); + if (overlay->dtbo == NULL) + return -ENOMEM; + + overlay->dtbo_size = count; + + err = create_overlay(overlay, overlay->dtbo); + if (err != 0) + goto out_err; + + return count; + +out_err: + kfree(overlay->dtbo); + overlay->dtbo = NULL; + overlay->dtbo_size = 0; + + return err; +} + +CONFIGFS_BIN_ATTR(cfs_overlay_item_, dtbo, NULL, SZ_1M); + +static struct configfs_bin_attribute *cfs_overlay_bin_attrs[] = { + &cfs_overlay_item_attr_dtbo, + NULL, +}; + +static void cfs_overlay_release(struct config_item *item) +{ + struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); + + if (overlay->ov_id >= 0) + of_overlay_destroy(overlay->ov_id); + if (overlay->fw) + release_firmware(overlay->fw); + /* kfree with NULL is safe */ + kfree(overlay->dtbo); + kfree(overlay); +} + +static struct configfs_item_operations cfs_overlay_item_ops = { + .release = cfs_overlay_release, +}; + +static struct config_item_type cfs_overlay_type = { + .ct_item_ops = &cfs_overlay_item_ops, + .ct_attrs = cfs_overlay_attrs, + .ct_bin_attrs = cfs_overlay_bin_attrs, + .ct_owner = THIS_MODULE, +}; + +static struct config_item *cfs_overlay_group_make_item( + struct config_group *group, const char *name) +{ + struct cfs_overlay_item *overlay; + + overlay = kzalloc(sizeof(*overlay), GFP_KERNEL); + if (!overlay) + return ERR_PTR(-ENOMEM); + overlay->ov_id = -1; + + config_item_init_type_name(&overlay->item, name, &cfs_overlay_type); + return &overlay->item; +} + +static void cfs_overlay_group_drop_item(struct config_group *group, + struct config_item *item) +{ + struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); + + config_item_put(&overlay->item); +} + +static struct configfs_group_operations overlays_ops = { + .make_item = cfs_overlay_group_make_item, + .drop_item = cfs_overlay_group_drop_item, +}; + +static struct config_item_type overlays_type = { + .ct_group_ops = &overlays_ops, + .ct_owner = THIS_MODULE, +}; + +static struct configfs_group_operations of_cfs_ops = { + /* empty - we don't allow anything to be created */ +}; + +static struct config_item_type of_cfs_type = { + .ct_group_ops = &of_cfs_ops, + .ct_owner = THIS_MODULE, +}; + +struct config_group of_cfs_overlay_group; + +static struct configfs_subsystem of_cfs_subsys = { + .su_group = { + .cg_item = { + .ci_namebuf = "device-tree", + .ci_type = &of_cfs_type, + }, + }, + .su_mutex = __MUTEX_INITIALIZER(of_cfs_subsys.su_mutex), +}; + +static int __init of_cfs_init(void) +{ + int ret; + + pr_info("%s\n", __func__); + + config_group_init(&of_cfs_subsys.su_group); + config_group_init_type_name(&of_cfs_overlay_group, "overlays", + &overlays_type); + configfs_add_default_group(&of_cfs_overlay_group, + &of_cfs_subsys.su_group); + + ret = configfs_register_subsystem(&of_cfs_subsys); + if (ret != 0) { + pr_err("%s: failed to register subsys\n", __func__); + goto out; + } + pr_info("%s: OK\n", __func__); +out: + return ret; +} +late_initcall(of_cfs_init); --- /dev/null 2019-09-30 09:50:43.919599165 +0200 +++ linux-4.14.127-fbx/drivers/phy/marvell/phy-utmi-cp110.c 2019-02-15 14:29:40.846651713 +0100 @@ -0,0 +1,402 @@ +/* + * phy-utmi-cp110.c for cp110-utmi + * Created by on Mon Jul 24 18:09:45 2017 + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "phy-utmi-cp110.h" + +#define UTMI_PHY_COUNT 2 + +struct utmi_cp110_priv; + +struct utmi_cp110_phy { + struct phy *phy; + struct utmi_cp110_priv *priv; + u32 mux; + int index; +}; + +struct utmi_cp110_priv { + void __iomem *utmi_unit_regs; + struct regmap *regmap; + + struct device *dev; + struct utmi_cp110_phy phys[2]; +}; + +static const struct of_device_id mvebu_comphy_of_match[] = { + { .compatible = "marvell,cp110-utmi-phy", }, + { }, +}; +MODULE_DEVICE_TABLE(of, mvebu_comphy_of_match); + +static void __iomem *map_resource(struct platform_device *pdev, + const char *resource_name) +{ + struct resource *res; + void *ret; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, resource_name); + if (!res) { + dev_err(&pdev->dev, "unable to get resource %s\n", + resource_name); + return NULL; + } + + ret = devm_ioremap_resource(&pdev->dev, res); + if (!ret) { + dev_err(&pdev->dev, "unable to remap resource %pR: (%s)\n", + res, resource_name); + } + dev_dbg(&pdev->dev, "ioremaped resource %pR: (%s)\n", + res, resource_name); + return ret; +} + +/* + * relative to priv->regmap register space. + */ +#define UPHY_CFG_REG_OFF(n) (0x440 + (n) * 4) +#define USB_CONFIG_REG (0x420) + +/* + * read/write from/to utmi configuration registers. + */ +static u32 uphy_config_read(struct utmi_cp110_phy *uphy) +{ + u32 ret; + + regmap_read(uphy->priv->regmap, UPHY_CFG_REG_OFF(uphy->index), &ret); + return ret; +} + +static void uphy_config_write(u32 value, struct utmi_cp110_phy *uphy) +{ + regmap_write(uphy->priv->regmap, UPHY_CFG_REG_OFF(uphy->index), value); +} + +/* + * read/write from/to usb configuration register + */ +static u32 usb_config_read(struct utmi_cp110_priv *priv) +{ + u32 ret; + + regmap_read(priv->regmap, USB_CONFIG_REG, &ret); + return ret; +} + +static void usb_config_write(u32 value, struct utmi_cp110_priv *priv) +{ + regmap_write(priv->regmap, USB_CONFIG_REG, value); +} + +/* + * read/write from/to utmi PHY unit registers. + */ +static u32 uphy_unit_read(struct utmi_cp110_phy *uphy, u32 off) +{ + u32 ret = readl(uphy->priv->utmi_unit_regs + off + + 0x1000 * uphy->index); + + return ret; +} + +static void uphy_unit_write(u32 value, struct utmi_cp110_phy *uphy, u32 off) +{ + writel(value, uphy->priv->utmi_unit_regs + off + 0x1000 * uphy->index); +} + +static void utmi_power_down(struct utmi_cp110_phy *uphy) +{ + u32 reg; + + reg = uphy_config_read(uphy); + reg &= ~UTMI_PHY_CFG_PU_MASK; + uphy_config_write(reg, uphy); + + reg = usb_config_read(uphy->priv); + if (uphy->mux == UTMI_PHY_USB2_DEVICE) { + /* + * if in USB device mode, configure mux while the phy + * is powered down. + */ + reg |= UTMI_USB_CFG_DEVICE_EN_MASK; + reg &= ~UTMI_USB_CFG_DEVICE_MUX_MASK; + reg |= (uphy->index << UTMI_USB_CFG_DEVICE_MUX_OFFSET); + } else { + /* + * otherwise disable USB3 device mode. + */ + reg &= ~UTMI_USB_CFG_DEVICE_EN_MASK; + } + usb_config_write(reg, uphy->priv); + + /* + * set suspend mode and test_sel + */ + reg = uphy_unit_read(uphy, UTMI_CTRL_STATUS0_REG); + reg |= UTMI_CTRL_STATUS0_SUSPENDM_MASK; + reg |= UTMI_CTRL_STATUS0_TEST_SEL_MASK; + uphy_unit_write(reg, uphy, UTMI_CTRL_STATUS0_REG); + + mdelay(2); +} + +static void utmi_pll_power_off(struct utmi_cp110_phy *uphy) +{ + u32 reg; + + /* + * FIXME: this is a global bit for both UTMI phys, is it safe + * to power it down when the other phy is powered on ? + */ + reg = usb_config_read(uphy->priv); + reg &= ~UTMI_USB_CFG_PLL_MASK; + usb_config_write(reg, uphy->priv); +} + +static void utmi_pll_power_on(struct utmi_cp110_phy *uphy) +{ + u32 reg; + + /* + * FIXME: see above. + */ + reg = usb_config_read(uphy->priv); + reg |= UTMI_USB_CFG_PLL_MASK; + usb_config_write(reg, uphy->priv); +} + +static void utmi_phy_configure(struct utmi_cp110_phy *uphy) +{ + u32 reg; + + reg = uphy_unit_read(uphy, UTMI_PLL_CTRL_REG); + /* Reference Clock Divider Select */ + reg &= ~UTMI_PLL_CTRL_REFDIV_MASK; + reg |= 0x5 << UTMI_PLL_CTRL_REFDIV_OFFSET; + /* Feedback Clock Divider Select - 90 for 25Mhz*/ + reg &= ~UTMI_PLL_CTRL_FBDIV_MASK; + reg |= 0x60 << UTMI_PLL_CTRL_FBDIV_OFFSET; + /* Select LPFR - 0x0 for 25Mhz/5=5Mhz*/ + reg &= ~UTMI_PLL_CTRL_SEL_LPFR_MASK; + reg |= 0x0 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET; + uphy_unit_write(reg, uphy, UTMI_PLL_CTRL_REG); + + /* Impedance Calibration Threshold Setting */ + reg = uphy_unit_read(uphy, UTMI_CALIB_CTRL_REG); + reg &= ~UTMI_CALIB_CTRL_IMPCAL_VTH_MASK; + reg |= 0x6 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET; + uphy_unit_write(reg, uphy, UTMI_CALIB_CTRL_REG); + + reg = uphy_unit_read(uphy, UTMI_TX_CH_CTRL_REG); + /* Set LS TX driver strength coarse control */ + reg &= ~UTMI_TX_CH_CTRL_DRV_EN_LS_MASK; + reg |= 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET; + /* Set LS TX driver fine adjustment */ + reg &= ~UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK; + reg |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET; + uphy_unit_write(reg, uphy, UTMI_TX_CH_CTRL_REG); + + reg = uphy_unit_read(uphy, UTMI_RX_CH_CTRL0_REG); + /* Enable SQ */ + reg &= ~UTMI_RX_CH_CTRL0_SQ_DET_MASK; + reg |= 0x0 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET; + /* Enable analog squelch detect */ + reg &= ~UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK; + reg |= 0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET; + uphy_unit_write(reg, uphy, UTMI_RX_CH_CTRL0_REG); + + /* Set External squelch calibration number */ + reg = uphy_unit_read(uphy, UTMI_RX_CH_CTRL1_REG); + reg &= ~UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK; + reg |= 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET; + /* Enable the External squelch calibration */ + reg &= ~UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK; + reg |= 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET; + uphy_unit_write(reg, uphy, UTMI_RX_CH_CTRL1_REG); + + /* Set Control VDAT Reference Voltage - 0.325V */ + reg = uphy_unit_read(uphy, UTMI_CHGDTC_CTRL_REG); + reg &= ~UTMI_CHGDTC_CTRL_VDAT_MASK; + reg |= 0x1 << UTMI_CHGDTC_CTRL_VDAT_OFFSET; + /* Set Control VSRC Reference Voltage - 0.6V */ + reg &= ~UTMI_CHGDTC_CTRL_VSRC_MASK; + reg |= 0x1 << UTMI_CHGDTC_CTRL_VSRC_OFFSET; + uphy_unit_write(reg, uphy, UTMI_CHGDTC_CTRL_REG); +} + +static int utmi_power_up(struct utmi_cp110_phy *uphy) +{ + u32 reg; + u32 tries; + + /* + * set PU bit + */ + reg = uphy_config_read(uphy); + reg |= UTMI_PHY_CFG_PU_MASK; + uphy_config_write(reg, uphy); + + /* + * clear test_sel + */ + reg = uphy_unit_read(uphy, UTMI_CTRL_STATUS0_REG); + reg &= ~UTMI_CTRL_STATUS0_TEST_SEL_MASK; + uphy_unit_write(reg, uphy, UTMI_CTRL_STATUS0_REG); + + /* + * wait for impedance calibration + */ + tries = 100; + while (tries) { + u32 reg = uphy_unit_read(uphy, UTMI_CALIB_CTRL_REG); + + if ((reg & (UTMI_CALIB_CTRL_IMPCAL_DONE_MASK | + UTMI_CALIB_CTRL_PLLCAL_DONE_MASK)) == + (UTMI_CALIB_CTRL_IMPCAL_DONE_MASK | + UTMI_CALIB_CTRL_PLLCAL_DONE_MASK)) + break; + mdelay(2); + --tries; + } + if (!tries) + return -ETIMEDOUT; + + /* + * wait for PLL ready. + */ + tries = 100; + while (tries) { + u32 reg = uphy_unit_read(uphy, UTMI_PLL_CTRL_REG); + + if (reg & UTMI_PLL_CTRL_PLL_RDY_MASK) + break; + mdelay(2); + --tries; + } + if (!tries) + return -ETIMEDOUT; + + return 0; +} + +static int utmi_cp110_power_off(struct phy *phy) +{ + struct utmi_cp110_phy *uphy = phy_get_drvdata(phy); + + utmi_power_down(uphy); + return 0; +} + +static int utmi_cp110_power_on(struct phy *phy) +{ + struct utmi_cp110_phy *uphy = phy_get_drvdata(phy); + int err; + + utmi_power_down(uphy); + utmi_pll_power_off(uphy); + utmi_phy_configure(uphy); + err = utmi_power_up(uphy); + utmi_pll_power_on(uphy); + + return err; +} + +static int utmi_cp110_set_mode(struct phy *phy, enum phy_mode mode) +{ + struct utmi_cp110_phy *uphy = phy_get_drvdata(phy); + + pr_info("utmi_cp110_set_mode(): mode %d\n", mode); + if (mode >= (int)UTMI_PHY_MAX) + return -EINVAL; + uphy->mux = mode; + return 0; +} + +static const struct phy_ops utmi_cp110_phy_ops = { + .power_on = utmi_cp110_power_on, + .power_off = utmi_cp110_power_off, + .set_mode = utmi_cp110_set_mode, + .owner = THIS_MODULE, +}; + +static struct phy *utmi_cp110_phy_of_xlate(struct device *dev, + struct of_phandle_args *args) +{ + struct utmi_cp110_priv *priv = dev_get_drvdata(dev); + u32 index = args->args[0]; + struct utmi_cp110_phy *uphy; + + if (index >= UTMI_PHY_COUNT) + return NULL; + + uphy = &priv->phys[index]; + + return uphy->phy; +} + +static int utmi_cp110_probe(struct platform_device *pdev) +{ + struct utmi_cp110_priv *priv; + struct phy_provider *provider; + int i; + + priv = devm_kzalloc(&pdev->dev, sizeof (*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = &pdev->dev; + priv->regmap = + syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "marvell,system-controller"); + if (IS_ERR(priv->regmap)) + return PTR_ERR(priv->regmap); + + priv->utmi_unit_regs = map_resource(pdev, "utmi-unit"); + if (!priv->utmi_unit_regs) + return -ENOMEM; + + for (i = 0; i < UTMI_PHY_COUNT; ++i) { + dev_dbg(&pdev->dev, "creating phy %d\n", i); + priv->phys[i].phy = devm_phy_create(&pdev->dev, NULL, + &utmi_cp110_phy_ops); + if (IS_ERR(priv->phys[i].phy)) { + int err = PTR_ERR(priv->phys[i].phy); + dev_err(&pdev->dev, "devm_phy_create: failed with %d\n", err); + return err; + } + priv->phys[i].priv = priv; + priv->phys[i].index = i; + phy_set_drvdata(priv->phys[i].phy, &priv->phys[i]); + } + platform_set_drvdata(pdev, priv); + + provider = devm_of_phy_provider_register(&pdev->dev, + utmi_cp110_phy_of_xlate); + if (!provider) + dev_err(&pdev->dev, "failed to register OF phy provider.\n"); + return PTR_ERR_OR_ZERO(provider); +} + +static struct platform_driver utmi_cp110_driver = { + .probe = utmi_cp110_probe, + .driver = { + .name = "phy-utmi-cp110", + .owner = THIS_MODULE, + .of_match_table = mvebu_comphy_of_match, + }, +}; +module_platform_driver(utmi_cp110_driver); --- /dev/null 2019-09-30 09:50:43.919599165 +0200 +++ linux-4.14.127-fbx/drivers/phy/marvell/phy-utmi-cp110.h 2019-02-15 14:29:40.846651713 +0100 @@ -0,0 +1,81 @@ +/* + * *************************************************************************** + * Copyright (C) 2015 Marvell International Ltd. + * *************************************************************************** + * This program is free software: you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation, either version 2 of the License, or any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * *************************************************************************** + */ + +#ifndef __PHY_UTMI_CP110_H +# define __PHY_UTMI_CP110_H + +#define UTMI_USB_CFG_DEVICE_EN_OFFSET 0 +#define UTMI_USB_CFG_DEVICE_EN_MASK (0x1 << UTMI_USB_CFG_DEVICE_EN_OFFSET) +#define UTMI_USB_CFG_DEVICE_MUX_OFFSET 1 +#define UTMI_USB_CFG_DEVICE_MUX_MASK (0x1 << UTMI_USB_CFG_DEVICE_MUX_OFFSET) +#define UTMI_USB_CFG_PLL_OFFSET 25 +#define UTMI_USB_CFG_PLL_MASK (0x1 << UTMI_USB_CFG_PLL_OFFSET) + +#define UTMI_PHY_CFG_PU_OFFSET 5 +#define UTMI_PHY_CFG_PU_MASK (0x1 << UTMI_PHY_CFG_PU_OFFSET) + +#define UTMI_PLL_CTRL_REG 0x0 +#define UTMI_PLL_CTRL_REFDIV_OFFSET 0 +#define UTMI_PLL_CTRL_REFDIV_MASK (0x7f << UTMI_PLL_CTRL_REFDIV_OFFSET) +#define UTMI_PLL_CTRL_FBDIV_OFFSET 16 +#define UTMI_PLL_CTRL_FBDIV_MASK (0x1FF << UTMI_PLL_CTRL_FBDIV_OFFSET) +#define UTMI_PLL_CTRL_SEL_LPFR_OFFSET 28 +#define UTMI_PLL_CTRL_SEL_LPFR_MASK (0x3 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET) +#define UTMI_PLL_CTRL_PLL_RDY_OFFSET 31 +#define UTMI_PLL_CTRL_PLL_RDY_MASK (0x1 << UTMI_PLL_CTRL_PLL_RDY_OFFSET) + +#define UTMI_CALIB_CTRL_REG 0x8 +#define UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET 8 +#define UTMI_CALIB_CTRL_IMPCAL_VTH_MASK (0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET) +#define UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET 23 +#define UTMI_CALIB_CTRL_IMPCAL_DONE_MASK (0x1 << UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET) +#define UTMI_CALIB_CTRL_PLLCAL_DONE_OFFSET 31 +#define UTMI_CALIB_CTRL_PLLCAL_DONE_MASK (0x1 << UTMI_CALIB_CTRL_PLLCAL_DONE_OFFSET) + +#define UTMI_TX_CH_CTRL_REG 0xC +#define UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET 12 +#define UTMI_TX_CH_CTRL_DRV_EN_LS_MASK (0xf << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET) +#define UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET 16 +#define UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK (0xf << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET) + +#define UTMI_RX_CH_CTRL0_REG 0x14 +#define UTMI_RX_CH_CTRL0_SQ_DET_OFFSET 15 +#define UTMI_RX_CH_CTRL0_SQ_DET_MASK (0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET) +#define UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET 28 +#define UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK (0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET) + +#define UTMI_RX_CH_CTRL1_REG 0x18 +#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET 0 +#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK (0x3 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET) +#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET 3 +#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK (0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET) + +#define UTMI_CTRL_STATUS0_REG 0x24 +#define UTMI_CTRL_STATUS0_SUSPENDM_OFFSET 22 +#define UTMI_CTRL_STATUS0_SUSPENDM_MASK (0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET) +#define UTMI_CTRL_STATUS0_TEST_SEL_OFFSET 25 +#define UTMI_CTRL_STATUS0_TEST_SEL_MASK (0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET) + +#define UTMI_CHGDTC_CTRL_REG 0x38 +#define UTMI_CHGDTC_CTRL_VDAT_OFFSET 8 +#define UTMI_CHGDTC_CTRL_VDAT_MASK (0x3 << UTMI_CHGDTC_CTRL_VDAT_OFFSET) +#define UTMI_CHGDTC_CTRL_VSRC_OFFSET 10 +#define UTMI_CHGDTC_CTRL_VSRC_MASK (0x3 << UTMI_CHGDTC_CTRL_VSRC_OFFSET) + +#endif /* __PHY_UTMI_CP110_H */ + diff -Nruw linux-4.14.127-fbx/drivers/platform/fbxgw7r./Kconfig linux-4.14.127-fbx/drivers/platform/fbxgw7r/Kconfig --- linux-4.14.127-fbx/drivers/platform/fbxgw7r./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/drivers/platform/fbxgw7r/Kconfig 2019-02-15 14:29:40.934652063 +0100 @@ -0,0 +1,6 @@ +config FBXGW7R_PLATFORM + bool "Freebox Gateway V7 specific drivers" + +config FBXGW7R_SWITCH + bool "Freebox Gateway V7 in kernel switch init code." + depends on FBXGW7R_PLATFORM diff -Nruw linux-4.14.127-fbx/drivers/platform/fbxgw7r./Makefile linux-4.14.127-fbx/drivers/platform/fbxgw7r/Makefile --- linux-4.14.127-fbx/drivers/platform/fbxgw7r./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/drivers/platform/fbxgw7r/Makefile 2019-02-15 14:29:40.934652063 +0100 @@ -0,0 +1 @@ +obj-$(CONFIG_FBXGW7R_SWITCH) += fbxgw7r-switch.o diff -Nruw linux-4.14.127-fbx/drivers/platform/fbxgw7r./fbxgw7r-switch.c linux-4.14.127-fbx/drivers/platform/fbxgw7r/fbxgw7r-switch.c --- linux-4.14.127-fbx/drivers/platform/fbxgw7r./fbxgw7r-switch.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/drivers/platform/fbxgw7r/fbxgw7r-switch.c 2019-07-22 10:44:48.014827640 +0200 @@ -0,0 +1,520 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PFX "fbxgw7r-switch: " + +#define PORTREG_SWITCH_IDENTIFIER 0x3 +#define PRODUCT_NUM(x) (((x) >> 4) & 0xfff) + +#define PDATA_MEMBER_UNMODIFIED 0 +#define PDATA_MEMBER_UNTAGGED 1 +#define PDATA_MEMBER_TAGGED 2 +#define PDATA_NOT_MEMBER 3 + +#define NFS_VLAN_ID 41 + +#define SWPORT(X) ((X) + 0x10) +#define PHYPORT(X) ((X) + 0x10) +#define MARVELL_PHYPORT0 0x00 +#define MARVELL_SWPORT0 0x10 +#define MARVELL_SWPORT4 0x14 +#define MARVELL_SWPORT5 0x15 + +#define PORTREG_PCS 0x1 + +#define PCS_RGMII_RX_DELAY (1 << 15) +#define PCS_RGMII_TX_DELAY (1 << 14) +#define PCS_FORCELINK_UP (1 << 5) +#define PCS_FORCELINK (1 << 4) +#define PCS_FORCEDUPLEX_FULL (1 << 3) +#define PCS_FORCEDUPLEX (1 << 2) +#define PCS_FORCESPEED_10 0x0 +#define PCS_FORCESPEED_100 0x1 +#define PCS_FORCESPEED_1000 0x2 +#define PCS_FORCESPEED_AUTO 0x3 + +#define PORTREG_PCR 0x4 +#define PCR_PORTSTATE_DISABLED 0x0 +#define PCR_PORTSTATE_FORWARDING 0x3 + +#define PORTREG_VLANID 0x7 + +#define PORTREG_PCR2 0x8 +#define PCR2_MODE_SHIFT 10 +#define PCR2_MODE_SECURE 3 + +#define MARVELL_GLOBAL1 0x1b +#define MARVELL_GLOBAL2 0x1c + +#define GLOBREG_VTUFID 0x2 +#define GLOBREG_VTUSID 0x3 + +#define GLOBREG_GCR 0x4 +#define GCR_PPUEN (1 << 14) + +#define GLOBREG_VTUOP 0x5 +#define VTUOP_BUSY (1 << 15) +#define VTUOP_OP_LOAD (0x3 << 12) +#define VTUOP_OP_STU_LOAD (0x5 << 12) +#define VTUOP_OP_GETNEXT (0x4 << 12) + +#define GLOBREG_VTUVID 0x6 +#define VTUVID_VALID (1 << 12) + +#define GLOBREG_VTU_P03_DATA 0x7 +#define GLOBREG_VTU_P46_DATA 0x8 + +#define GLOBREG_VTU_DATA 0x9 + +#define GLOBREG_SMI_CMD 0x18 +# define SMI_CMD_BUSY (1 << 15) +# define SMI_CLAUSE_22 (1 << 12) +# define SMI_CMD_READ (2 << 10) +# define SMI_CMD_WRITE (1 << 10) +# define SMI_CMD_C45_SETADDR (0 << 10) +# define SMI_CMD_C45_WRITE (1 << 10) +# define SMI_CMD_C45_READ (3 << 10) +# define SMI_DEVADDR(DevAddr) (DevAddr << 5) +# define SMI_REGADDR(RegAddr) (RegAddr) +#define GLOBREG_SMI_DATA 0x19 + +#define GLOBAL1_GSR 0x0 +# define GSR_PPU_POLLING_BIT (15) +# define GSR_INITREADY_BIT (11) + +/* + * + */ +struct sw_priv { + int dev_id; + struct mdio_device *mdiodev; +}; + +static int __sw_read(struct sw_priv *priv, int addr, u32 regnum) +{ + return mdiobus_read(priv->mdiodev->bus, addr, regnum); +} + +static int __sw_write(struct sw_priv *priv, int addr, u32 regnum, u16 val) +{ + return mdiobus_write(priv->mdiodev->bus, addr, regnum, val); +} + +static int __sw_indirect_wait(struct sw_priv *priv, int tries) +{ + while (tries) { + u16 val = __sw_read(priv, MARVELL_GLOBAL2, GLOBREG_SMI_CMD); + if ((val & SMI_CMD_BUSY) == 0) + return 0; + udelay(1000); + --tries; + } + return -ETIMEDOUT; +} + +/* + * Ye Olde Clause 22 read / write helpers. Use this on copper phy + * ports 1-4. + */ +static int sw_c22_read(struct sw_priv *priv, int phy_id, int reg) +{ + u16 smi_cmd = SMI_CMD_BUSY | SMI_CLAUSE_22 | SMI_CMD_READ | + SMI_DEVADDR(phy_id) | SMI_REGADDR(reg); + + __sw_write(priv, MARVELL_GLOBAL2, GLOBREG_SMI_CMD, smi_cmd); + if (__sw_indirect_wait(priv, 1000) < 0) { + printk(KERN_WARNING PFX "indirect phy read did not " + "complete.\n"); + return 0xffff; + } + return __sw_read(priv, MARVELL_GLOBAL2, GLOBREG_SMI_DATA); +} + +static void sw_c22_write(struct sw_priv *priv, int phy_id, int reg, + int val) +{ + u16 smi_cmd = SMI_CMD_BUSY | SMI_CLAUSE_22 | SMI_CMD_WRITE | + SMI_DEVADDR(phy_id) | SMI_REGADDR(reg); + + __sw_write(priv, MARVELL_GLOBAL2, GLOBREG_SMI_DATA, val); + __sw_write(priv, MARVELL_GLOBAL2, GLOBREG_SMI_CMD, smi_cmd); + if (__sw_indirect_wait(priv, 1000) < 0) { + printk(KERN_WARNING PFX "indirect phy write did not " + "complete.\n"); + } +} + +#define PORT_CMODE_MASK (0xf) + +static void change_p5_cmode(struct sw_priv *priv, u8 new_cmode) +{ + u16 psr = __sw_read(priv, 0x15, 0); + + if ((psr & PORT_CMODE_MASK) == new_cmode) { + printk("change_p5_cmode: mode is already %02x\n", new_cmode); + return ; + } + + /* Make CMODE writeable */ + __sw_write(priv, 0x15, 0x1a, 0x8100); + __sw_write(priv, 0x14, 0x1a, 0xdea0); + + /* write new CMODE*/ + __sw_write(priv, 0x15, 0x0, new_cmode); + + psr = __sw_read(priv, 0x15, 0); + if ((psr & PORT_CMODE_MASK) != new_cmode) + printk("change_p5_cmode: unable to change mode to %02x\n", + new_cmode); +} + +/* + * Ye Newe Clause 45 register accesses. an address cycle must be sent + * before sending a read or a write command. register address space is + * now 16bit wide. + * + * Valid on port 5 phy, when in SerDes mode. + */ +static u16 sw_c45_read(struct sw_priv *priv, u8 phy_addr, u8 devtype, + u16 reg) +{ + u16 smi_command = SMI_DEVADDR(phy_addr) | SMI_REGADDR(devtype) | + SMI_CMD_BUSY | SMI_CMD_C45_SETADDR; + + __sw_write(priv, MARVELL_GLOBAL2, 0x19, reg); + __sw_write(priv, MARVELL_GLOBAL2, 0x18, smi_command); + __sw_indirect_wait(priv, 1000); + + smi_command = SMI_DEVADDR(phy_addr) | SMI_REGADDR(devtype) | + SMI_CMD_BUSY | SMI_CMD_C45_READ; + __sw_write(priv, MARVELL_GLOBAL2, 0x18, smi_command); + __sw_indirect_wait(priv, 1000); + return __sw_read(priv, MARVELL_GLOBAL2, 0x19); +} + +static void sw_c45_write(struct sw_priv *priv, u8 phy_addr, u8 devtype, + u16 reg, u16 data) +{ + u16 smi_command = SMI_DEVADDR(phy_addr) | SMI_REGADDR(devtype) | + SMI_CMD_BUSY | SMI_CMD_C45_SETADDR; + + __sw_write(priv, MARVELL_GLOBAL2, 0x19, reg); + __sw_write(priv, MARVELL_GLOBAL2, 0x18, smi_command); + __sw_indirect_wait(priv, 1000); + + smi_command = SMI_DEVADDR(phy_addr) | SMI_REGADDR(devtype) | + SMI_CMD_BUSY | SMI_CMD_C45_WRITE; + __sw_write(priv, MARVELL_GLOBAL2, 0x19, data); + __sw_write(priv, MARVELL_GLOBAL2, 0x18, smi_command); + __sw_indirect_wait(priv, 1000); +} + + +static void __vtu_wait(struct sw_priv *priv) +{ + for (;;) { + u16 val = __sw_read(priv, MARVELL_GLOBAL1, GLOBREG_VTUOP); + if ((val & (1 << 15)) == 0) + break; + msleep(10); + } +} + +static void fbxgw7r_sw_vtu_stu_init(struct sw_priv *priv, int port_state, + size_t nr_ports) +{ + u16 vtu_op = VTUOP_OP_STU_LOAD; + u16 regs[2] = { 0 , 0 }; + int i; + + __sw_write(priv, MARVELL_GLOBAL1, GLOBREG_VTUOP, vtu_op); + + __sw_write(priv, MARVELL_GLOBAL1, GLOBREG_VTUSID, 0); + __sw_write(priv, MARVELL_GLOBAL1, GLOBREG_VTUVID, VTUVID_VALID); + + + for (i = 0; i < nr_ports; ++i) { + int off; + int shift; + + off = i / 4; + shift = 4 * (i % 4) + 2; + + regs[off] |= port_state << shift; + } + + __sw_write(priv, MARVELL_GLOBAL1, GLOBREG_VTU_P03_DATA, regs[0]); + __sw_write(priv, MARVELL_GLOBAL1, GLOBREG_VTU_P46_DATA, regs[1]); + + vtu_op |= VTUOP_BUSY; + __sw_write(priv, MARVELL_GLOBAL1, GLOBREG_VTUOP, vtu_op); + __vtu_wait(priv); +} + +static void fbxgw7r_sw_vtu_load(struct sw_priv *priv, u16 vid, const u8 *ports, + size_t nr_ports) +{ + u16 vtu_op; + u16 regs[2] = { 0, 0 }; + int i; + + vtu_op = VTUOP_OP_LOAD; + __sw_write(priv, MARVELL_GLOBAL1, GLOBREG_VTUOP, vtu_op); + + __sw_write(priv, MARVELL_GLOBAL1, GLOBREG_VTUFID, 1); + __sw_write(priv, MARVELL_GLOBAL1, GLOBREG_VTUSID, 0); + + __sw_write(priv, MARVELL_GLOBAL1, GLOBREG_VTUVID, + vid | VTUVID_VALID); + + for (i = 0; i < nr_ports; ++i) { + int off; + int shift; + + off = (i / 4); + shift = (i % 4) * 4; + + regs[off] |= ports[i] << shift; + } + + __sw_write(priv, MARVELL_GLOBAL1, GLOBREG_VTU_P03_DATA, regs[0]); + __sw_write(priv, MARVELL_GLOBAL1, GLOBREG_VTU_P46_DATA, regs[1]); + + vtu_op |= VTUOP_BUSY; + __sw_write(priv, MARVELL_GLOBAL1, GLOBREG_VTUOP, vtu_op); + + __vtu_wait(priv); +} + +static void fbxgw7r_sw_config_phy_port(struct sw_priv *priv, int phy_port) +{ + u16 val; + + /* power up phy for eth port 0 */ + val = sw_c22_read(priv, phy_port, 0x00); + val &= ~0x0800; + sw_c22_write(priv, phy_port, 0x00, val); + + + /* restart autoneg */ + val = sw_c22_read(priv, phy_port, 0x00); + val |= 0x0200; + sw_c22_write(priv, phy_port, 0x00, val); + + sw_c22_write(priv, phy_port, 20, 0); +} + +/* + * Serdes PHY must be accessed using clause 45 access. phy address is + * 0x15 (same as it would be for normal clause 22 addresses). function + * must be 0x4. + * + * standard phy registers are at offset 0x2000, in function 4. + * + * similar to the clause 22 copper phys, the only required stuff is to + * clear the power down bit and restart the autoneg. + */ +#define C45_BMCR 0x2000 +#define C45_ADVERTISE 0x2004 + +static void fbxgw7r_sw_config_serdes_port(struct sw_priv *priv, int phy_port) +{ + u16 reg; + + /* 1000BASE-X + autoneg */ + change_p5_cmode(priv, 0x9); + + reg = sw_c45_read(priv, phy_port, 0x4, C45_ADVERTISE); + reg |= ADVERTISE_1000XFULL | ADVERTISE_1000XHALF; + sw_c45_write(priv, phy_port, 0x4, C45_ADVERTISE, reg); + reg = sw_c45_read(priv, phy_port, 0x4, C45_ADVERTISE); + + reg = sw_c45_read(priv, phy_port, 0x4, C45_BMCR); + reg &= ~BMCR_PDOWN; + sw_c45_write(priv, phy_port, 0x4, C45_BMCR, reg); + + reg |= BMCR_ANRESTART | BMCR_ANENABLE; + sw_c45_write(priv, phy_port, 0x4, C45_BMCR, reg); +} + +static void fbxgw7r_sw_port_default_vid(struct sw_priv *priv, + int swport, u16 vid) +{ + u16 val; + + val = __sw_read(priv, swport, PORTREG_VLANID); + val &= ~0xfff; + val |= vid; + __sw_write(priv, swport, PORTREG_VLANID, val); +} + +static void fbxgw7r_sw_port_dot1q_secure(struct sw_priv *priv, int swport) +{ + u16 val; + + val = __sw_read(priv, swport, PORTREG_PCR2); + val &= ~(3 << PCR2_MODE_SHIFT); + val |= (PCR2_MODE_SECURE << PCR2_MODE_SHIFT); + __sw_write(priv, swport, PORTREG_PCR2, val); +} + +static void fbxgw7r_sw_port_forward_enable(struct sw_priv *priv, int swport) +{ + u16 val; + + /* enable forwarding */ + val = __sw_read(priv, swport, PORTREG_PCR); + val |= PCR_PORTSTATE_FORWARDING; + __sw_write(priv, swport, PORTREG_PCR, val); +} + + +static int sw_wait_on_gsr_bit(struct sw_priv *priv, int bit) +{ + u16 mask = (1 << bit); + u16 reg; + int tries = 100; + + do { + reg = __sw_read(priv, MARVELL_GLOBAL1, GLOBAL1_GSR); + if ((reg & mask)) + break; + msleep(10); + } while (--tries); + + if (!tries) + return -ETIMEDOUT; + + return 0; +} + +static int wait_sw_ready(struct sw_priv *priv) +{ + int error; + + error = sw_wait_on_gsr_bit(priv, GSR_INITREADY_BIT); + if (error) { + pr_err("timed out waiting for switch ready bit.\n"); + return error; + } + error = sw_wait_on_gsr_bit(priv, GSR_PPU_POLLING_BIT); + if (error) { + pr_err("timed out waiting for switch ready bit.\n"); + return error; + } + return error; +} + +static int mv6141_config(struct sw_priv *priv) +{ + struct device *dev = &priv->mdiodev->dev; + int error; + u16 val; + const u8 config[7] = { + PDATA_NOT_MEMBER, + PDATA_MEMBER_UNTAGGED, + PDATA_NOT_MEMBER, + PDATA_NOT_MEMBER, + PDATA_NOT_MEMBER, + PDATA_MEMBER_TAGGED, + PDATA_NOT_MEMBER, + }; + + /* probe */ + val = __sw_read(priv, SWPORT(0), PORTREG_SWITCH_IDENTIFIER); + if (PRODUCT_NUM(val) != 0x340) { + printk(KERN_ERR PFX "unknown switch id: 0x%03x\n", + PRODUCT_NUM(val)); + return -ENXIO; + } + + error = wait_sw_ready(priv); + if (error) + return error; + + priv->dev_id = 0x6141; + + fbxgw7r_sw_config_phy_port(priv, PHYPORT(1)); + fbxgw7r_sw_config_serdes_port(priv, PHYPORT(5)); + + + fbxgw7r_sw_vtu_stu_init(priv, PCR_PORTSTATE_FORWARDING, + sizeof (config)); + fbxgw7r_sw_vtu_load(priv, NFS_VLAN_ID, config, sizeof (config)); + + fbxgw7r_sw_port_default_vid(priv, SWPORT(1), NFS_VLAN_ID); + fbxgw7r_sw_port_default_vid(priv, SWPORT(5), NFS_VLAN_ID); + fbxgw7r_sw_port_dot1q_secure(priv, SWPORT(1)); + fbxgw7r_sw_port_dot1q_secure(priv, SWPORT(5)); + + fbxgw7r_sw_port_forward_enable(priv, SWPORT(5)); + fbxgw7r_sw_port_forward_enable(priv, SWPORT(1)); + + dev_info(dev, "marvell 6141 initialized\n"); + return 0; +} + +static int fbxgw7r_mv61xx_probe(struct mdio_device *mdiodev) +{ + struct device *dev = &mdiodev->dev; + struct sw_priv *priv; + int reset_gpio; + unsigned int flags; + u32 id; + + reset_gpio = of_get_named_gpio_flags(dev->of_node, + "gpio-reset", 0, &flags); + if (reset_gpio < 0) + return reset_gpio; + + priv = devm_kzalloc(dev, sizeof (*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->mdiodev = mdiodev; + dev_info(dev, "resetting switch\n"); + + gpio_direction_output(reset_gpio, 0); + msleep(1); + gpiod_set_value_cansleep(gpio_to_desc(reset_gpio), 1); + msleep(500); + + id = (unsigned long)of_device_get_match_data(dev); + switch (id) { + case 0x6141: + return mv6141_config(priv); + + default: + dev_err(dev, "unsupported model\n"); + return -ENODEV; + } + + mdiodev->flags = MDIO_DEVICE_FLAG_PHY; + return 0; +} + +static const struct of_device_id fbxgw7r_mv61xx_of_match[] = { + { + .compatible = "freebox,fbxgw7r-mv6141", + .data = (void *)0x6141, + }, + { /* sentinel */ }, +}; + +static struct mdio_driver fbxgw7r_mv61xx_driver = { + .probe = fbxgw7r_mv61xx_probe, + .mdiodrv.driver = { + .name = "fbxgw7r-mv61xx", + .of_match_table = of_match_ptr(fbxgw7r_mv61xx_of_match), + }, +}; + +mdio_module_driver(fbxgw7r_mv61xx_driver); diff -Nruw linux-4.14.127-fbx/drivers/platform/intelce./Kconfig linux-4.14.127-fbx/drivers/platform/intelce/Kconfig --- linux-4.14.127-fbx/drivers/platform/intelce./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/drivers/platform/intelce/Kconfig 2019-02-15 14:29:40.934652063 +0100 @@ -0,0 +1,18 @@ +# +# IntelCE devices configuration +# + +menu "IntelCE devices" + +config INTELCE_GPIO + tristate "GPIO support" + select ARCH_REQUIRE_GPIOLIB + ---help--- + IntelCE 3100/4100 GPIO support. + +config INTELCE_DFX + tristate "DFX reporting support" + ---help--- + IntelCE 3100/4100 DFX fuse reporting support. + +endmenu diff -Nruw linux-4.14.127-fbx/drivers/platform/intelce./Makefile linux-4.14.127-fbx/drivers/platform/intelce/Makefile --- linux-4.14.127-fbx/drivers/platform/intelce./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/drivers/platform/intelce/Makefile 2019-02-15 14:29:40.934652063 +0100 @@ -0,0 +1,2 @@ +obj-$(CONFIG_INTELCE_GPIO) += gpio-intelce.o +obj-$(CONFIG_INTELCE_DFX) += dfx.o diff -Nruw linux-4.14.127-fbx/drivers/soc/bcm/bcm63xx./Makefile linux-4.14.127-fbx/drivers/soc/bcm/bcm63xx/Makefile --- linux-4.14.127-fbx/drivers/soc/bcm/bcm63xx./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/drivers/soc/bcm/bcm63xx/Makefile 2019-02-15 14:29:41.530654424 +0100 @@ -0,0 +1,2 @@ +obj-y += pmc.o +obj-y += rdp/ diff -Nruw linux-4.14.127-fbx/drivers/soc/bcm/bcm63xx./rdp/Makefile linux-4.14.127-fbx/drivers/soc/bcm/bcm63xx/rdp/Makefile --- linux-4.14.127-fbx/drivers/soc/bcm/bcm63xx./rdp/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/drivers/soc/bcm/bcm63xx/rdp/Makefile 2019-02-15 14:29:41.530654424 +0100 @@ -0,0 +1,9 @@ +obj-y += rdp_drv.o + +rdp_drv-y += \ + rdp.o \ + rdp_api.o \ + rdp_io.o \ + rdp_ioctl.o + +rdp_drv-$(CONFIG_DEBUG_FS) += rdp_debug.o --- /dev/null 2019-09-30 09:50:43.919599165 +0200 +++ linux-4.14.127-fbx/drivers/video/fbdev/ssd1327.c 2019-02-15 14:29:42.630658784 +0100 @@ -0,0 +1,771 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * commands + */ +#define OPCODE_CONTRAST 0x81 + +#define OPCODE_SET_COLUMN 0x15 +#define OPCODE_SET_ROW 0x75 +#define OPCODE_SET_REMAP 0xa0 +#define OPCODE_DISPLAY_NORMAL 0xa4 +#define OPCODE_DISPLAY_ALL_ON 0xa5 +#define OPCODE_DISPLAY_ALL_OFF 0xa6 + +#define OPCODE_DISPLAY_OFF 0xae +#define OPCODE_DISPLAY_ON 0xaf + +#define OPCODE_DEF_GRAY 0xb9 + +#define SSD1327_MAX_BRIGHTNESS 0x81 +#define SSD1327_NOMINAL_BRIGHTNESS 0x64 + +/* + * fbinfo + */ +static struct fb_fix_screeninfo ssd1327_fb_fix = { + .id = "ssd1327", + .type = FB_TYPE_PACKED_PIXELS, + .visual = FB_VISUAL_STATIC_PSEUDOCOLOR, + .xpanstep = 0, + .ypanstep = 1, + .ywrapstep = 0, + .accel = FB_ACCEL_NONE, +}; + +static struct fb_var_screeninfo ssd1327_fb_var = { + .bits_per_pixel = 8, + .grayscale = 1, + .nonstd = 1, + .red.length = 8, + .green.length = 8, + .blue.length = 8, +}; + +/* + * private data + */ +#define SSD1327_COLS 64 +#define SSD1327_ROWS 128 +#define GDDRAM_SIZE SSD1327_COLS * SSD1327_ROWS + +struct ssd1327 { + struct mutex mutex; + + /* configuration from device tree */ + u32 width; + u32 height; + u32 rotate; + u32 watchdog; + + /* image of display ram */ + u8 gddram[GDDRAM_SIZE]; + u8 old_gddram[GDDRAM_SIZE]; + + /* data ram, 8 bits per pixel */ + u8 *vmem; + unsigned int vmem_size; + + + struct fb_info *fb; + struct gpio_desc *vcc_gpio; + struct reset_control *reset; + struct gpio_desc *data_gpio; + struct spi_device *spi; + + struct backlight_device *backlight; + unsigned int brightness; + + /* watchog timer */ + struct delayed_work wtd_work; + atomic_t wtd_count; +}; + +/* + * send command to device + */ +static int send_cmd(struct ssd1327 *priv, u8 cmd) +{ + int ret; + + mutex_lock(&priv->mutex); + gpiod_set_value(priv->data_gpio, 0); + ret = spi_write_then_read(priv->spi, &cmd, 1, NULL, 0); + mutex_unlock(&priv->mutex); + return ret; +} + +/* + * send command list to device + */ +static int send_cmds(struct ssd1327 *priv, const u8 *cmd, unsigned int len) +{ + unsigned int i; + int ret; + + for (i = 0; i < len; i++) { + ret = send_cmd(priv, cmd[i]); + if (ret < 0) + return ret; + } + return 0; +} + +/* + * write given data into device gddram + */ +static int write_data(struct ssd1327 *priv, u8 *tx, unsigned int size) +{ + int ret; + + mutex_lock(&priv->mutex); + gpiod_set_value(priv->data_gpio, 1); + ret = spi_write(priv->spi, tx, size); + mutex_unlock(&priv->mutex); + return ret; +} + +/* + * soft reset & initialize ssd1327 + */ +static int ssd1327_init(struct ssd1327 *priv) +{ + const u8 init_cmds[] = { OPCODE_DISPLAY_ON, + + /* set even/odd splitting */ + OPCODE_SET_REMAP, (1 << 6), + OPCODE_CONTRAST, SSD1327_NOMINAL_BRIGHTNESS, + OPCODE_DEF_GRAY, + OPCODE_DISPLAY_NORMAL, + }; + int ret; + + /* check if we need to powerup */ + if (priv->reset && reset_control_status(priv->reset)) { + dev_info(&priv->spi->dev, "reset held, powerup needed"); + gpiod_direction_output(priv->vcc_gpio, 0); + reset_control_deassert(priv->reset); + msleep(10); + gpiod_direction_output(priv->vcc_gpio, 1); + msleep(100); + } + + /* zero ram */ + ret = write_data(priv, priv->gddram, GDDRAM_SIZE); + if (ret) + return ret; + + return send_cmds(priv, init_cmds, sizeof (init_cmds)); +} + +/* + * update area + */ +static int ssd1327_fb_update(struct ssd1327 *priv) +{ + unsigned int col, row, w, h, i, count; + unsigned char *vmem; + u8 *start; + u8 ccmds[3] = { OPCODE_SET_COLUMN, 0, 0x3f }; + u8 rcmds[3] = { OPCODE_SET_ROW, 0, 0x7f }; + int toggle, last_toggle_pos, moved; + + w = priv->width; + h = priv->height; + + /* backup previous gddram */ + memcpy(priv->old_gddram, priv->gddram, GDDRAM_SIZE); + + vmem = priv->vmem + w * priv->fb->var.yoffset; + + for (row = 0; row < SSD1327_ROWS; row++) { + + if (row >= h) + break; + + for (col = 0; col < SSD1327_COLS; col++) { + unsigned int nibble; + u8 val; + + val = 0; + for (nibble = 0; nibble < 2; nibble++) { + unsigned int off, x; + u8 vval; + + x = col * 2 + nibble; + if (x >= w) + break; + + switch (priv->fb->var.rotate) { + case 0: + default: + off = row * w + x; + break; + + case 180: + off = w * h - (row * w + x) - 1; + break; + + case 90: + off = (w - x - 1) * w + row; + break; + + case 270: + off = x * w + (h - row - 1); + break; + } + + vval = vmem[off] >> 4; + val |= vval << (nibble * 4); + } + + priv->gddram[row * SSD1327_COLS + col] = val; + } + } + + /* count consecutive toggled bytes, each column/row address + * change adds 6 bytes to send */ + moved = toggle = 0; + last_toggle_pos = -INT_MAX; + count = 0; + for (i = 0; i < GDDRAM_SIZE; i++) { + if (priv->gddram[i] ^ priv->old_gddram[i]) { + /* if crossing column boundary and first + * address is not 0, we must send column + * command */ + if (moved && ((i % SSD1327_COLS) == 0)) { + count += 3; + moved = 0; + } + + if (!toggle) { + if (i - last_toggle_pos < 6) { + unsigned int j; + + /* fake last columns as dirty, + * cheaper than repositionning + * cursor */ + for (j = last_toggle_pos; j < i; j++) + priv->old_gddram[j] = + ~priv->gddram[j]; + + count += i - last_toggle_pos - 1; + } else { + /* send command to change + * address & column */ + count += 6; + + /* if we changed first column address + * to non 0, remember it */ + if ((i % SSD1327_COLS)) + moved = 1; + else + moved = 0; + } + } + + toggle = 1; + count++; + + } else { + if (toggle) + last_toggle_pos = i - 1; + toggle = 0; + } + } + + /* force full gddram update if we would send more bytes + * using clever update */ + if (count > GDDRAM_SIZE) + return write_data(priv, priv->gddram, GDDRAM_SIZE); + + moved = toggle = 0; + count = 0; + start = NULL; + for (i = 0; i < GDDRAM_SIZE; i++) { + + if (priv->gddram[i] ^ priv->old_gddram[i]) { + /* if crossed column boundary and first + * address is not 0, we must send command to + * reset column*/ + if (moved && ((i % SSD1327_COLS) == 0)) { + write_data(priv, start, count); + start += count; + count = 0; + ccmds[1] = 0; + send_cmds(priv, ccmds, 3); + moved = 0; + } + + if (!toggle) { + ccmds[1] = i % SSD1327_COLS; + rcmds[1] = i / SSD1327_COLS; + send_cmds(priv, ccmds, 3); + send_cmds(priv, rcmds, 3); + + /* if we changed first column address + * to non 0, remember it */ + if ((i % SSD1327_COLS)) + moved = 1; + else + moved = 0; + start = &priv->gddram[i]; + } + + count++; + toggle = 1; + + } else { + if (count) { + write_data(priv, start, count); + count = 0; + } + toggle = 0; + } + } + + if (count) + write_data(priv, start, count); + + /* reset position */ + ccmds[1] = 0; + send_cmds(priv, ccmds, 3); + rcmds[1] = 0; + send_cmds(priv, rcmds, 3); + return 0; +} + +/* + * frame buffer fill rect callback + */ +static void ssd1327_fb_fillrect(struct fb_info *info, + const struct fb_fillrect *rect) +{ + struct ssd1327 *priv = info->par; + sys_fillrect(info, rect); + atomic_set(&priv->wtd_count, priv->watchdog); + ssd1327_fb_update(priv); +} + +/* + * frame buffer copy area callback + */ +static void ssd1327_fb_copyarea(struct fb_info *info, + const struct fb_copyarea *area) +{ + struct ssd1327 *priv = info->par; + sys_copyarea(info, area); + atomic_set(&priv->wtd_count, priv->watchdog); + ssd1327_fb_update(priv); +} + +/* + * frame buffer image blit + */ +static void ssd1327_fb_imageblit(struct fb_info *info, + const struct fb_image *image) +{ + struct ssd1327 *priv = info->par; + sys_imageblit(info, image); + atomic_set(&priv->wtd_count, priv->watchdog); + ssd1327_fb_update(priv); +} + +/* + * frame buffer pan callback + */ +static int ssd1327_fb_pan(struct fb_var_screeninfo *var, struct fb_info *info) +{ + struct ssd1327 *priv = info->par; + priv->fb->var.xoffset = var->xoffset; + priv->fb->var.yoffset = var->yoffset; + atomic_set(&priv->wtd_count, priv->watchdog); + ssd1327_fb_update(priv); + return 0; +} + +/* + * fram buffer set_par callback, set videomode + */ +static int ssd1327_fb_set_par(struct fb_info *info) +{ + struct ssd1327 *priv = info->par; + /* called after rotate update */ + atomic_set(&priv->wtd_count, priv->watchdog); + ssd1327_fb_update(priv); + return 0; +} + +static int ssd1327_fb_check_var(struct fb_var_screeninfo *var, + struct fb_info *info) +{ + unsigned int rotate; + + rotate = var->rotate; + if (rotate != 0 && rotate != 90 && rotate != 180 && rotate != 270) + rotate = 0; + *var = info->var; + var->rotate = rotate; + return 0; +} + +/* + * frame buffer blank callback + */ +static int ssd1327_fb_blank(int blank, struct fb_info *info) +{ + return 0; +} + +/* + * frame buffer write from userspace + */ +static ssize_t ssd1327_fb_write(struct fb_info *info, const char __user *buf, + size_t count, loff_t *ppos) +{ + struct ssd1327 *priv = info->par; + unsigned long p = *ppos; + void *dst; + int err = 0; + unsigned long total_size; + + if (info->state != FBINFO_STATE_RUNNING) + return -EPERM; + + total_size = info->fix.smem_len; + + if (p > total_size) + return -EFBIG; + + if (count > total_size) { + err = -EFBIG; + count = total_size; + } + + if (count + p > total_size) { + if (!err) + err = -ENOSPC; + + count = total_size - p; + } + + dst = (void __force *)(info->screen_base + p); + + if (copy_from_user(dst, buf, count)) + err = -EFAULT; + + if (!err) + *ppos += count; + + atomic_set(&priv->wtd_count, priv->watchdog); + ssd1327_fb_update(priv); + + return (err) ? err : count; +} + +static struct fb_ops ssd1327_fb_ops = { + .owner = THIS_MODULE, + .fb_write = ssd1327_fb_write, + .fb_fillrect = ssd1327_fb_fillrect, + .fb_copyarea = ssd1327_fb_copyarea, + .fb_imageblit = ssd1327_fb_imageblit, + .fb_pan_display = ssd1327_fb_pan, + .fb_blank = ssd1327_fb_blank, + .fb_check_var = ssd1327_fb_check_var, + .fb_set_par = ssd1327_fb_set_par, +}; + +/* + * watchdog timer + */ +static void wtd_work_cb(struct work_struct *t) +{ + struct ssd1327 *priv; + struct delayed_work *dwork; + + dwork = container_of(t, struct delayed_work, work); + priv = container_of(dwork, struct ssd1327, wtd_work); + + if (atomic_dec_and_test(&priv->wtd_count)) { + dev_err(&priv->spi->dev, "watchdog triggered\n"); + memset(priv->vmem, 0, priv->vmem_size); + ssd1327_fb_update(priv); + } + + schedule_delayed_work(&priv->wtd_work, HZ); +} + +/* + * backlight control + */ +static int ssd1327_bl_update_status(struct backlight_device *bl) +{ + struct ssd1327 *priv; + u8 bl_cmds[2]; + int ret; + + priv = bl_get_data(bl); + + bl_cmds[0] = OPCODE_CONTRAST; + bl_cmds[1] = bl->props.brightness; + + ret = send_cmds(priv, bl_cmds, sizeof (bl_cmds)); + if (ret < 0) + return ret; + priv->brightness = bl->props.brightness; + return 0; +} + +static int ssd1327_bl_get_brightness(struct backlight_device *bl) +{ + struct ssd1327 *priv; + priv = bl_get_data(bl); + return priv->brightness; +} + +static struct backlight_ops ssd1327_bl_ops = { + .update_status = ssd1327_bl_update_status, + .get_brightness = ssd1327_bl_get_brightness, +}; + +static const struct backlight_properties ssd1327_bl_props = { + .power = FB_BLANK_UNBLANK, + .fb_blank = FB_BLANK_UNBLANK, + .max_brightness = SSD1327_MAX_BRIGHTNESS, + .type = BACKLIGHT_RAW, +}; + +static int init_backlight(struct ssd1327 *priv) +{ + struct backlight_device *bl; + + bl = backlight_device_register("ssd1327", &priv->spi->dev, + priv, &ssd1327_bl_ops, + &ssd1327_bl_props); + if (IS_ERR(bl)) { + dev_err(&priv->spi->dev, "error %ld on backlight register\n", + PTR_ERR(bl)); + return PTR_ERR(bl); + } + priv->backlight = bl; + bl->props.brightness = priv->brightness; + return 0; +} + +/* + * platform device probe callback + */ +static int ssd1327_probe(struct spi_device *spi) +{ + struct device_node *node = spi->dev.of_node; + struct ssd1327 *priv; + struct fb_info *fb; + int ret; + + if (!node) { + dev_err(&spi->dev, "No device tree data found!\n"); + return -EINVAL; + } + + fb = framebuffer_alloc(sizeof (*priv), &spi->dev); + if (!fb) + return -ENOMEM; + + priv = fb->par; + mutex_init(&priv->mutex); + priv->spi = spi; + priv->fb = fb; + priv->brightness = SSD1327_NOMINAL_BRIGHTNESS; + + priv->reset = devm_reset_control_get_shared_by_index(&spi->dev, 0); + if (IS_ERR(priv->reset)) { + ret = PTR_ERR(priv->reset); + if (ret == -ENOENT) + priv->reset = NULL; + else { + if (ret != -EPROBE_DEFER) + dev_err(&spi->dev, "failed to get reset: %d\n", + ret); + goto fail; + } + } + + priv->vcc_gpio = NULL; + if (priv->reset) { + priv->vcc_gpio = devm_gpiod_get(&spi->dev, "ssd1327,vcc", + GPIOD_ASIS); + if (IS_ERR(priv->vcc_gpio)) { + ret = PTR_ERR(priv->vcc_gpio); + if (ret != -EPROBE_DEFER) + dev_err(&spi->dev, + "failed to get vcc gpio: %d\n", ret); + goto fail; + } + } + + priv->data_gpio = devm_gpiod_get(&spi->dev, + "ssd1327,data-select", + GPIOD_OUT_LOW); + if (IS_ERR(priv->data_gpio)) { + ret = PTR_ERR(priv->data_gpio); + if (ret != -EPROBE_DEFER) + dev_err(&spi->dev, "failed to get data gpio: %d\n", + ret); + goto fail; + } + + ret = of_property_read_u32(node, "ssd1327,width", &priv->width); + if (ret) { + dev_err(&spi->dev, "failed to get width\n"); + goto fail; + } + + ret = of_property_read_u32(node, "ssd1327,height", &priv->height); + if (ret) { + dev_err(&spi->dev, "failed to get height\n"); + goto fail; + } + + /* sanity check on screen size */ + if (priv->width > SSD1327_COLS * 2 || + priv->height > SSD1327_ROWS) { + dev_err(&spi->dev, "unsupported screen dimension\n"); + goto fail; + } + + ret = of_property_read_u32(node, "ssd1327,rotate", &priv->rotate); + if (ret) { + dev_err(&spi->dev, "failed to get rotate\n"); + goto fail; + } + + ret = of_property_read_u32(node, "ssd1327,watchdog", &priv->watchdog); + if (ret) { + dev_err(&spi->dev, "failed to get watchdog\n"); + goto fail; + } + + /* setup framebuffer */ + fb->fbops = &ssd1327_fb_ops; + fb->flags = FBINFO_FLAG_DEFAULT | FBINFO_HWACCEL_YPAN; + fb->var = ssd1327_fb_var; + fb->fix = ssd1327_fb_fix; + + fb->var.xres = priv->width; + fb->var.yres = priv->height; + fb->var.xres_virtual = priv->width; + fb->var.yres_virtual = priv->height * 2; + + /* twice lcd size so we can pan in one direction */ + fb->fix.smem_len = (priv->width * priv->height) * 2; + fb->fix.line_length = priv->width; + fb->var.rotate = priv->rotate; + + /* allocate video memory */ + priv->vmem_size = PAGE_ALIGN(fb->fix.smem_len); + priv->vmem = vmalloc(priv->vmem_size); + if (!priv->vmem) { + ret = -ENOMEM; + goto fail; + } + memset(priv->vmem, 0, priv->vmem_size); + fb->screen_base = (char __iomem *)priv->vmem; + + ret = ssd1327_init(priv); + if (ret) + goto fail; + + if (init_backlight(priv)) + goto fail; + + /* register frame buffer */ + ret = register_framebuffer(fb); + if (ret < 0) + goto fail; + + INIT_DELAYED_WORK(&priv->wtd_work, wtd_work_cb); + + if (priv->watchdog) { + atomic_set(&priv->wtd_count, priv->watchdog); + schedule_delayed_work(&priv->wtd_work, HZ); + } + + dev_info(&spi->dev, + "fb%d: SSD1327 frame buffer device (%ux%u screen)\n", + fb->node, priv->width, priv->height); + + dev_set_drvdata(&spi->dev, priv); + return 0; + +fail: + if (priv->vmem) + vfree(priv->vmem); + if (priv->backlight) + backlight_device_unregister(priv->backlight); + framebuffer_release(fb); + return ret; +} + +/* + * platform device remove callback + */ +static int ssd1327_remove(struct spi_device *spi) +{ + struct ssd1327 *priv; + unsigned int i; + + priv = dev_get_drvdata(&spi->dev); + cancel_delayed_work_sync(&priv->wtd_work); + unregister_framebuffer(priv->fb); + for (i = 0; i < priv->vmem_size; i += PAGE_SIZE) { + struct page *page; + page = vmalloc_to_page(priv->vmem + i); + page->mapping = NULL; + } + vfree(priv->vmem); + backlight_device_unregister(priv->backlight); + framebuffer_release(priv->fb); + return 0; +} + + +static const struct of_device_id ssd1327_of_match[] = { + { + .compatible = "solomon,ssd1327", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, ssd1327_of_match); + +static struct spi_driver ssd1327_driver = { + .driver = { + .name = "ssd1327", + .of_match_table = ssd1327_of_match, + }, + .probe = ssd1327_probe, + .remove = ssd1327_remove, +}; + +module_spi_driver(ssd1327_driver); + +MODULE_DESCRIPTION("SSD1327 driver"); +MODULE_AUTHOR("Maxime Bizon "); +MODULE_LICENSE("GPL"); diff -Nruw linux-4.14.127-fbx/fs/exfat./Kconfig linux-4.14.127-fbx/fs/exfat/Kconfig --- linux-4.14.127-fbx/fs/exfat./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/fs/exfat/Kconfig 2019-01-14 15:09:09.119950445 +0100 @@ -0,0 +1,3 @@ + +config EXFAT_FS + tristate "exFAT fs support" diff -Nruw linux-4.14.127-fbx/fs/exfat./Makefile linux-4.14.127-fbx/fs/exfat/Makefile --- linux-4.14.127-fbx/fs/exfat./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/fs/exfat/Makefile 2019-01-14 15:09:09.119950445 +0100 @@ -0,0 +1,13 @@ + +obj-$(CONFIG_EXFAT_FS) += exfat.o + +exfat-y = super.o \ + inode.o \ + fat.o \ + read-write.o \ + upcase.o \ + bitmap.o \ + time.o \ + dir.o \ + namei.o \ + file.o diff -Nruw linux-4.14.127-fbx/fs/exfat./bitmap.c linux-4.14.127-fbx/fs/exfat/bitmap.c --- linux-4.14.127-fbx/fs/exfat./bitmap.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/fs/exfat/bitmap.c 2019-01-14 15:16:37.082082405 +0100 @@ -0,0 +1,606 @@ +/* + * bitmap.c for exfat + * Created by on Thu Aug 8 19:21:05 2013 + */ + +#include +#include + +#include "exfat.h" +#include "exfat_fs.h" + + +static inline sector_t exfat_bitmap_sector(struct exfat_sb_info *sbi, + u32 cluster) +{ + return sbi->first_bitmap_sector + ((cluster / 8) >> sbi->sectorbits); +} + +static inline u32 exfat_bitmap_off(struct exfat_sb_info *sbi, + u32 cluster) +{ + return (cluster / 8) & sbi->sectormask; +} + +static inline u32 exfat_bitmap_shift(u32 cluster) +{ + return cluster & 7; +} + +static int __find_get_free_cluster(struct inode *inode, u32 *out_cluster) +{ + struct exfat_sb_info *sbi = EXFAT_SB(inode->i_sb); + + while (1) { + sector_t sect = exfat_bitmap_sector(sbi, + sbi->cur_bitmap_cluster); + u32 off = exfat_bitmap_off(sbi, sbi->cur_bitmap_cluster); + u32 shift = exfat_bitmap_shift(sbi->cur_bitmap_cluster); + + /* disk is full */ + if (!sbi->free_clusters) + break; + + if (!sbi->cur_bitmap_bh || + sect != sbi->cur_bitmap_sector) { + if (sbi->cur_bitmap_bh) + brelse(sbi->cur_bitmap_bh); + sbi->cur_bitmap_bh = sb_bread(inode->i_sb, sect); + sbi->cur_bitmap_sector = sect; + if (!sbi->cur_bitmap_bh) { + exfat_msg(inode->i_sb, KERN_ERR, + "unable to read bitmap sector " + "at %llu", (unsigned long long)sect); + return -EIO; + } + } + + if (!(sbi->cur_bitmap_bh->b_data[off] & (1 << shift))) { + sbi->cur_bitmap_bh->b_data[off] |= (1 << shift); + *out_cluster = sbi->cur_bitmap_cluster; + goto found; + } + + ++sbi->cur_bitmap_cluster; + if (sbi->cur_bitmap_cluster == sbi->cluster_count) + sbi->cur_bitmap_cluster = 0; + } + return -ENOSPC; + +found: + sbi->prev_free_cluster = *out_cluster; + --sbi->free_clusters; + mark_buffer_dirty(sbi->cur_bitmap_bh); + return 0; +} + +static int __put_cluster(struct inode *inode, u32 cluster) +{ + struct exfat_sb_info *sbi = EXFAT_SB(inode->i_sb); + sector_t sect = exfat_bitmap_sector(sbi, cluster); + u32 off = exfat_bitmap_off(sbi, cluster); + u32 shift = exfat_bitmap_shift(cluster); + + + if (!sbi->cur_bitmap_bh || sect != sbi->cur_bitmap_sector) { + if (sbi->cur_bitmap_bh) + brelse(sbi->cur_bitmap_bh); + sbi->cur_bitmap_bh = sb_bread(inode->i_sb, sect); + if (!sbi->cur_bitmap_bh) { + exfat_msg(inode->i_sb, KERN_ERR, + "unable to read bitmap sector at %llu", + (unsigned long long)sect); + return -EIO; + } + sbi->cur_bitmap_sector = sect; + sbi->cur_bitmap_cluster = cluster; + } + if ((sbi->cur_bitmap_bh->b_data[off] & (1 << shift)) == 0) { + exfat_fs_error(inode->i_sb, "put_cluster: cluster %u " + "already free.", cluster); + return -EIO; + } + + ++sbi->free_clusters; + sbi->cur_bitmap_bh->b_data[off] &= ~(1 << shift); + sbi->prev_free_cluster = cluster; + mark_buffer_dirty(sbi->cur_bitmap_bh); + /* sync_dirty_buffer(sbi->cur_bitmap_bh); */ + return 0; +} + +/* + * setup search to start at given cluster. + */ +static void __exfat_reset_bitmap(struct exfat_sb_info *sbi, u32 cluster) +{ + sector_t sect; + + if (cluster >= sbi->cluster_count) + cluster = 0; + + sect = exfat_bitmap_sector(sbi, cluster); + if (sbi->cur_bitmap_sector != sect) { + sbi->cur_bitmap_sector = sect; + if (sbi->cur_bitmap_bh) { + brelse(sbi->cur_bitmap_bh); + sbi->cur_bitmap_bh = NULL; + } + } + sbi->cur_bitmap_cluster = cluster; +} + +static bool all_contiguous(u32 *clusters, u32 nr) +{ + u32 i; + + for (i = 0; i < nr - 1; ++i) { + if (clusters[i] != clusters[i + 1] - 1) + return false; + } + return true; +} + +/* + * hint must be the immediately after the last allocated cluster of + * the inode. + */ +int exfat_alloc_clusters(struct inode *inode, u32 hint, u32 *clusters, u32 nr) +{ + struct exfat_sb_info *sbi = EXFAT_SB(inode->i_sb); + struct exfat_inode_info *info = EXFAT_I(inode); + u32 i; + + mutex_lock(&sbi->bitmap_mutex); + __exfat_reset_bitmap(sbi, hint - 2); + for (i = 0; i < nr; ++i) { + u32 new; + int error; + + error = __find_get_free_cluster(inode, &new); + if (error) { + mutex_unlock(&sbi->bitmap_mutex); + return error; + } + + clusters[i] = new + 2; + } + mutex_unlock(&sbi->bitmap_mutex); + + /* + * all clusters found: now see if we need to update/create a + * fat chain. + */ + if (info->first_cluster == 0) { + info->first_cluster = clusters[0]; + if (all_contiguous(clusters, nr)) { + /* + * first cluster alloc on inode and all + * clusters are contiguous. + */ + info->flags |= EXFAT_I_FAT_INVALID; + } else { + /* + * first alloc and already fragmented. + */ + return exfat_write_fat(inode, 0, clusters, nr); + } + } else { + int error; + if ((info->flags & EXFAT_I_FAT_INVALID) && + (clusters[0] != hint || !all_contiguous(clusters, nr))) { + /* + * must now use fat chain instead of bitmap. + */ + info->flags &= ~(EXFAT_I_FAT_INVALID); + + /* + * write the contiguous chain that would + * previously be accessed without the FAT + * chain. + */ + error = exfat_write_fat_contiguous(inode, + info->first_cluster, + hint - info->first_cluster); + if (error) + return error; + } + + if ((info->flags & EXFAT_I_FAT_INVALID) == 0) { + /* + * link the allocated clusters after hint. + */ + error = exfat_write_fat(inode, hint - 1, clusters, nr); + if (error) + return error; + } + + } + + /* + * update i_blocks. + */ + inode->i_blocks += nr << (sbi->clusterbits - 9); + info->allocated_clusters += nr; + + /* + * caller must call mark_inode_dirty so that inode + * first_cluster and inode flags get written to the disk. + * caller must update inode size (directory and regular file + * have different rules). + */ + return 0; +} + + +static int exfat_free_clusters_contiguous(struct inode *inode, + u32 start, u32 nr) +{ + u32 cluster; + struct exfat_sb_info *sbi = EXFAT_SB(inode->i_sb); + int error = 0; + + mutex_lock(&sbi->bitmap_mutex); + for (cluster = start; cluster < start + nr; ++cluster) { + error = __put_cluster(inode, cluster - 2); + if (error) + break; + } + mutex_unlock(&sbi->bitmap_mutex); + return error; +} + +static int exfat_free_clusters_fat(struct inode *inode, + u32 fcluster_start, u32 nr) +{ + struct exfat_sb_info *sbi = EXFAT_SB(inode->i_sb); + u32 fcluster; + int error = 0; + + mutex_lock(&sbi->bitmap_mutex); + for (fcluster = fcluster_start; fcluster < fcluster_start + nr; + ++fcluster) { + u32 dcluster; + int error; + + error = exfat_get_fat_cluster(inode, fcluster, &dcluster); + if (error) + break; + + error = __put_cluster(inode, dcluster - 2); + if (error) + break; + } + mutex_unlock(&sbi->bitmap_mutex); + + /* + * per-inode file cluster to disk cluster translation cache + * mostly now holds entries to the zone we just truncated, so + * they must not be kept (this could lead to FS corruption). + */ + exfat_inode_cache_drop(inode); + + return error; +} + +int exfat_free_clusters_inode(struct inode *inode, u32 fcluster_start) +{ + struct exfat_inode_info *info = EXFAT_I(inode); + int error; + u32 nr_to_free = info->allocated_clusters - fcluster_start; + + if (info->first_cluster == 0 || nr_to_free == 0) + /* + * no clusters allocated, or nothing to do + */ + return 0; + + if (info->flags & EXFAT_I_FAT_INVALID) + error = exfat_free_clusters_contiguous(inode, + info->first_cluster + fcluster_start, + nr_to_free); + else + error = exfat_free_clusters_fat(inode, fcluster_start, + nr_to_free); + if (error) + return error; + + info->allocated_clusters -= nr_to_free; + inode->i_blocks = EXFAT_I(inode)->allocated_clusters << + (EXFAT_SB(inode->i_sb)->clusterbits - 9); + + /* + * update inode info, caller must call mark_inode_dirty and + * update inode->i_size. + */ + if (fcluster_start == 0) { + info->first_cluster = 0; + info->flags &= ~(EXFAT_I_FAT_INVALID); + } + return 0; +} + +static u32 count_clusters_bh(struct buffer_head *bh, u32 count) +{ + u8 *ptr = bh->b_data; + u32 ret = 0; + u8 val; + + while (count >= sizeof (u64) * 8) { + u64 val = *(u64*)ptr; + + ret += hweight64(~val); + count -= sizeof (u64) * 8; + ptr += sizeof (u64); + } + if (count >= sizeof (u32) * 8) { + u32 val = *(u32*)ptr; + + ret += hweight32(~val); + count -= sizeof (u32) * 8; + ptr += sizeof (u32); + } + if (count >= sizeof (u16) * 8) { + u16 val = *(u16*)ptr; + + ret += hweight16(~val); + count -= sizeof (u16) * 8; + ptr += sizeof (u16); + } + if (count >= sizeof (u8) * 8) { + u8 val = *ptr; + + ret += hweight8(~val); + count -= sizeof (u8) * 8; + ptr += sizeof (u8); + } + + if (count) { + val = *ptr; + while (count) { + ret += (~val & 1); + val >>= 1; + --count; + } + } + return ret; +} + +/* + * only called during mount, so taking sbi->bitmap_mutex should not be + * needed. + */ +static int exfat_get_free_cluster_count(struct super_block *sb, u32 *out_count) +{ + struct exfat_sb_info *sbi = EXFAT_SB(sb); + u32 clusters_per_sector = 8 * sbi->sectorsize; + u32 cluster; + + *out_count = 0; + for (cluster = 0; cluster < sbi->cluster_count; + cluster += clusters_per_sector) { + sector_t sect = exfat_bitmap_sector(sbi, cluster); + struct buffer_head *bh; + u32 count = clusters_per_sector; + + if (cluster + clusters_per_sector > sbi->cluster_count) + count = sbi->cluster_count - cluster; + + bh = sb_bread(sb, sect); + if (!bh) { + exfat_msg(sb, KERN_ERR, + "unable to read bitmap sector at %llu", + (unsigned long long)sect); + return -EIO; + } + *out_count += count_clusters_bh(bh, count); + brelse(bh); + } + return 0; +} + +/* + * setup a bitmap context, preload a bh from the requested starting + * cluster. + */ +int exfat_init_bitmap_context(struct super_block *sb, + struct exfat_bitmap_ctx *ctx, + u32 cluster) +{ + memset(ctx, 0, sizeof (*ctx)); + ctx->sb = sb; + + cluster -= 2; + if (cluster >= EXFAT_SB(sb)->cluster_count) + return -ENOSPC; + + ctx->cur_sector = exfat_bitmap_sector(EXFAT_SB(sb), cluster); + ctx->bh = sb_bread(ctx->sb, ctx->cur_sector); + + if (!ctx->bh) { + exfat_msg(sb, KERN_ERR, "unable to read bitmap sector at %llu", + (unsigned long long)ctx->cur_sector); + return -EIO; + } + return 0; +} + +/* + * release bh in an already setup bitmap context. + */ +void exfat_exit_bitmap_context(struct exfat_bitmap_ctx *ctx) +{ + if (ctx->bh) + brelse(ctx->bh); +} + +/* + * test a specific cluster usage in the bitmap. reuse the bh in the + * exfat_bitmap_ctx or read a new one if starting cluster is outside + * the current one. + */ +static int exfat_test_bitmap_cluster(struct exfat_bitmap_ctx *ctx, + uint32_t cluster, bool *cluster_in_use) +{ + sector_t sect; + uint32_t off = exfat_bitmap_off(EXFAT_SB(ctx->sb), cluster); + int shift = exfat_bitmap_shift(cluster); + + sect = exfat_bitmap_sector(EXFAT_SB(ctx->sb), cluster); + if (sect != ctx->cur_sector) { + ctx->cur_sector = sect; + ctx->bh = sb_bread(ctx->sb, ctx->cur_sector); + if (!ctx->bh) { + exfat_msg(ctx->sb, KERN_ERR, + "unable to read bitmap sector at %llu", + (unsigned long long)sect); + return -EIO; + } + } + + *cluster_in_use = !!(ctx->bh->b_data[off] & (1 << shift)); + return 0; +} + +/* + * update first_in_use and nr_in_use with the first zone of used + * clusters starting from start_cluster. + */ +int exfat_test_bitmap(struct exfat_bitmap_ctx *ctx, uint32_t start_cluster, + uint32_t *first_in_use, uint32_t *nr_in_use) +{ + bool in_use = false; + int error = 0; + struct exfat_sb_info *sbi = EXFAT_SB(ctx->sb); + + start_cluster -= 2; + + /* + * scan bitmap until we find a cluster that is in use. + */ + while (1) { + if (start_cluster == sbi->cluster_count) { + /* + * readched end of disk: no more in use + * cluster found. + */ + *first_in_use = sbi->cluster_count; + *nr_in_use = 0; + return 0; + } + error = exfat_test_bitmap_cluster(ctx, start_cluster, &in_use); + if (error) + return error; + if (in_use) + break; + ++start_cluster; + } + + + /* + * update first_in_use, and scan until a free cluster is + * found. + */ + *first_in_use = start_cluster + 2; + *nr_in_use = 0; + while (1) { + error = exfat_test_bitmap_cluster(ctx, start_cluster, &in_use); + if (error) + return error; + if (!in_use) + break; + ++(*nr_in_use); + ++start_cluster; + } + return 0; +} + +int exfat_init_bitmap(struct inode *root) +{ + struct exfat_sb_info *sbi = EXFAT_SB(root->i_sb); + struct exfat_bitmap_entry *be; + struct exfat_dir_ctx dctx; + u32 first_bitmap_cluster; + u32 last_bitmap_cluster; + + int error; + + mutex_init(&sbi->bitmap_mutex); + + error = exfat_init_dir_ctx(root, &dctx, 0); + if (error) + return error; + +try_bitmap: + error = -ENOENT; + be = __exfat_dentry_next(&dctx, E_EXFAT_BITMAP, 0xff, true, NULL); + if (!be) { + exfat_msg(root->i_sb, KERN_ERR, "root directory does not " + "have a bitmap entry."); + goto fail; + } + + if (exfat_bitmap_nr(be->flags) != 0) + /* + * not expected to find a second bitmap entry here + * since we checked during superblock fill that we + * were not on a texFAT volume ... + */ + goto try_bitmap; + + + error = -EINVAL; + if (__le64_to_cpu(be->length) * 8 < sbi->cluster_count) { + exfat_msg(root->i_sb, KERN_INFO, "bitmap does not cover " + "the whole cluster heap."); + goto fail; + } + + first_bitmap_cluster = __le32_to_cpu(be->cluster_addr); + last_bitmap_cluster = first_bitmap_cluster + + (__le32_to_cpu(be->length) >> sbi->clusterbits); + + /* + * check that bitmap start and end clusters are inside the + * disk. + */ + error = -ERANGE; + if (first_bitmap_cluster < 2 && + first_bitmap_cluster >= sbi->cluster_count) { + exfat_msg(root->i_sb, KERN_ERR, "bitmap start cluster is " + "outside disk limits."); + goto fail; + } + if (last_bitmap_cluster < 2 && + last_bitmap_cluster >= sbi->cluster_count) { + exfat_msg(root->i_sb, KERN_ERR, "bitmap last cluster is " + "outside disk limits."); + goto fail; + } + + sbi->bitmap_length = __le32_to_cpu(be->length); + sbi->first_bitmap_sector = exfat_cluster_sector(sbi, + __le32_to_cpu(be->cluster_addr)); + sbi->last_bitmap_sector = sbi->first_bitmap_sector + + DIV_ROUND_UP(sbi->bitmap_length, sbi->sectorsize); + + error = exfat_get_free_cluster_count(root->i_sb, &sbi->free_clusters); + if (error) + goto fail; + + sbi->prev_free_cluster = 0; + + exfat_cleanup_dir_ctx(&dctx); + return 0; +fail: + exfat_cleanup_dir_ctx(&dctx); + return error; +} + +void exfat_exit_bitmap(struct super_block *sb) +{ + struct exfat_sb_info *sbi = EXFAT_SB(sb); + + if (sbi->cur_bitmap_bh) + brelse(sbi->cur_bitmap_bh); +} diff -Nruw linux-4.14.127-fbx/fs/exfat./dir.c linux-4.14.127-fbx/fs/exfat/dir.c --- linux-4.14.127-fbx/fs/exfat./dir.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/fs/exfat/dir.c 2019-01-14 15:09:09.119950445 +0100 @@ -0,0 +1,400 @@ +/* + * dir.c for exfat + * Created by on Tue Aug 20 11:42:46 2013 + */ + +#include +#include +#include +#include +#include + +#include "exfat.h" +#include "exfat_fs.h" + +/* + * setup an exfat_dir_ctx structure so that __exfat_dentry_next can + * work with it. + */ +int exfat_init_dir_ctx(struct inode *inode, struct exfat_dir_ctx *ctx, + off_t start) +{ + u32 cluster = EXFAT_I(inode)->first_cluster; + + memset(ctx, 0, sizeof (*ctx)); + + if (cluster == 0) { + ctx->empty = true; + ctx->sb = inode->i_sb; + return 0; + } + + if (cluster < EXFAT_CLUSTER_FIRSTVALID || + cluster > EXFAT_CLUSTER_LASTVALID) { + exfat_msg(inode->i_sb, KERN_ERR, "exfat_init_dir_ctx: invalid " + "cluster %u", cluster); + return -EINVAL; + } + + start &= ~(0x20 - 1); + if (start == 0) + ctx->off = -1; + else + ctx->off = start - 0x20; + + ctx->sb = inode->i_sb; + ctx->inode = inode; + + return 0; +} + +void exfat_cleanup_dir_ctx(struct exfat_dir_ctx *dctx) +{ + if (dctx->bh) + brelse(dctx->bh); +} + +/* + * calculate the checksum for the current direntry. fields containing + * the checksum for the first entry is not part of the checksum + * calculation. + */ +u16 exfat_direntry_checksum(void *data, u16 checksum, bool first) +{ + u8 *ptr = data; + int i; + + for (i = 0; i < 0x20; ++i) { + if (first && (i == 2 || i == 3)) + continue ; + checksum = ((checksum << 15) | (checksum >> 1)) + (u16)ptr[i]; + } + return checksum; +} + +u32 exfat_dctx_fpos(struct exfat_dir_ctx *dctx) +{ + return dctx->off; +} + +u64 exfat_dctx_dpos(struct exfat_dir_ctx *dctx) +{ + struct exfat_sb_info *sbi = EXFAT_SB(dctx->sb); + + return (dctx->sector << sbi->sectorbits) + + (dctx->off & sbi->sectormask); +} + +static int exfat_get_dctx_disk_cluster(struct exfat_dir_ctx *dctx, + u32 file_cluster, u32 *disk_cluster) +{ + struct exfat_inode_info *info = EXFAT_I(dctx->inode); + + if (info->flags & EXFAT_I_FAT_INVALID) { + *disk_cluster = info->first_cluster + file_cluster; + return 0; + } else { + return exfat_get_fat_cluster(dctx->inode, file_cluster, + disk_cluster); + } +} + +/* + * get the next typed dentry in the exfat_dir_ctx structure. can_skip + * indicates whether the entry must be immediately there in the entry + * stream. *end indicates whether end of directory entry stream is + * reached or not. + * + * only one buffer_head is kept at a time. subsequent calls to + * __exfat_dentry_next can invalidate pointers from previous calls due + * to that. + */ +void *__exfat_dentry_next(struct exfat_dir_ctx *dctx, int type, int mask, + bool can_skip, bool *end) +{ + struct exfat_sb_info *sbi = EXFAT_SB(dctx->sb); + + if (dctx->empty) { + if (end) + *end = true; + return NULL; + } + + if (end) + *end = false; + + if (dctx->off == -1) + dctx->off = 0; + else + dctx->off += 0x20; + + for (;;) { + sector_t wanted_sector; + u32 file_cluster = dctx->off >> sbi->clusterbits; + u32 disk_cluster; + int error; + int sector_offset; + sector_t sector_in_cluster; + + if (dctx->off >= dctx->inode->i_size) { + *end = true; + return NULL; + } + + + error = exfat_get_dctx_disk_cluster(dctx, file_cluster, + &disk_cluster); + if (error) + return NULL; + + sector_in_cluster = (dctx->off >> sbi->sectorbits) % + sbi->sectors_per_cluster; + + wanted_sector = exfat_cluster_sector(sbi, disk_cluster) + + sector_in_cluster; + if (wanted_sector != dctx->sector || !dctx->bh) { + /* + * need to fetch a new sector from the current + * cluster. + */ + dctx->sector = wanted_sector; + if (dctx->bh) + brelse(dctx->bh); + dctx->bh = sb_bread(dctx->sb, dctx->sector); + if (!dctx->bh) + return NULL; + } + + sector_offset = dctx->off & sbi->sectormask; + if ((dctx->bh->b_data[sector_offset] & mask) == (type & mask)) + /* + * return pointer to entry if type matches the + * one given. + */ + return dctx->bh->b_data + sector_offset; + + if (dctx->bh->b_data[sector_offset] == 0 && end) + /* + * set end if no more entries in this directory. + */ + *end = true; + + if (dctx->bh->b_data[sector_offset] == 0 || !can_skip) + /* + * handle can_skip / end of directory. + */ + return NULL; + + /* + * move to next entry. + */ + dctx->off += 0x20; + } + return NULL; +} + +/* + * helper around __exfat_dentry_next that copies the content of the + * found entry in a user supplied buffer. + */ +int exfat_dentry_next(void *out, struct exfat_dir_ctx *dctx, + int type, bool can_skip) +{ + bool end; + + void *ptr = __exfat_dentry_next(dctx, type, 0xff, can_skip, &end); + + if (!ptr) { + if (end) + return -ENOENT; + else { + exfat_msg(dctx->sb, KERN_INFO, "no ptr and " + "end not reached: " + "type %02x, can_skip %s\n", type, + can_skip ? "true" : "false"); + return -EIO; + } + } + memcpy(out, ptr, 0x20); + return 0; +} + +/* + * extract name by parsing consecutive E_EXFAT_FILENAME entries in a + * caller provided buffer. also update the checksum on the fly. + * + * no utf16 to utf8 conversion is performed. + */ +int __exfat_get_name(struct exfat_dir_ctx *dctx, u32 name_length, + __le16 *name, u16 *calc_checksum, + struct exfat_iloc *iloc) +{ + __le16 *ptr; + int error; + int nr; + + ptr = name; + + error = -EIO; + nr = 0; + while (name_length) { + struct exfat_filename_entry *e; + u32 len = 15; + + e = __exfat_dentry_next(dctx, E_EXFAT_FILENAME, 0xff, + false, NULL); + if (!e) + goto fail; + *calc_checksum = exfat_direntry_checksum(e, *calc_checksum, + false); + + if (iloc) + iloc->disk_offs[nr + 2] = exfat_dctx_dpos(dctx); + if (name_length < 15) + len = name_length; + + memcpy(ptr, e->name_frag, len * sizeof (__le16)); + name_length -= len; + ptr += len; + nr++; + } + return 0; + +fail: + return error; +} + +/* + * walk the directory and invoke filldir on all found entries. + */ +static int __exfat_iterate(struct exfat_dir_ctx *dctx, struct file *file, + struct dir_context *ctx) +{ + int error; + char *name = __getname(); + __le16 *utf16name = __getname(); + + if (!name) + return -ENOMEM; + if (!utf16name) { + __putname(name); + return -ENOMEM; + } + + for (;;) { + struct exfat_filedir_entry *efd; + struct exfat_stream_extension_entry *esx; + int dtype = DT_REG; + int name_length; + bool end; + u16 calc_checksum; + u16 expect_checksum; + + /* + * get the next filedir entry, we are allowed to skip + * entries for that. + */ + error = -EIO; + efd = __exfat_dentry_next(dctx, E_EXFAT_FILEDIR, 0xff, + true, &end); + if (!efd) { + if (end) + break; + else + goto fail; + } + expect_checksum = __le16_to_cpu(efd->set_checksum); + calc_checksum = exfat_direntry_checksum(efd, 0, true); + + if (__le16_to_cpu(efd->attributes & E_EXFAT_ATTR_DIRECTORY)) + dtype = DT_DIR; + + /* + * get immediate stream extension entry. + */ + esx = __exfat_dentry_next(dctx, E_EXFAT_STREAM_EXT, 0xff, false, + NULL); + if (!esx) + goto fail; + calc_checksum = exfat_direntry_checksum(esx, calc_checksum, + false); + + /* + * get immediate name. + */ + error = __exfat_get_name(dctx, esx->name_length, utf16name, + &calc_checksum, NULL); + if (error) { + exfat_msg(dctx->sb, KERN_INFO, "__exfat_get_name " + "has failed with %i", error); + goto fail; + } + + if (calc_checksum != expect_checksum) { + exfat_msg(dctx->sb, KERN_INFO, "checksum: " + "calculated %04x, expect %04x", + calc_checksum, expect_checksum); + error = -EIO; + goto fail; + } + + /* + * convert utf16 to utf8 for kernel filldir callback. + */ + name_length = utf16s_to_utf8s(utf16name, esx->name_length, + UTF16_LITTLE_ENDIAN, + name, NAME_MAX + 2); + if (name_length < 0) { + error = name_length; + goto fail; + } + if (name_length > 255) { + error = -ENAMETOOLONG; + goto fail; + } + + /* + * tell the kernel we have an entry by calling + * dir_emit + */ + if (dir_emit(ctx, name, name_length, 1, dtype)) + ctx->pos = 2 + exfat_dctx_fpos(dctx); + else + goto fail; + } + __putname(name); + __putname(utf16name); + ctx->pos = file_inode(file)->i_size + 2; + return 0; +fail: + __putname(name); + __putname(utf16name); + return error; +} + +/* + * readdir callback for VFS. fill "." and "..", then invoke + * __exfat_iterate. + */ +int exfat_iterate(struct file *file, struct dir_context *ctx) +{ + struct exfat_dir_ctx dctx; + int error; + struct inode *inode = file_inode(file); + + switch (ctx->pos) { + case 0: + return dir_emit_dots(file, ctx); + default: + if (ctx->pos >= inode->i_size + 2) + return 0; + error = exfat_init_dir_ctx(inode, &dctx, ctx->pos - 2); + if (error) + return error; + exfat_lock_super(inode->i_sb); + error = __exfat_iterate(&dctx, file, ctx); + exfat_unlock_super(inode->i_sb); + exfat_cleanup_dir_ctx(&dctx); + return error; + } +} diff -Nruw linux-4.14.127-fbx/fs/exfat./exfat.h linux-4.14.127-fbx/fs/exfat/exfat.h --- linux-4.14.127-fbx/fs/exfat./exfat.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/fs/exfat/exfat.h 2019-02-15 14:29:43.726663128 +0100 @@ -0,0 +1,325 @@ +/* + * exfat.h for exfat + * Created by on Tue Jul 23 12:37:12 2013 + */ + +#ifndef __EXFAT_H +# define __EXFAT_H + +#define EXFAT_HASH_BITS (8) +#define EXFAT_HASH_SIZE (1 << EXFAT_HASH_BITS) + +/* + * special inode number for root directory. + */ +#define EXFAT_ROOT_INO 1 + +enum { + EXFAT_ERROR_ACTION_CONTINUE, + EXFAT_ERROR_ACTION_REMOUNT_RO, + EXFAT_ERROR_ACTION_PANIC, +}; + +struct exfat_sb_options { + kuid_t uid; + kgid_t gid; + mode_t dmask; + mode_t fmask; + int time_offset; + int time_offset_set; + int error_action; +}; + +struct exfat_sb_info { + struct exfat_sb_options options; + + struct buffer_head *sb_bh; + struct exfat_vbr *vbr; + bool dirty; + + u32 sectorsize; /* in bytes*/ + u32 clustersize; /* in bytes */ + u32 sectors_per_cluster; + int sectorbits; + int clusterbits; + u32 sectormask; + u32 clustermask; + + u32 fat_offset; + u32 fat_length; + + u32 root_dir_cluster; + u32 cluster_heap_offset; + u32 cluster_count; + + __le16 *upcase_table; + u32 upcase_len; + + /* + * bitmap fields + */ + struct mutex bitmap_mutex; + u32 bitmap_length; + sector_t first_bitmap_sector; + sector_t last_bitmap_sector; + sector_t cur_bitmap_sector; + u32 cur_bitmap_cluster; + struct buffer_head *cur_bitmap_bh; + u32 free_clusters; + u32 prev_free_cluster; + + /* + * inode hash fields + */ + spinlock_t inode_hash_lock; + struct hlist_head inode_hash[EXFAT_HASH_SIZE]; + + struct mutex sb_mutex; +}; + +struct exfat_cache_entry { + struct list_head list; + u32 file_cluster; + u32 disk_cluster; + u32 nr_contig; +}; + +struct exfat_cache { + struct mutex mutex; + struct list_head entries; + u32 nr_entries; +}; + +struct exfat_iloc { + u8 nr_secondary; + u32 file_off; + u64 disk_offs[19]; +}; + +struct exfat_inode_info { + u8 flags; + u16 attributes; + u32 first_cluster; + u32 allocated_clusters; + loff_t mmu_private; + struct exfat_iloc iloc; + struct hlist_node hash_list; + + struct exfat_cache exfat_cache; + struct inode vfs_inode; +}; + +static inline struct exfat_sb_info *EXFAT_SB(struct super_block *sb) +{ + return sb->s_fs_info; +} + +static inline struct exfat_inode_info *EXFAT_I(struct inode *inode) +{ + return container_of(inode, struct exfat_inode_info, vfs_inode); +} + +loff_t exfat_dir_links(struct inode *inode); + +int exfat_write_fat_contiguous(struct inode *inode, u32 first_cluster, + u32 nr_clusters); +int exfat_write_fat(struct inode *inode, u32 prev_cluster, u32 *clusters, + u32 nr_clusters); + +__printf(3, 4) void exfat_msg(struct super_block *sb, const char *level, + const char *fmt, ...); +__printf(2, 3) void exfat_fs_error(struct super_block *sb, + const char *fmt, ...); +int exfat_get_fat_cluster(struct inode *inode, u32 fcluster, u32 *dcluster); +int __exfat_get_fat_cluster(struct inode *inode, u32 fcluster, u32 *dcluster, + bool eof_is_fatal); + +void exfat_inode_cache_init(struct inode *inode); +void exfat_inode_cache_drop(struct inode *inode); + +int exfat_init_fat(struct super_block *sb); + +int exfat_init_bitmap(struct inode *root); +void exfat_exit_bitmap(struct super_block *sb); +int exfat_alloc_clusters(struct inode *inode, u32 hint_cluster, + u32 *cluster, u32 nr); +int exfat_free_clusters_inode(struct inode *inode, u32 start); + + +/* + * read only bitmap accessors: used by EXFAT_IOCGETBITMAP ioctl. + */ +struct exfat_bitmap_ctx { + struct super_block *sb; + struct buffer_head *bh; + sector_t cur_sector; +}; + +int exfat_init_bitmap_context(struct super_block *sb, + struct exfat_bitmap_ctx *ctx, u32 cluster); +void exfat_exit_bitmap_context(struct exfat_bitmap_ctx *ctx); +int exfat_test_bitmap(struct exfat_bitmap_ctx *ctx, uint32_t start_cluster, + uint32_t *first_in_use, uint32_t *nr_in_use); + + +/* + * return the physical sector address for a given cluster. + */ +static inline sector_t exfat_cluster_sector(struct exfat_sb_info *sbi, + u32 cluster) +{ + return (sector_t)sbi->cluster_heap_offset + (cluster - 2) * + (sector_t)sbi->sectors_per_cluster; +} + +/* + * in dir.c + */ +struct exfat_dir_ctx { + struct super_block *sb; + struct inode *inode; + struct buffer_head *bh; + + off_t off; /* from beginning of directory */ + sector_t sector; + bool empty; +}; + +int exfat_init_dir_ctx(struct inode *inode, struct exfat_dir_ctx *ctx, + off_t off); +void exfat_cleanup_dir_ctx(struct exfat_dir_ctx *dctx); +int exfat_get_cluster_hint(struct inode *inode, u32 *out_hint); +int exfat_dentry_next(void *, struct exfat_dir_ctx *, int, bool); +void *__exfat_dentry_next(struct exfat_dir_ctx *dctx, int type, int mask, + bool can_skip, bool *end); +u16 exfat_direntry_checksum(void *data, u16 checksum, bool first); +u32 exfat_dctx_fpos(struct exfat_dir_ctx *dctx); +u64 exfat_dctx_dpos(struct exfat_dir_ctx *dctx); +int __exfat_get_name(struct exfat_dir_ctx *dctx, u32 name_length, __le16 *name, + u16 *calc_checksum, struct exfat_iloc *iloc); + +/* + * in namei.c + */ + +/* + * hold a pointer to an exfat dir entry, with the corresponding bh. + */ +struct dir_entry_buffer { + struct buffer_head *bh; + u32 off; /* in bytes, inside the buffer_head b_data array */ + void *start; +}; + +int exfat_get_dir_entry_buffers(struct inode *dir, struct exfat_iloc *iloc, + struct dir_entry_buffer *entries, + size_t nr_entries); +u16 exfat_dir_entries_checksum(struct dir_entry_buffer *entries, u32 nr); +void exfat_dirty_dir_entries(struct dir_entry_buffer *entries, + size_t nr_entries, bool sync); +void exfat_write_time(struct exfat_sb_info *sbi, struct timespec *ts, + __le32 *datetime, u8 *time_cs, u8 *tz_offset); + +/* + * in inode.c + */ + +int exfat_init_inodes(void); +void exfat_exit_inodes(void); + +struct inode *exfat_iget(struct super_block *sb, loff_t disk_pos); +void exfat_insert_inode_hash(struct inode *inode); +void exfat_remove_inode_hash(struct inode *inode); +int __exfat_write_inode(struct inode *inode, bool sync); + +/* + * in upcase.c + */ +int exfat_upcase_init(struct inode *root); +static inline __le16 exfat_upcase_convert(struct super_block *sb, __le16 _c) +{ + u16 c = __le16_to_cpu(_c); + + if (c >= EXFAT_SB(sb)->upcase_len) + return _c; + return EXFAT_SB(sb)->upcase_table[c]; +} + +/* + * superblock operations + */ +struct inode *exfat_alloc_inode(struct super_block *sb); +void exfat_destroy_inode(struct inode *_inode); +int exfat_drop_inode(struct inode *inode); +void exfat_evict_inode(struct inode *inode); + +/* + * file operations + */ +int exfat_iterate(struct file *f, struct dir_context *ctx); +long exfat_ioctl(struct file *, unsigned int, unsigned long); +int exfat_truncate_blocks(struct inode *inode, loff_t newsize); + +/* + * inode operations + */ +struct dentry *exfat_inode_lookup(struct inode *, struct dentry *, + unsigned int); +int exfat_inode_create(struct inode *dir, struct dentry *dentry, umode_t mode, + bool excl); +int exfat_inode_mkdir(struct inode *dir, struct dentry *dentry, umode_t mode); + +mode_t exfat_make_mode(struct exfat_sb_info *sbi, mode_t mode, u16 attrs); + +int exfat_write_inode(struct inode *inode, struct writeback_control *wbc); + +int exfat_inode_unlink(struct inode *inode, struct dentry *dentry); + +int exfat_inode_rmdir(struct inode *inode, struct dentry *dentry); + +int exfat_getattr(const struct path *, struct kstat *, u32, unsigned int); +int exfat_setattr(struct dentry *, struct iattr *); +int exfat_rename(struct inode *, struct dentry *, + struct inode *, struct dentry *, unsigned int); + +/* + * address space operations + */ +int exfat_readpage(struct file *file, struct page *page); +int exfat_readpages(struct file *file, struct address_space *mapping, + struct list_head *pages, unsigned nr_pages); +int exfat_write_begin(struct file *file, struct address_space *mapping, + loff_t pos, unsigned len, unsigned flags, + struct page **pagep, void **fsdata); +int exfat_write_end(struct file *file, struct address_space *mapping, + loff_t pos, unsigned len, unsigned copied, + struct page *page, void *fsdata); +int exfat_writepage(struct page *page, struct writeback_control *wbc); +int exfat_writepages(struct address_space *, struct writeback_control *); + + +extern const struct inode_operations exfat_dir_inode_operations; +extern const struct inode_operations exfat_file_inode_operations; +extern const struct file_operations exfat_dir_operations; +extern const struct file_operations exfat_file_operations; +extern const struct address_space_operations exfat_address_space_operations; + +/* + * time functions + */ +void exfat_time_2unix(struct timespec *ts, u32 datetime, u8 time_cs, + s8 tz_offset); +void exfat_time_2exfat(struct exfat_sb_info *sbi, struct timespec *ts, + u32 *datetime, u8 *time_cs, s8 *tz_offset); + +static inline void exfat_lock_super(struct super_block *sb) +{ + mutex_lock(&EXFAT_SB(sb)->sb_mutex); +} + +static inline void exfat_unlock_super(struct super_block *sb) +{ + mutex_unlock(&EXFAT_SB(sb)->sb_mutex); +} + +#endif /*! __EXFAT_H */ diff -Nruw linux-4.14.127-fbx/fs/exfat./exfat_fs.h linux-4.14.127-fbx/fs/exfat/exfat_fs.h --- linux-4.14.127-fbx/fs/exfat./exfat_fs.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/fs/exfat/exfat_fs.h 2019-01-14 15:09:09.119950445 +0100 @@ -0,0 +1,200 @@ +/* + * exfat_fs.h for exfat + * Created by on Mon Jul 29 15:06:38 2013 + */ + +#ifndef __EXFAT_FS_H +# define __EXFAT_FS_H + +/* + * exfat on disk structures and constants + */ + +#include + +struct exfat_vbr { + u8 jump[3]; + u8 fsname[8]; + u8 reserved1[53]; + + __le64 partition_offset; + __le64 volume_length; + + __le32 fat_offset; + __le32 fat_length; + + __le32 cluster_heap_offset; + __le32 cluster_count; + __le32 cluster_root_dir; + + __le32 serial_number; + + __le16 fs_rev; + __le16 volume_flags; + + u8 bytes_per_sector; + u8 sectors_per_cluster; + + u8 fat_num; + u8 drive_select; + u8 heap_use_percent; + + u8 reserved2[7]; + u8 boot_code[390]; + + u8 boot_sig[2]; +}; + +enum { + EXFAT_CLUSTER_FIRSTVALID = 0x00000002, + EXFAT_CLUSTER_LASTVALID = 0xfffffff6, + EXFAT_CLUSTER_BADBLK = 0xfffffff7, + EXFAT_CLUSTER_MEDIATYPE = 0xfffffff8, + EXFAT_CLUSTER_EOF = 0xffffffff, +}; + +enum { + EXFAT_ACTIVEFAT_MASK = (1 << 0), + EXFAT_FLAG_DIRTY = (1 << 1), + EXFAT_FLAG_MEDIA_FAILURE = (1 << 2), +}; + +static inline int exfat_active_fat(u16 flags) +{ + return flags & EXFAT_ACTIVEFAT_MASK; +} + +#define EXFAT_CHECKSUM_SECTORS 11 + +enum { + EXFAT_I_ALLOC_POSSIBLE = (1 << 0), + EXFAT_I_FAT_INVALID = (1 << 1), +}; + +/* + * directory cluster content + */ + +/* + * entry types + */ +enum { + E_EXFAT_EOD = 0x00, + E_EXFAT_VOLUME_LABEL = 0x83, + E_EXFAT_BITMAP = 0x81, + E_EXFAT_UPCASE_TABLE = 0x82, + E_EXFAT_GUID = 0xa0, + E_EXFAT_PADDING = 0xa1, + E_EXFAT_ACL = 0xe2, + E_EXFAT_FILEDIR = 0x85, + E_EXFAT_STREAM_EXT = 0xc0, + E_EXFAT_FILENAME = 0xc1, +}; + +/* + * file attributes in exfat_filedir_entry + */ +enum { + E_EXFAT_ATTR_RO = (1 << 0), + E_EXFAT_ATTR_HIDDEN = (1 << 1), + E_EXFAT_ATTR_SYSTEM = (1 << 2), + /* bit 3 reserved */ + E_EXFAT_ATTR_DIRECTORY = (1 << 4), + E_EXFAT_ATTR_ARCHIVE = (1 << 5), + /* bits 6-15 reserved */ +}; + +/* type 0x83 */ +struct exfat_volume_label_entry { + u8 type; + u8 charcount; + __u16 label[11]; + u8 reserved1[8]; +}; + +static inline int exfat_bitmap_nr(u8 flags) +{ + return flags & 1; +} + +/* type 0x81 */ +struct exfat_bitmap_entry { + u8 type; + u8 flags; + u8 reserved1[18]; + __le32 cluster_addr; + __le64 length; +}; + +/* type 0x82 */ +struct exfat_upcase_entry { + u8 type; + u8 reserved1[3]; + __le32 checksum; + u8 reserved2[12]; + __le32 cluster_addr; + __le64 length; +}; + +/* type 0xa0 */ +struct exfat_guid_entry { + u8 type; + u8 secondary_count; + __le16 set_checksum; + __le16 flags; + u8 guid[16]; + u8 reserved1[10]; +}; + +/* type 0xa1 */ +struct exfat_padding_entry { + u8 type; + u8 reserved1[31]; +}; + +/* type 0xe2 */ +struct exfat_acl_entry { + u8 type; + u8 reserved1[31]; +}; + +/* type 0x85 */ +struct exfat_filedir_entry { + u8 type; + u8 secondary_count; + __le16 set_checksum; + __le16 attributes; + u8 reserved1[2]; + __le32 create; + __le32 modified; + __le32 accessed; + u8 create_10ms; + u8 modified_10ms; + s8 create_tz_offset; + s8 modified_tz_offset; + s8 accessed_tz_offset; + u8 reserved2[7]; +}; + +/* 0xc0 */ +struct exfat_stream_extension_entry { + u8 type; + u8 flags; + u8 reserved1; + u8 name_length; + __le16 name_hash; + u8 reserved2[2]; + __le64 valid_data_length; + u8 reserved3[4]; + __le32 first_cluster; + __le64 data_length; +}; + +/* 0xc1 */ +struct exfat_filename_entry { + u8 type; + u8 flags; + __le16 name_frag[15]; +}; + +#endif /*! __EXFAT_FS_H */ diff -Nruw linux-4.14.127-fbx/fs/exfat./fat.c linux-4.14.127-fbx/fs/exfat/fat.c --- linux-4.14.127-fbx/fs/exfat./fat.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/fs/exfat/fat.c 2019-01-14 15:16:37.082082405 +0100 @@ -0,0 +1,424 @@ +/* + * fat.c for exfat + * Created by on Mon Jul 29 19:43:38 2013 + */ + +#include +#include +#include + +#include "exfat.h" +#include "exfat_fs.h" + +#define MAX_CACHED_FAT 16 + +/* + * helpers for exfat_next_fat_cluster. + */ + +/* + * get the sector number in the fat where the next requested cluster + * number is to be found. + */ +static inline sector_t cluster_sector(struct exfat_sb_info *sbi, u32 cluster) +{ + return sbi->fat_offset + (((u64)cluster * sizeof (u32)) >> sbi->sectorbits); +} + +/* + * get the offset in the fat sector where the next requested cluster + * number is to be found. + */ +static inline off_t cluster_offset(struct exfat_sb_info *sbi, u32 cluster) +{ + return (cluster * sizeof (u32)) & sbi->sectormask; +} + +/* + * walk one step in the fat chain. + */ +static int exfat_next_fat_cluster(struct super_block *sb, u32 *cluster) +{ + struct exfat_sb_info *sbi = EXFAT_SB(sb); + sector_t sect = cluster_sector(sbi, *cluster); + off_t off = cluster_offset(sbi, *cluster); + struct buffer_head *bh; + + bh = sb_bread(sb, sect); + if (!bh) { + exfat_msg(sb, KERN_ERR, "unable to read FAT sector at %llu", + (unsigned long long)sect); + return -EIO; + } + + *cluster = __le32_to_cpu(*(u32*)&bh->b_data[off]); + brelse(bh); + return 0; +} + +/* + * setup inode cache + */ +void exfat_inode_cache_init(struct inode *inode) +{ + mutex_init(&EXFAT_I(inode)->exfat_cache.mutex); + EXFAT_I(inode)->exfat_cache.nr_entries = 0; + INIT_LIST_HEAD(&EXFAT_I(inode)->exfat_cache.entries); +} + +/* + * drop inode cache content + */ +void exfat_inode_cache_drop(struct inode *inode) +{ + struct exfat_cache *cache = &EXFAT_I(inode)->exfat_cache; + struct exfat_cache_entry *e, *tmp; + + mutex_lock(&cache->mutex); + list_for_each_entry_safe (e, tmp, &cache->entries, list) { + kfree(e); + } + INIT_LIST_HEAD(&cache->entries); + cache->nr_entries = 0; + mutex_unlock(&cache->mutex); +} + +/* + * move the entry to the head of the list, this will make it less + * likely to be the victim in when caching new entries. + * + * caller must hold cache->mutex. + */ +static void __exfat_fat_lru(struct exfat_cache *cache, + struct exfat_cache_entry *e) +{ + if (cache->entries.next != &e->list) + list_move(&e->list, &cache->entries); +} + +/* + * find a cache entry that is close to the wanted fcluster (ideally + * spanning over the requested file cluster). + * + * caller must hold cache->mutex. + */ +static struct exfat_cache_entry *__exfat_cache_lookup(struct exfat_cache *cache, + u32 fcluster) +{ + struct exfat_cache_entry *e; + struct exfat_cache_entry *best = NULL; + + list_for_each_entry (e, &cache->entries, list) { + if (e->file_cluster <= fcluster && + e->file_cluster + e->nr_contig >= fcluster) + return e; + + if (!best && e->file_cluster < fcluster) + best = e; + if (best && best->file_cluster < e->file_cluster && + e->file_cluster < fcluster) + best = e; + } + return best; +} + +/* + * caller must hold cache->mutex. + */ +static int __exfat_cache_cluster(struct exfat_cache *cache, + struct exfat_cache_entry *nearest, + u32 fcluster, u32 dcluster) +{ + struct exfat_cache_entry *e; + + /* + * see if we can merge with the nearest entry. in the ideal + * case, all cluster in the chain are contiguous, and only + * one entry is needed for a single file. + */ + if (nearest && + nearest->file_cluster + nearest->nr_contig + 1 == fcluster && + nearest->disk_cluster + nearest->nr_contig + 1 == dcluster) { + list_move(&nearest->list, &cache->entries); + nearest->nr_contig++; + return 0; + } + + /* + * allocate a new entry or reuse an existing one if the number + * of cached entries is too hihc. + */ + if (cache->nr_entries < MAX_CACHED_FAT) { + e = kmalloc(sizeof (*e), GFP_NOFS); + list_add(&e->list, &cache->entries); + ++cache->nr_entries; + } else { + e = list_entry(cache->entries.prev, struct exfat_cache_entry, + list); + list_move(&e->list, &cache->entries); + } + + if (!e) + return -ENOMEM; + + e->file_cluster = fcluster; + e->disk_cluster = dcluster; + e->nr_contig = 0; + + return 0; +} + +int __exfat_get_fat_cluster(struct inode *inode, u32 fcluster, u32 *dcluster, + bool eof_is_fatal) +{ + struct exfat_inode_info *info = EXFAT_I(inode); + struct exfat_cache *cache = &info->exfat_cache; + int error; + struct exfat_cache_entry *e; + u32 fcluster_start; + + /* + * intial translation: first file cluster is found in the + * inode info. + */ + if (fcluster == 0) { + *dcluster = info->first_cluster; + return 0; + } + + mutex_lock(&cache->mutex); + /* + * try to find a cached entry either covering the file cluster + * we want or at least close to the file cluster. + */ + e = __exfat_cache_lookup(cache, fcluster); + if (e && e->file_cluster <= fcluster && + e->file_cluster + e->nr_contig >= fcluster) { + /* + * perfect match, entry zone covers the requested file + * cluster. + */ + __exfat_fat_lru(cache, e); + *dcluster = e->disk_cluster + (fcluster - e->file_cluster); + mutex_unlock(&cache->mutex); + return 0; + } + + if (e) { + /* + * we have an entry, hopefully close enough, setup + * cluster walk from there. + */ + *dcluster = e->disk_cluster + e->nr_contig; + fcluster_start = e->file_cluster + e->nr_contig; + } else { + /* + * no entry, walk the FAT chain from the start of the + * file. + */ + fcluster_start = 0; + *dcluster = info->first_cluster; + } + + /* + * walk fhe FAT chain the number of time required to get the + * disk cluster corresponding to the file cluster. + */ + while (fcluster_start != fcluster) { + error = exfat_next_fat_cluster(inode->i_sb, dcluster); + if (error) { + mutex_unlock(&cache->mutex); + return error; + } + if (*dcluster == EXFAT_CLUSTER_EOF) { + if (eof_is_fatal) + /* + * exfat_fill_root uses + * __exfat_get_fat_cluster with + * eof_is_fatal set to false, as the + * root inode does not have a size + * field and thus requires a complete + * FAT walk to compute the size. + */ + exfat_fs_error(inode->i_sb, "premature EOF in FAT " + "chain. file cluster %u out " + "of %u\n", fcluster_start, + fcluster); + mutex_unlock(&cache->mutex); + return -EIO; + } + if (*dcluster < EXFAT_CLUSTER_FIRSTVALID) { + exfat_fs_error(inode->i_sb, "invalid cluster %u found " + "in fat chain.", *dcluster); + mutex_unlock(&cache->mutex); + return -EIO; + } + ++fcluster_start; + } + + /* + * cache the result. + */ + __exfat_cache_cluster(cache, e, fcluster, *dcluster); + mutex_unlock(&cache->mutex); + return 0; +} + +int exfat_get_fat_cluster(struct inode *inode, u32 fcluster, u32 *dcluster) +{ + return __exfat_get_fat_cluster(inode, fcluster, dcluster, true); +} + +int exfat_init_fat(struct super_block *sb) +{ + struct exfat_sb_info *sbi = EXFAT_SB(sb); + struct buffer_head *bh; + int error = 0; + u32 first, second; + + bh = sb_bread(sb, sbi->fat_offset); + if (!bh) { + exfat_msg(sb, KERN_ERR, "unable to read FAT sector at %u", + sbi->fat_offset); + return -EIO; + } + + first = __le32_to_cpu(*(__le32*)(bh->b_data + 0)); + second = __le32_to_cpu(*(__le32*)(bh->b_data + sizeof (__le32))); + + if (first != 0xf8ffffff && second != 0xffffffff) { + exfat_msg(sb, KERN_INFO, "invalid FAT start: %08x, %08x", + first, second); + error = -ENXIO; + } + + brelse(bh); + return error; +} + +/* + * fat write context, store the current buffer_head and current + * cluster to avoid having sb_bread all the time when the clusters are + * contiguous or at least not too far apart. + */ +struct fat_write_ctx { + struct super_block *sb; + struct buffer_head *bh; + u32 cur_cluster; +}; + +static void fat_init_write_ctx(struct fat_write_ctx *fwctx, + struct super_block *sb) +{ + memset(fwctx, 0, sizeof (*fwctx)); + fwctx->sb = sb; +} + +static void fat_exit_write_ctx(struct fat_write_ctx *fwctx) +{ + if (fwctx->bh) + brelse(fwctx->bh); +} + +static int __fat_write_entry(struct fat_write_ctx *fwctx, + u32 cluster, u32 next) +{ + struct exfat_sb_info *sbi = EXFAT_SB(fwctx->sb); + sector_t current_sector = cluster_sector(sbi, fwctx->cur_cluster); + sector_t wanted_sector = cluster_sector(sbi, cluster); + off_t off = cluster_offset(sbi, cluster); + + /* + * first see if we need a different buffer head from the + * current one in the fat_write_ctx. + */ + if (current_sector != wanted_sector || !fwctx->bh) { + if (fwctx->bh) + brelse(fwctx->bh); + fwctx->bh = sb_bread(fwctx->sb, wanted_sector); + if (!fwctx->bh) { + exfat_msg(fwctx->sb, KERN_ERR, + "unable to read FAT sector at %llu", + (unsigned long long)wanted_sector); + return -EIO; + } + } + + /* + * set fat cluster to point to the next cluster, and mark bh + * dirty so that the change hits the storage device. + */ + fwctx->cur_cluster = cluster; + *(__le32*)(fwctx->bh->b_data + off) = __cpu_to_le32(next); + mark_buffer_dirty(fwctx->bh); + return 0; +} + +/* + * write nr_clusters contiguous clusters starting at first_cluster. + */ +int exfat_write_fat_contiguous(struct inode *inode, u32 first_cluster, + u32 nr_clusters) +{ + u32 cluster; + struct fat_write_ctx fwctx; + int error = 0; + + fat_init_write_ctx(&fwctx, inode->i_sb); + for (cluster = first_cluster; + cluster < first_cluster + nr_clusters - 1; + ++cluster) { + error = __fat_write_entry(&fwctx, cluster, cluster + 1); + if (error) + goto end; + } + + /* + * set EOF + */ + error = __fat_write_entry(&fwctx, cluster, EXFAT_CLUSTER_EOF); +end: + fat_exit_write_ctx(&fwctx); + return error; + +} + +/* + * write cluster nr_clusters stored in clusters array, link with prev_cluster. + */ +int exfat_write_fat(struct inode *inode, u32 prev_cluster, u32 *clusters, + u32 nr_clusters) +{ + u32 i; + struct fat_write_ctx fwctx; + int error; + + if (!nr_clusters) + /* ??! */ + return 0; + + fat_init_write_ctx(&fwctx, inode->i_sb); + + if (prev_cluster) { + /* + * link with previous cluster if applicable. + */ + error = __fat_write_entry(&fwctx, prev_cluster, clusters[0]); + if (error) + goto end; + } + for (i = 0; i < nr_clusters - 1; ++i) { + error = __fat_write_entry(&fwctx, clusters[i], clusters[i + 1]); + if (error) + goto end; + } + + /* + * set EOF. + */ + error = __fat_write_entry(&fwctx, clusters[i], EXFAT_CLUSTER_EOF); + + end: + fat_exit_write_ctx(&fwctx); + return error; +} diff -Nruw linux-4.14.127-fbx/fs/exfat./file.c linux-4.14.127-fbx/fs/exfat/file.c --- linux-4.14.127-fbx/fs/exfat./file.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/fs/exfat/file.c 2019-02-15 14:29:43.726663128 +0100 @@ -0,0 +1,427 @@ +/* + * file.c for exfat + * Created by on Tue Aug 20 14:39:41 2013 + */ + +#include +#include +#include + +#include "exfat.h" +#include "exfat_fs.h" + +static int append_fragment(struct exfat_fragment __user *ufrag, + struct exfat_fragment *kfrag) +{ + if (copy_to_user(ufrag, kfrag, sizeof (*kfrag))) + return -EFAULT; + return 0; +} + +static void setup_fragment(struct exfat_sb_info *sbi, + struct exfat_fragment *fragment, uint32_t fcluster, + uint32_t dcluster) +{ + fragment->fcluster_start = fcluster; + fragment->dcluster_start = dcluster; + fragment->sector_start = exfat_cluster_sector(sbi, dcluster); + fragment->nr_clusters = 1; +} + +static int exfat_ioctl_get_fragments(struct inode *inode, + struct exfat_fragment_head __user *uhead) +{ + struct exfat_fragment_head head; + struct exfat_fragment fragment; + u32 fcluster; + u32 prev_dcluster; + u32 cur_fragment; + struct exfat_inode_info *info = EXFAT_I(inode); + struct exfat_sb_info *sbi = EXFAT_SB(inode->i_sb); + int error; + + memset(&fragment, 0, sizeof (fragment)); + + if (copy_from_user(&head, uhead, sizeof (head))) + return -EFAULT; + + + if (put_user(sbi->sectorsize, &uhead->sector_size) || + put_user(sbi->clustersize, &uhead->cluster_size)) + return -EFAULT; + + if (!head.nr_fragments) { + /* + * user did not provide space for fragments after + * header. + */ + return 0; + } + + if (head.fcluster_start >= info->allocated_clusters) { + /* + * requested start cluster is after file EOF + */ + if (put_user(0, &uhead->nr_fragments)) + return -EFAULT; + return 0; + } + + if (info->flags & EXFAT_I_FAT_INVALID) { + /* + * not FAT chain, this file has only one fragment. + */ + fragment.fcluster_start = head.fcluster_start; + fragment.dcluster_start = + info->first_cluster + head.fcluster_start; + fragment.nr_clusters = info->allocated_clusters - + head.fcluster_start; + fragment.sector_start = + exfat_cluster_sector(sbi, fragment.dcluster_start); + + if (copy_to_user(&uhead->fragments[0], &fragment, + sizeof (fragment))) + return -EFAULT; + if (put_user(1, &uhead->nr_fragments)) + return -EFAULT; + if (put_user(info->first_cluster + info->allocated_clusters, + &uhead->fcluster_start)) + return -EFAULT; + return 0; + } + + fcluster = head.fcluster_start; + cur_fragment = 0; + + /* + * initial fragment setup + */ + error = exfat_get_fat_cluster(inode, fcluster, + &prev_dcluster); + if (error) + return error; + setup_fragment(sbi, &fragment, fcluster, prev_dcluster); + ++fcluster; + while (fcluster < info->allocated_clusters) { + int error; + u32 dcluster; + + /* + * walk one step in the FAT. + */ + error = exfat_get_fat_cluster(inode, fcluster, &dcluster); + if (error) + return error; + + if (prev_dcluster == dcluster - 1) { + /* + * dcluster and prev_dcluster are contiguous. + */ + ++fragment.nr_clusters; + } else { + /* + * put this cluster in the user array + */ + error = append_fragment(&uhead->fragments[cur_fragment], + &fragment); + if (error) + return error; + + ++cur_fragment; + if (cur_fragment == head.nr_fragments) + break; + + /* + * setup a new fragment. + */ + setup_fragment(sbi, &fragment, fcluster, dcluster); + } + ++fcluster; + prev_dcluster = dcluster; + } + + if (cur_fragment < head.nr_fragments) { + append_fragment(&uhead->fragments[cur_fragment], &fragment); + ++cur_fragment; + } + + /* + * update nr_fragments in user supplied head. + */ + if (cur_fragment != head.nr_fragments && + put_user(cur_fragment, &uhead->nr_fragments)) + return -EFAULT; + + /* + * update fcluster_start in user supplied head. + */ + if (put_user(fcluster, &uhead->fcluster_start)) + return -EFAULT; + + + return 0; +} + +static int exfat_ioctl_get_bitmap(struct super_block *sb, + struct exfat_bitmap_head __user *uhead) +{ + struct exfat_sb_info *sbi = EXFAT_SB(sb); + struct exfat_bitmap_head head; + uint32_t i; + int error; + struct exfat_bitmap_ctx ctx; + uint32_t start_cluster; + + if (copy_from_user(&head, uhead, sizeof (head))) + return -EFAULT; + + start_cluster = head.start_cluster; + if (start_cluster < 2) + return -EINVAL; + + + error = exfat_init_bitmap_context(sb, &ctx, head.start_cluster); + if (error) + return error; + for (i = 0; i < head.nr_entries; ++i) { + uint32_t first_in_use; + uint32_t nr_in_use; + int error; + + error = exfat_test_bitmap(&ctx, start_cluster, &first_in_use, + &nr_in_use); + if (error) + goto out_error; + + if (first_in_use == sbi->cluster_count) + break; + if (put_user(first_in_use, &uhead->entries[i].start_cluster)) + goto out_efault; + if (put_user(nr_in_use, &uhead->entries[i].nr_clusters)) + goto out_efault; + if (put_user(exfat_cluster_sector(sbi, first_in_use), + &uhead->entries[i].sector_start)) + goto out_efault; + if (put_user((u64)nr_in_use * sbi->sectors_per_cluster, + &uhead->entries[i].nr_sectors)) + goto out_efault; + start_cluster = first_in_use + nr_in_use + 1; + } + + exfat_exit_bitmap_context(&ctx); + if (put_user(i, &uhead->nr_entries)) + return -EFAULT; + if (put_user(start_cluster, &uhead->start_cluster)) + return -EFAULT; + + return 0; + +out_efault: + error = -EFAULT; +out_error: + exfat_exit_bitmap_context(&ctx); + return error; +} + +static int exfat_ioctl_get_dirents(struct inode *inode, + struct exfat_dirent_head __user *uhead) +{ + struct exfat_dir_ctx dctx; + struct exfat_dirent_head head; + int error; + uint32_t i; + + if (!S_ISDIR(inode->i_mode)) + return -ENOTDIR; + + if (copy_from_user(&head, uhead, sizeof (head))) + return -EFAULT; + + /* make sure we're aligned on an entry boundary */ + head.offset &= ~0x1f; + + error = exfat_init_dir_ctx(inode, &dctx, head.offset); + if (error < 0) + return error; + + error = 0; + for (i = 0; i < head.nr_entries; ++i) { + bool end; + u8 *entry = __exfat_dentry_next(&dctx, 0, 0, false, &end); + u8 type; + + if (!entry && end) + /* genuine end of file */ + break; + if (!entry) { + /* something went wrong */ + error = -EIO; + goto out; + } + type = *entry; + + if (put_user(type, &uhead->entries[i])) { + error = -EFAULT; + goto out; + } + } + + /* + * update head nr_entries and offset. + */ + if (put_user(i, &uhead->nr_entries)) { + error = -EFAULT; + goto out; + } + if (put_user(head.offset + 0x20 * i, &uhead->offset)) { + error = -EFAULT; + goto out; + } + + out: + exfat_cleanup_dir_ctx(&dctx); + return error; +} + +long exfat_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + switch (cmd) { + case EXFAT_IOCGETFRAGMENTS: + return exfat_ioctl_get_fragments(file_inode(file), + (void __user*)arg); + case EXFAT_IOCGETBITMAP: + return exfat_ioctl_get_bitmap(file_inode(file)->i_sb, + (void __user*)arg); + case EXFAT_IOCGETDIRENTS: + return exfat_ioctl_get_dirents(file_inode(file), + (void __user*)arg); + default: + return -ENOTTY; + } +} + +static int exfat_cont_expand(struct inode *inode, loff_t newsize) +{ + int error; + + error = generic_cont_expand_simple(inode, newsize); + if (error) + return error; + + inode->i_mtime = current_time(inode); + mark_inode_dirty(inode); + + if (IS_SYNC(inode)) + exfat_msg(inode->i_sb, KERN_ERR, "TODO: cont_expand with " + "sync mode."); + return 0; +} + +int exfat_truncate_blocks(struct inode *inode, loff_t newsize) +{ + struct exfat_sb_info *sbi = EXFAT_SB(inode->i_sb); + u32 fcluster = (newsize + sbi->clustersize - 1) >> sbi->clusterbits; + int error; + + if (EXFAT_I(inode)->mmu_private > newsize) + EXFAT_I(inode)->mmu_private = newsize; + + error = exfat_free_clusters_inode(inode, fcluster); + if (error) { + exfat_msg(inode->i_sb, KERN_INFO, "exfat_free_clusters_inode: " + "%i", error); + return error; + } + + return 0; +} + +int exfat_getattr(const struct path *path, struct kstat *stat, u32 request_mask, + unsigned int flags) +{ + struct inode *inode = d_inode(path->dentry); + generic_fillattr(inode, stat); + stat->blksize = EXFAT_SB(inode->i_sb)->clustersize; + return 0; +} + +#define EXFAT_VALID_MODE (S_IFREG | S_IFDIR | S_IRWXUGO) + +static int exfat_mode_fixup(struct inode *inode, umode_t *mode) +{ + mode_t mask, perm; + struct exfat_sb_info *sbi = EXFAT_SB(inode->i_sb); + + if (S_ISDIR(*mode)) + mask = sbi->options.dmask; + else + mask = sbi->options.fmask; + + perm = *mode & ~(S_IFMT | mask); + + /* + * we want 'r' and 'x' bits when mask allows for it. + */ + if ((perm & (S_IRUGO | S_IXUGO)) != + (inode->i_mode & ~mask & (S_IRUGO | S_IXUGO))) { + return -EPERM; + } + + /* + * we want all 'w' bits or none, depending on mask. + */ + if ((perm & S_IWUGO) && (perm & S_IWUGO) != (~mask & S_IWUGO)) + return -EPERM; + *mode &= ~mask; + return 0; +} + +int exfat_setattr(struct dentry *dentry, struct iattr *attrs) +{ + struct inode *inode = dentry->d_inode; + int error; + + /* + * can set uid/gid, only if it the same as the current one in + * the inode. + */ + if (attrs->ia_valid & ATTR_UID && + !uid_eq(inode->i_uid, attrs->ia_uid)) + return -EPERM; + + if (attrs->ia_valid & ATTR_GID && + !gid_eq(inode->i_gid, attrs->ia_gid)) + return -EPERM; + + if (attrs->ia_valid & ATTR_MODE && + (attrs->ia_mode & ~EXFAT_VALID_MODE || + exfat_mode_fixup(inode, &attrs->ia_mode) < 0)) { + /* + * silently ignore mode change if we're not OK with + * it (same behavior as vfat). + */ + attrs->ia_valid &= ~ATTR_MODE; + } + + if (attrs->ia_valid & ATTR_SIZE) { + inode_dio_wait(inode); + if (attrs->ia_size > inode->i_size) { + /* + * expand file + */ + error = exfat_cont_expand(inode, attrs->ia_size); + if (error) + return error; + } else { + /* + * shrink file + */ + truncate_setsize(inode, attrs->ia_size); + exfat_truncate_blocks(inode, attrs->ia_size); + } + } + + setattr_copy(inode, attrs); + mark_inode_dirty(inode); + return 0; +} diff -Nruw linux-4.14.127-fbx/fs/exfat./inode.c linux-4.14.127-fbx/fs/exfat/inode.c --- linux-4.14.127-fbx/fs/exfat./inode.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/fs/exfat/inode.c 2019-01-14 15:16:37.082082405 +0100 @@ -0,0 +1,277 @@ +/* + * inode.c<2> for exfat + * Created by on Wed Jul 24 16:15:52 2013 + */ + +#include +#include +#include +#include +#include +#include + +#include "exfat_fs.h" +#include "exfat.h" + +static struct kmem_cache *exfat_inodes_cachep; + +/* + * inode callbacks. + */ +struct inode *exfat_alloc_inode(struct super_block *sb) +{ + struct exfat_inode_info *ei = kmem_cache_alloc(exfat_inodes_cachep, + GFP_NOFS); + + if (!ei) + return NULL; + + return &ei->vfs_inode; +} + +static void exfat_i_callback(struct rcu_head *head) +{ + struct inode *inode = container_of(head, struct inode, i_rcu); + + kmem_cache_free(exfat_inodes_cachep, EXFAT_I(inode)); +} + +void exfat_destroy_inode(struct inode *_inode) +{ + struct exfat_inode_info *inode = EXFAT_I(_inode); + + call_rcu(&inode->vfs_inode.i_rcu, exfat_i_callback); +} + +static void exfat_inode_init_once(void *ptr) +{ + struct exfat_inode_info *info = ptr; + + INIT_HLIST_NODE(&info->hash_list); + exfat_inode_cache_init(&info->vfs_inode); + inode_init_once(&info->vfs_inode); +} + +/* + * inode cache create/destroy. + */ +int exfat_init_inodes(void) +{ + exfat_inodes_cachep = kmem_cache_create("exfat-inodes", + sizeof (struct exfat_inode_info), 0, + SLAB_RECLAIM_ACCOUNT |SLAB_MEM_SPREAD, + exfat_inode_init_once); + if (!exfat_inodes_cachep) + return -ENOMEM; + return 0; +} + +void exfat_exit_inodes(void) +{ + kmem_cache_destroy(exfat_inodes_cachep); +} + +int exfat_drop_inode(struct inode *inode) +{ + return generic_drop_inode(inode); +} + +void exfat_evict_inode(struct inode *inode) +{ + truncate_inode_pages_final(&inode->i_data); + if (!inode->i_nlink) { + inode->i_size = 0; + exfat_free_clusters_inode(inode, 0); + } + invalidate_inode_buffers(inode); + clear_inode(inode); + exfat_remove_inode_hash(inode); + exfat_inode_cache_drop(inode); +} + +static u32 exfat_hash(loff_t disk_pos) +{ + return hash_32(disk_pos, EXFAT_HASH_BITS); +} + +struct inode *exfat_iget(struct super_block *sb, loff_t disk_pos) +{ + struct exfat_inode_info *info; + struct exfat_sb_info *sbi = EXFAT_SB(sb); + struct hlist_head *head = sbi->inode_hash + exfat_hash(disk_pos); + struct inode *ret = NULL; + + + spin_lock(&sbi->inode_hash_lock); + hlist_for_each_entry (info, head, hash_list) { + if (info->iloc.disk_offs[0] != disk_pos) + continue ; + ret = igrab(&info->vfs_inode); + if (ret) + break; + } + spin_unlock(&sbi->inode_hash_lock); + return ret; +} + +void exfat_insert_inode_hash(struct inode *inode) +{ + struct exfat_sb_info *sbi = EXFAT_SB(inode->i_sb); + struct exfat_inode_info *info = EXFAT_I(inode); + struct hlist_head *head = sbi->inode_hash + + exfat_hash(info->iloc.disk_offs[0]); + + spin_lock(&sbi->inode_hash_lock); + hlist_add_head(&info->hash_list, head); + spin_unlock(&sbi->inode_hash_lock); +} + +void exfat_remove_inode_hash(struct inode *inode) +{ + struct exfat_inode_info *info = EXFAT_I(inode); + struct exfat_sb_info *sbi = EXFAT_SB(inode->i_sb); + + spin_lock(&sbi->inode_hash_lock); + info->iloc.disk_offs[0] = 0; + hlist_del_init(&info->hash_list); + spin_unlock(&sbi->inode_hash_lock); +} + +/* + * calculate the number of links in a directory. this is the number of + * EXFAT_FILEDIR_ENTRY typed elements in the directory stream. This + * does not include the '.' and '..' entries. + */ +loff_t exfat_dir_links(struct inode *inode) +{ + size_t ret = 0; + struct exfat_dir_ctx dctx; + int error; + bool end; + + error = exfat_init_dir_ctx(inode, &dctx, 0); + if (error) + return error; + + error = -EIO; + for (;;) { + struct exfat_filedir_entry *e = + __exfat_dentry_next(&dctx, E_EXFAT_FILEDIR, 0xff, + true, &end); + if (!e) { + if (end) + error = 0; + goto out; + } + ++ret; + } +out: + exfat_cleanup_dir_ctx(&dctx); + if (error) + return error; + return ret; +} + +int exfat_get_cluster_hint(struct inode *inode, u32 *out_hint) +{ + struct exfat_inode_info *info = EXFAT_I(inode); + int error; + u32 first_cluster = info->first_cluster; + + + if (!first_cluster) { + /* + * empty file, return a cluster likely to be free. + */ + *out_hint = EXFAT_SB(inode->i_sb)->prev_free_cluster + 2; + return 0; + } + + if (info->flags & EXFAT_I_FAT_INVALID) { + /* + * not fat run, all clusters are contiguous, set hint + * to next last file cluster. + */ + *out_hint = first_cluster + info->allocated_clusters; + return 0; + } + + /* + * fat run available, walk it to get the last physical cluster + * address and set hint to the immediate next physical + * cluster. + */ + error = exfat_get_fat_cluster(inode, info->allocated_clusters - 1, + out_hint); + if (error) + return error; + (*out_hint)++; + return 0; +} + +int __exfat_write_inode(struct inode *inode, bool sync) +{ + struct exfat_sb_info *sbi = EXFAT_SB(inode->i_sb); + struct exfat_inode_info *info = EXFAT_I(inode); + struct dir_entry_buffer entries[info->iloc.nr_secondary]; + int error; + struct exfat_filedir_entry *efd; + struct exfat_stream_extension_entry *esx; + u16 checksum; + + if (inode->i_ino == EXFAT_ROOT_INO) + return 0; + + if (info->iloc.disk_offs[0] == 0) { + /* + * write_inode() to unlinked inode: don't corrupt + * superblock. + */ + return 0; + } + + error = exfat_get_dir_entry_buffers(inode, &info->iloc, + entries, info->iloc.nr_secondary); + if (error) + return error; + + if (inode->i_mode & S_IWUGO) + info->attributes &= ~E_EXFAT_ATTR_RO; + else + info->attributes |= E_EXFAT_ATTR_RO; + + efd = entries[0].start; + esx = entries[1].start; + + efd->attributes = __cpu_to_le16(info->attributes); + esx->data_length = __cpu_to_le64(inode->i_size); + esx->valid_data_length = esx->data_length = + __cpu_to_le64(inode->i_size); + esx->flags = info->flags; + esx->first_cluster = __cpu_to_le32(info->first_cluster); + + exfat_write_time(sbi, &inode->i_ctime, &efd->create, &efd->create_10ms, + &efd->create_tz_offset); + exfat_write_time(sbi, &inode->i_mtime, &efd->modified, + &efd->modified_10ms, &efd->modified_tz_offset); + exfat_write_time(sbi, &inode->i_atime, &efd->accessed, NULL, + &efd->accessed_tz_offset); + + checksum = exfat_dir_entries_checksum(entries, info->iloc.nr_secondary); + efd->set_checksum = __cpu_to_le16(checksum); + + exfat_dirty_dir_entries(entries, info->iloc.nr_secondary, sync); + + + return 0; +} + +int exfat_write_inode(struct inode *inode, struct writeback_control *wbc) +{ + int ret; + + exfat_lock_super(inode->i_sb); + ret = __exfat_write_inode(inode, wbc->sync_mode == WB_SYNC_ALL); + exfat_unlock_super(inode->i_sb); + return ret; +} diff -Nruw linux-4.14.127-fbx/fs/exfat./namei.c linux-4.14.127-fbx/fs/exfat/namei.c --- linux-4.14.127-fbx/fs/exfat./namei.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/fs/exfat/namei.c 2019-02-15 14:29:43.726663128 +0100 @@ -0,0 +1,929 @@ +/* + * namei.c for exfat + * Created by on Tue Aug 20 12:00:27 2013 + */ + +#include +#include +#include +#include +#include + +#include "exfat.h" +#include "exfat_fs.h" + +static u16 exfat_filename_hash_cont(struct super_block *sb, + const __le16 *name, u16 hash, size_t len); + + +void exfat_write_time(struct exfat_sb_info *sbi, struct timespec *ts, + __le32 *datetime, u8 *time_cs, u8 *tz_offset) +{ + u32 cpu_datetime; + + exfat_time_2exfat(sbi, ts, &cpu_datetime, time_cs, tz_offset); + *datetime = __cpu_to_le32(cpu_datetime); +} + +static void exfat_read_time(struct timespec *ts, __le32 datetime, u8 time_cs, + u8 tz_offset) +{ + u32 cpu_datetime = __le32_to_cpu(datetime); + exfat_time_2unix(ts, cpu_datetime, time_cs, tz_offset); +} + +static int exfat_zero_cluster(struct super_block *sb, u32 cluster, bool sync) +{ + sector_t start = exfat_cluster_sector(EXFAT_SB(sb), cluster); + sector_t end = start + EXFAT_SB(sb)->sectors_per_cluster; + sector_t sect; + + for (sect = start; sect < end; ++sect) { + struct buffer_head *bh = sb_bread(sb, sect); + if (!bh) { + exfat_msg(sb, KERN_WARNING, + "unable to read sector %llu for zeroing.", + (unsigned long long)sect); + return -EIO; + } + memset(bh->b_data, 0, bh->b_size); + mark_buffer_dirty(bh); + if (sync) + sync_dirty_buffer(bh); + brelse(bh); + } + return 0; +} + +/* + * use per superblock fmask or dmaks, depending on provided entry + * attribute to restrict the provided mode even more. + */ +mode_t exfat_make_mode(struct exfat_sb_info *sbi, mode_t mode, u16 attrs) +{ + if (attrs & E_EXFAT_ATTR_DIRECTORY) + mode = (mode & ~sbi->options.dmask) | S_IFDIR; + else + mode = (mode & ~sbi->options.fmask) | S_IFREG; + if (attrs & E_EXFAT_ATTR_RO) + mode &= ~S_IWUGO; + return mode; +} + +/* + * populate inode fields. + */ +static struct inode *exfat_populate_inode(struct super_block *sb, + const struct exfat_filedir_entry *efd, + const struct exfat_stream_extension_entry *esx, + const struct exfat_iloc *iloc) +{ + struct exfat_sb_info *sbi = EXFAT_SB(sb); + struct inode *inode; + + inode = exfat_iget(sb, iloc->disk_offs[0]); + if (inode) + return inode; + + inode = new_inode(sb); + if (!inode) + return NULL; + + inode->i_ino = iunique(sb, EXFAT_ROOT_INO); + EXFAT_I(inode)->first_cluster = __le32_to_cpu(esx->first_cluster); + EXFAT_I(inode)->flags = esx->flags; + EXFAT_I(inode)->iloc = *iloc; + EXFAT_I(inode)->attributes = __le16_to_cpu(efd->attributes); + + inode->i_size = __le64_to_cpu(esx->data_length); + EXFAT_I(inode)->allocated_clusters = inode->i_size >> sbi->clusterbits; + if (inode->i_size & sbi->clustermask) + EXFAT_I(inode)->allocated_clusters++; + inode->i_blocks = EXFAT_I(inode)->allocated_clusters << + (sbi->clusterbits - 9); + EXFAT_I(inode)->mmu_private = inode->i_size; + + inode->i_uid = sbi->options.uid; + inode->i_gid = sbi->options.gid; + inode->i_mode = exfat_make_mode(sbi, S_IRWXUGO, + EXFAT_I(inode)->attributes); + + if (EXFAT_I(inode)->attributes & E_EXFAT_ATTR_DIRECTORY) { + loff_t nlinks = exfat_dir_links(inode); + if (nlinks < 0) + goto iput; + set_nlink(inode, nlinks + 2); + } else + set_nlink(inode, 1); + + if (esx->data_length != esx->valid_data_length) + exfat_msg(sb, KERN_WARNING, "data length (%llu) != valid data " + "length (%llu)", __le64_to_cpu(esx->data_length), + __le64_to_cpu(esx->valid_data_length)); + + if (S_ISDIR(inode->i_mode)) { + inode->i_fop = &exfat_dir_operations; + inode->i_op = &exfat_dir_inode_operations; + } else { + /* until we support write */ + inode->i_fop = &exfat_file_operations; + inode->i_op = &exfat_file_inode_operations; + inode->i_data.a_ops = &exfat_address_space_operations; + } + + + exfat_read_time(&inode->i_ctime, efd->create, efd->create_10ms, + efd->create_tz_offset); + exfat_read_time(&inode->i_mtime, efd->modified, efd->modified_10ms, + efd->modified_tz_offset); + exfat_read_time(&inode->i_atime, efd->accessed, 0, + efd->accessed_tz_offset); + + exfat_insert_inode_hash(inode); + insert_inode_hash(inode); + return inode; +iput: + iput(inode); + return NULL; +} + +/* + * lookup an inode. + */ +struct dentry *exfat_inode_lookup(struct inode *parent, struct dentry *dentry, + unsigned int flags) +{ + struct super_block *sb = dentry->d_sb; + struct exfat_dir_ctx dctx; + int error; + struct exfat_filedir_entry efd; + struct exfat_stream_extension_entry esx; + __le16 *name = __getname(); + __le16 *utf16_name = __getname(); + unsigned int utf16_name_length; + __le16 name_hash; + + exfat_lock_super(parent->i_sb); + + if (!name || !utf16_name) { + error = -ENOMEM; + goto putnames; + } + + utf16_name_length = utf8s_to_utf16s(dentry->d_name.name, + dentry->d_name.len, + UTF16_LITTLE_ENDIAN, + utf16_name, 255 + 2); + if (utf16_name_length > 255) { + error = -ENAMETOOLONG; + goto putnames; + } + + /* + * get the name hash of the wanted inode early so that we can + * skip entries with only an efd and an esx entry. + */ + name_hash = __cpu_to_le16(exfat_filename_hash_cont(sb, utf16_name, 0, + utf16_name_length)); + + /* + * create a dir ctx from the parent so that we can iterate on + * it. + */ + error = exfat_init_dir_ctx(parent, &dctx, 0); + if (error) + goto putnames; + + for (;;) { + u32 name_length; + struct inode *inode; + u16 calc_checksum; + u16 expect_checksum; + struct exfat_iloc iloc; + + memset(&iloc, 0, sizeof (iloc)); + /* + * get filedir and stream extension entries. + */ + error = exfat_dentry_next(&efd, &dctx, E_EXFAT_FILEDIR, true); + if (error < 0) + /* end of directory reached, or other error */ + goto cleanup; + + error = -EINVAL; + if (efd.secondary_count > 18) + goto cleanup; + + iloc.file_off = exfat_dctx_fpos(&dctx); + iloc.disk_offs[0] = exfat_dctx_dpos(&dctx); + iloc.nr_secondary = efd.secondary_count + 1; + + error = exfat_dentry_next(&esx, &dctx, E_EXFAT_STREAM_EXT, + false); + if (error) + goto cleanup; + + if (esx.name_hash != name_hash) + /* + * stored name hash is not the same as the + * wanted hash: no point in processing the + * remaining entries for the current efd/esx + * any further. + */ + continue ; + + /* + * now that the hash matches it is ok to update the + * checksum for the efd and esx entries. + */ + expect_checksum = __le16_to_cpu(efd.set_checksum); + calc_checksum = exfat_direntry_checksum(&efd, 0, true); + + calc_checksum = exfat_direntry_checksum(&esx, + calc_checksum, false); + iloc.disk_offs[1] = exfat_dctx_dpos(&dctx); + + /* + * fetch name. + */ + name_length = esx.name_length; + error = __exfat_get_name(&dctx, name_length, name, + &calc_checksum, &iloc); + if (error) + goto cleanup; + + if (calc_checksum != expect_checksum) { + exfat_msg(dctx.sb, KERN_INFO, "checksum: " + "calculated %04x, expect %04x", + calc_checksum, expect_checksum); + error = -EIO; + goto cleanup; + } + + + if (utf16_name_length != name_length) + continue ; + + if (memcmp(utf16_name, name, name_length * sizeof (__le16))) + continue ; + + inode = exfat_populate_inode(sb, &efd, &esx, &iloc); + if (inode) { + d_add(dentry, inode); + error = 0; + } else + error = -EIO; + goto cleanup; + } + +cleanup: + exfat_cleanup_dir_ctx(&dctx); +putnames: + if (name) + __putname(name); + if (utf16_name) + __putname(utf16_name); + exfat_unlock_super(parent->i_sb); + if (error && error != -ENOENT) + return ERR_PTR(error); + return NULL; +} + +/* + * find nr unused directory entries (type & 0x80 == 0). + */ +static int exfat_find_dir_iloc(struct inode *inode, int nr, + struct exfat_iloc *iloc) +{ + struct exfat_dir_ctx dctx; + bool end = false; + int error; + struct exfat_sb_info *sbi = EXFAT_SB(inode->i_sb); + u32 nr_new_clusters, i; + u32 new_clusters[2]; + u32 hint_cluster; + +retry: + memset(iloc, 0, sizeof (*iloc)); + iloc->nr_secondary = nr; + + error = exfat_init_dir_ctx(inode, &dctx, 0); + if (error) + return error; + + while (1) { + int nr_free; + void *ent; + + ent = __exfat_dentry_next(&dctx, 0x00, 0x80, true, &end); + if (end) + break; + if (!ent) { + exfat_cleanup_dir_ctx(&dctx); + return -EIO; + } + + nr_free = 1; + iloc->file_off = exfat_dctx_fpos(&dctx); + iloc->disk_offs[0] = exfat_dctx_dpos(&dctx); + while (__exfat_dentry_next(&dctx, 0x00, 0x80, false, &end) + != NULL && nr_free < nr) { + iloc->disk_offs[nr_free] = exfat_dctx_dpos(&dctx); + ++nr_free; + } + if (nr_free == nr) { + /* + * we found enough consecutive free entries. + */ + exfat_cleanup_dir_ctx(&dctx); + return 0; + } + + } + + /* + * not enough consecutive free entries found, kick the cluster + * allocator and retry. + */ + exfat_cleanup_dir_ctx(&dctx); + + /* + * with the smallest cluster size, a file can take more than + * two clusters. allocate two in that case reardless of what + * is needed to make code simplier. + */ + switch (sbi->clustersize) { + case 512: + nr_new_clusters = 2; + break; + default: + nr_new_clusters = 1; + break; + } + + /* + * get a hint cluster for the cluster allocator. + */ + error = exfat_get_cluster_hint(inode, &hint_cluster); + if (error) + return error; + + /* + * peform the allocation. + */ + error = exfat_alloc_clusters(inode, hint_cluster, new_clusters, + nr_new_clusters); + if (error) + return error; + + /* + * fill new cluster(s) with zero. + */ + for (i = 0; i < nr_new_clusters; ++i) + exfat_zero_cluster(inode->i_sb, new_clusters[i], false); + + /* + * update size and mark inode as dirty so that write_inode() + * can update it's size, and the other fields updated by + * exfat_alloc_clusters. + */ + inode->i_size += nr_new_clusters << sbi->clusterbits; + mark_inode_dirty(inode); + + /* + * kick the whole place search again, this time with the newly + * allocated clusters. + */ + goto retry; +} + +/* + * setup dir_entry_buffers starting at using iloc. + */ +int exfat_get_dir_entry_buffers(struct inode *dir, struct exfat_iloc *iloc, + struct dir_entry_buffer *entries, + size_t nr_entries) +{ + size_t i; + int error; + struct exfat_sb_info *sbi = EXFAT_SB(dir->i_sb); + + BUG_ON(iloc->nr_secondary != nr_entries); + + memset(entries, 0, sizeof (*entries) * nr_entries); + for (i = 0; i < nr_entries; ++i) { + sector_t sector = iloc->disk_offs[i] >> sbi->sectorbits; + + entries[i].off = iloc->disk_offs[i] & sbi->sectormask; + entries[i].bh = sb_bread(dir->i_sb, sector); + if (!entries[i].bh) { + error = -EIO; + goto fail; + } + entries[i].start = entries[i].bh->b_data + entries[i].off; + } + return 0; + +fail: + for (i = 0; i < nr_entries; ++i) + if (entries[i].bh) + brelse(entries[i].bh); + return error; +} + +static u16 exfat_filename_hash_cont(struct super_block *sb, + const __le16 *name, u16 hash, size_t len) +{ + while (len) { + u16 c = __le16_to_cpu(exfat_upcase_convert(sb, *name)); + + hash = ((hash << 15) | (hash >> 1)) + (c & 0xff); + hash = ((hash << 15) | (hash >> 1)) + (c >> 8); + --len; + ++name; + } + return hash; +} + +u16 exfat_dir_entries_checksum(struct dir_entry_buffer *entries, u32 nr) +{ + u32 checksum = 0; + + if (nr) { + checksum = exfat_direntry_checksum(entries->start, + checksum, true); + --nr; + ++entries; + } + while (nr) { + checksum = exfat_direntry_checksum(entries->start, + checksum, false); + --nr; + ++entries; + } + return checksum; +} + +/* + * setup exfat_filedir_entry and exfat_stream_extension_entry for a + * new entry, with attribute attrs, and named name. + */ +static void exfat_fill_dir_entries(struct super_block *sb, + struct dir_entry_buffer *entries, + size_t nr_entries, u8 attrs, + __le16 *name, int name_length) +{ + struct exfat_filedir_entry *efd; + struct exfat_stream_extension_entry *esx; + int i; + u16 name_hash; + u16 checksum; + struct timespec ts = current_kernel_time(); + + efd = entries[0].start; + esx = entries[1].start; + + /* + * fill exfat filedir entry + */ + memset(efd, 0, sizeof (*efd)); + efd->type = E_EXFAT_FILEDIR; + efd->secondary_count = nr_entries - 1; + efd->set_checksum = 0; + efd->attributes = __cpu_to_le16(attrs); + + /* + * update file directory entry times + */ + efd = entries[0].start; + exfat_write_time(EXFAT_SB(sb), &ts, &efd->create, &efd->create_10ms, + &efd->create_tz_offset); + efd->modified = efd->accessed = efd->create; + efd->modified_10ms = efd->create_10ms; + efd->accessed_tz_offset = efd->modified_tz_offset = + efd->create_tz_offset; + + /* + * fill exfat stream extension entry + */ + memset(esx, 0, sizeof (*esx)); + esx->type = E_EXFAT_STREAM_EXT; + esx->flags = EXFAT_I_ALLOC_POSSIBLE; + esx->first_cluster = __cpu_to_le32(0); + esx->data_length = __cpu_to_le64(0); + esx->valid_data_length = __cpu_to_le64(0); + esx->name_length = name_length; + + /* + * fill name fragments. + */ + name_hash = 0; + for (i = 0; i < nr_entries - 2; ++i, name_length -= 15) { + struct exfat_filename_entry *efn = entries[i + 2].start; + int len = 15; + + if (name_length < 15) + len = name_length; + + memset(efn, 0, sizeof (*efn)); + efn->type = E_EXFAT_FILENAME; + memcpy(efn->name_frag, name + i * 15, len * sizeof (__le16)); + name_hash = exfat_filename_hash_cont(sb, efn->name_frag, + name_hash, len); + } + esx->name_hash = __cpu_to_le16(name_hash); + + checksum = exfat_dir_entries_checksum(entries, nr_entries); + efd->set_checksum = __cpu_to_le16(checksum); +} + +/* + * mark all buffer heads in the entries array as dirty. optionally + * sync them if required. + */ +void exfat_dirty_dir_entries(struct dir_entry_buffer *entries, + size_t nr_entries, bool sync) +{ + size_t i; + + for (i = 0; i < nr_entries; ++i) { + mark_buffer_dirty(entries[i].bh); + if (sync) + sync_dirty_buffer(entries[i].bh); + brelse(entries[i].bh); + } +} + +/* + * cleanup all buffer heads in entries. + */ +static void exfat_cleanup_dir_entries(struct dir_entry_buffer *entries, + size_t nr_entries) +{ + size_t i; + + for (i = 0; i < nr_entries; ++i) + brelse(entries[i].bh); +} + +/* + * create an inode + */ +static int __exfat_inode_create(struct inode *dir, struct dentry *dentry, + umode_t mode, bool is_dir) +{ + int nr_entries; + struct dir_entry_buffer entries[19]; + struct inode *new; + struct exfat_iloc iloc; + int error; + u8 attr = 0; + __le16 *utf16_name; + int utf16_name_length; + + if (is_dir) + attr |= E_EXFAT_ATTR_DIRECTORY; + + exfat_lock_super(dir->i_sb); + + utf16_name = __getname(); + if (!utf16_name) { + error = -ENOMEM; + goto unlock_super; + } + + utf16_name_length = utf8s_to_utf16s(dentry->d_name.name, + dentry->d_name.len, + UTF16_LITTLE_ENDIAN, utf16_name, + 255 + 2); + if (utf16_name_length < 0) { + error = utf16_name_length; + goto putname; + } + if (utf16_name_length > 255) { + error = -ENAMETOOLONG; + goto putname; + } + + + nr_entries = 2 + DIV_ROUND_UP(utf16_name_length, 15); + if (nr_entries > 19) { + error = -ENAMETOOLONG; + goto putname; + } + + error = exfat_find_dir_iloc(dir, nr_entries, &iloc); + if (error < 0) + goto putname; + + error = exfat_get_dir_entry_buffers(dir, &iloc, entries, nr_entries); + if (error) + goto putname; + exfat_fill_dir_entries(dir->i_sb, entries, nr_entries, attr, + utf16_name, utf16_name_length); + + /* + * create an inode with it. + */ + error = -ENOMEM; + new = exfat_populate_inode(dir->i_sb, entries[0].start, + entries[1].start, &iloc); + if (!new) + goto cleanup; + inc_nlink(dir); + d_instantiate(dentry, new); + + /* + * update directory atime / ctime. + */ + dir->i_atime = dir->i_mtime = current_time(dir); + if (IS_DIRSYNC(dir)) + __exfat_write_inode(dir, true); + else + mark_inode_dirty(dir); + + /* + * write to disk + */ + exfat_dirty_dir_entries(entries, nr_entries, false); + __putname(utf16_name); + exfat_unlock_super(dir->i_sb); + return 0; + +cleanup: + exfat_cleanup_dir_entries(entries, nr_entries); +putname: + __putname(utf16_name); +unlock_super: + exfat_unlock_super(dir->i_sb); + return error; +} + +int exfat_inode_create(struct inode *dir, struct dentry *dentry, umode_t mode, + bool excl) +{ + return __exfat_inode_create(dir, dentry, mode, false); +} + +int exfat_inode_mkdir(struct inode *dir, struct dentry *dentry, umode_t mode) +{ + return __exfat_inode_create(dir, dentry, mode, true); +} + +/* + * inode unlink: find all direntry buffers and clear seventh bit of + * the entry type to mark the as unused. + */ +static int __exfat_inode_unlink(struct inode *dir, struct dentry *dentry) +{ + struct inode *inode = dentry->d_inode; + struct exfat_inode_info *info = EXFAT_I(inode); + struct dir_entry_buffer entries[info->iloc.nr_secondary]; + int error; + u32 i; + + error = exfat_get_dir_entry_buffers(inode, &info->iloc, + entries, info->iloc.nr_secondary); + if (error) + return error; + + for (i = 0; i < info->iloc.nr_secondary; ++i) { + u8 *type = entries[i].start; + + *type &= 0x7f; + } + + drop_nlink(dir); + clear_nlink(inode); + inode->i_mtime = inode->i_atime = current_time(inode); + + /* + * update atime & mtime for parent directory. + */ + dir->i_mtime = dir->i_atime = current_time(dir); + if (IS_DIRSYNC(dir)) + __exfat_write_inode(dir, true); + else + mark_inode_dirty(dir); + + exfat_dirty_dir_entries(entries, info->iloc.nr_secondary, false); + exfat_remove_inode_hash(inode); + return 0; +} + +int exfat_inode_unlink(struct inode *dir, struct dentry *dentry) +{ + int ret; + + exfat_lock_super(dir->i_sb); + ret = __exfat_inode_unlink(dir, dentry); + exfat_unlock_super(dir->i_sb); + return ret; +} + +/* + * inode rmdir: check that links is not greater than 2 (meaning that + * the directory is empty) and invoke unlink. + */ +static int __exfat_inode_rmdir(struct inode *dir, struct dentry *dentry) +{ + struct inode *inode = dentry->d_inode; + + if (inode->i_nlink > 2) + return -ENOTEMPTY; + + return __exfat_inode_unlink(dir, dentry); +} + +int exfat_inode_rmdir(struct inode *dir, struct dentry *dentry) +{ + int ret; + + exfat_lock_super(dir->i_sb); + ret = __exfat_inode_rmdir(dir, dentry); + exfat_unlock_super(dir->i_sb); + return ret; +} + +int exfat_rename(struct inode *old_dir, struct dentry *old_dentry, + struct inode *new_dir, struct dentry *new_dentry, + unsigned int flags) +{ + struct inode *old_inode = old_dentry->d_inode; + struct inode *new_inode = new_dentry->d_inode; + int new_nr_entries; + int error = 0; + struct exfat_iloc new_iloc; + struct exfat_inode_info *old_info = EXFAT_I(old_inode); + struct dir_entry_buffer old_buffers[old_info->iloc.nr_secondary]; + struct dir_entry_buffer new_buffers[19]; + struct exfat_filedir_entry *efd; + struct exfat_stream_extension_entry *esx; + int name_length; + __le16 *name; + u16 name_hash; + int i; + + if (flags & ~RENAME_NOREPLACE) + return -EINVAL; + + exfat_lock_super(new_dir->i_sb); + + /* + * convert new name to utf16 + */ + name = __getname(); + if (!name) { + error = -ENOMEM; + goto unlock_super; + } + name_length = utf8s_to_utf16s(new_dentry->d_name.name, + new_dentry->d_name.len, + UTF16_LITTLE_ENDIAN, name, 255 + 2); + + if (name_length > 255) { + error = -ENAMETOOLONG; + goto err_putname; + } + if (name_length < 0) { + error = name_length; + goto err_putname; + } + + new_nr_entries = 2 + DIV_ROUND_UP(name_length, 15); + + /* + * find space for new entry + */ + error = exfat_find_dir_iloc(new_dir, new_nr_entries, &new_iloc); + if (error < 0) + goto err_putname; + + /* + * get buffers for old and new entries. + */ + error = exfat_get_dir_entry_buffers(old_dir, &old_info->iloc, + old_buffers, old_info->iloc.nr_secondary); + if (error < 0) + goto err_putname; + + error = exfat_get_dir_entry_buffers(new_dir, &new_iloc, new_buffers, + new_nr_entries); + if (error < 0) + goto err_cleanup_old_buffers; + + + /* + * remove new inode, if it exists. + */ + if (new_inode) { + if (S_ISDIR(new_inode->i_mode)) + error = __exfat_inode_rmdir(new_dir, new_dentry); + else + error = __exfat_inode_unlink(new_dir, new_dentry); + if (error < 0) + goto err_cleanup_new_buffers; + } + + /* + * move old esd to new esd (and ditto for esx). + */ + efd = new_buffers[0].start; + esx = new_buffers[1].start; + memcpy(efd, old_buffers[0].start, sizeof (*efd)); + memcpy(esx, old_buffers[1].start, sizeof (*esx)); + + efd->secondary_count = new_nr_entries - 1; + + /* + * patch new name after that. + */ + esx->name_length = __cpu_to_le16(name_length); + + /* + * fill name fragments. + */ + name_hash = 0; + for (i = 0; i < new_nr_entries - 2; ++i, name_length -= 15) { + struct exfat_filename_entry *efn = new_buffers[i + 2].start; + int len = 15; + + if (name_length < 15) + len = name_length; + + memset(efn, 0, sizeof (*efn)); + efn->type = E_EXFAT_FILENAME; + memcpy(efn->name_frag, name + i * 15, len * sizeof (__le16)); + name_hash = exfat_filename_hash_cont(new_dir->i_sb, + efn->name_frag, + name_hash, len); + } + __putname(name); + esx->name_hash = __cpu_to_le16(name_hash); + efd->set_checksum = exfat_dir_entries_checksum(new_buffers, + new_nr_entries); + efd->set_checksum = __cpu_to_le16(efd->set_checksum); + + /* + * mark old buffer entries as unused. + */ + for (i = 0; i < old_info->iloc.nr_secondary; ++i) + *((u8*)old_buffers[i].start) &= 0x7f; + + /* + * dirty old & new entries buffers. + */ + exfat_dirty_dir_entries(new_buffers, new_nr_entries, false); + exfat_dirty_dir_entries(old_buffers, old_info->iloc.nr_secondary, + false); + + /* + * update links if new_dir and old_dir are differents. + */ + if (new_dir != old_dir) { + drop_nlink(old_dir); + inc_nlink(new_dir); + } + + /* + * make old inode use the new iloc, and update sb inode hash. + */ + exfat_remove_inode_hash(old_inode); + old_info->iloc = new_iloc; + exfat_insert_inode_hash(old_inode); + + /* + * update new dir & old dir mtime/atime + */ + if (new_dir == old_dir) { + new_dir->i_mtime = new_dir->i_atime = current_time(new_dir); + if (IS_DIRSYNC(new_dir)) + __exfat_write_inode(new_dir, true); + else + mark_inode_dirty(new_dir); + } else { + new_dir->i_mtime = new_dir->i_atime = + old_dir->i_mtime = old_dir->i_atime = + current_time(old_dir); + if (IS_DIRSYNC(new_dir)) { + __exfat_write_inode(new_dir, true); + __exfat_write_inode(old_dir, true); + } else { + mark_inode_dirty(new_dir); + mark_inode_dirty(old_dir); + } + } + + exfat_unlock_super(new_dir->i_sb); + return 0; + +err_cleanup_new_buffers: + exfat_cleanup_dir_entries(new_buffers, new_nr_entries); +err_cleanup_old_buffers: + exfat_cleanup_dir_entries(old_buffers, old_info->iloc.nr_secondary); +err_putname: + __putname(name); +unlock_super: + exfat_unlock_super(new_dir->i_sb); + return error; +} diff -Nruw linux-4.14.127-fbx/fs/exfat./read-write.c linux-4.14.127-fbx/fs/exfat/read-write.c --- linux-4.14.127-fbx/fs/exfat./read-write.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/fs/exfat/read-write.c 2019-01-14 15:16:37.082082405 +0100 @@ -0,0 +1,150 @@ +/* + * read-write.c for exfat + * Created by on Wed Jul 31 16:37:51 2013 + */ + +#include +#include +#include +#include +#include + +#include "exfat.h" +#include "exfat_fs.h" + +/* + * map file sector to disk sector. + */ +static int exfat_bmap(struct inode *inode, sector_t fsect, sector_t *dsect) +{ + struct exfat_sb_info *sbi = EXFAT_SB(inode->i_sb); + struct exfat_inode_info *info = EXFAT_I(inode); + u32 cluster_nr = fsect >> (sbi->clusterbits - sbi->sectorbits); + u32 cluster; + unsigned int offset = fsect & (sbi->sectors_per_cluster - 1); + + if (info->flags & EXFAT_I_FAT_INVALID) + cluster = info->first_cluster + cluster_nr; + else { + int error; + + error = exfat_get_fat_cluster(inode, cluster_nr, &cluster); + if (error) + return error; + } + + *dsect = exfat_cluster_sector(sbi, cluster) + offset; + return 0; +} + +static int exfat_get_block(struct inode *inode, sector_t block, + struct buffer_head *bh, int create) +{ + struct exfat_sb_info *sbi = EXFAT_SB(inode->i_sb); + struct exfat_inode_info *info = EXFAT_I(inode); + sector_t last_block; + unsigned int offset; + sector_t dblock; + int error; + + last_block = (i_size_read(inode) + sbi->sectorsize - 1) >> + sbi->sectorbits; + offset = block & (sbi->sectors_per_cluster - 1); + + if (!create && block >= last_block) + return 0; + + if (create && block >= last_block && offset == 0) { + u32 hint, cluster; + + /* + * request for first sector in a cluster immediate to + * the last allocated cluster of the file: must + * allocate a new clluster. + */ + error = exfat_get_cluster_hint(inode, &hint); + if (error) + return error; + + error = exfat_alloc_clusters(inode, hint, &cluster, 1); + if (error) + return error; + } + + error = exfat_bmap(inode, block, &dblock); + if (error) + return error; + + if (create && block >= last_block) { + /* + * currently in create mode: we need to update + * mmu_private. + */ + info->mmu_private += sbi->sectorsize; + set_buffer_new(bh); + } + map_bh(bh, inode->i_sb, dblock); + return 0; +} + +int exfat_readpage(struct file *file, struct page *page) +{ + return mpage_readpage(page, exfat_get_block); +} + +int exfat_readpages(struct file *file, struct address_space *mapping, + struct list_head *pages, unsigned nr_pages) +{ + return mpage_readpages(mapping, pages, nr_pages, exfat_get_block); +} + +static int exfat_write_error(struct inode *inode, loff_t to) +{ + if (to > inode->i_size) { + truncate_pagecache(inode, to); + exfat_truncate_blocks(inode, inode->i_size); + } + return 0; +} + +int exfat_write_begin(struct file *file, struct address_space *mapping, + loff_t pos, unsigned len, unsigned flags, + struct page **pagep, void **fsdata) +{ + struct inode *inode = mapping->host; + int error; + + *pagep = NULL; + error = cont_write_begin(file, mapping, pos, len, flags, pagep, fsdata, + exfat_get_block, &EXFAT_I(inode)->mmu_private); + + if (error) + exfat_write_error(inode, pos + len); + return error; +} + +int exfat_write_end(struct file *file, struct address_space *mapping, + loff_t pos, unsigned len, unsigned copied, + struct page *page, void *fsdata) +{ + struct inode *inode = mapping->host; + int error; + + error = generic_write_end(file, mapping, pos, len, copied, page, + fsdata); + + if (error < len) + exfat_write_error(inode, pos + len); + return error; +} + +int exfat_writepage(struct page *page, struct writeback_control *wbc) +{ + return block_write_full_page(page, exfat_get_block, wbc); +} + +int exfat_writepages(struct address_space *mapping, + struct writeback_control *wbc) +{ + return mpage_writepages(mapping, wbc, exfat_get_block); +} diff -Nruw linux-4.14.127-fbx/fs/exfat./super.c linux-4.14.127-fbx/fs/exfat/super.c --- linux-4.14.127-fbx/fs/exfat./super.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/fs/exfat/super.c 2019-02-15 14:29:43.726663128 +0100 @@ -0,0 +1,741 @@ +/* + * super.c<2> for exfat + * Created by on Tue Jul 23 12:33:53 2013 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "exfat_fs.h" +#include "exfat.h" + + +#define PFX "exFAT: " + +static void exfat_put_super(struct super_block *sb); +static int exfat_statfs(struct dentry *dentry, struct kstatfs *kstat); +static int exfat_show_options(struct seq_file *m, struct dentry *root); +static int exfat_remount(struct super_block *sb, int *flags, char *opts); + +static const struct super_operations exfat_super_ops = { + .alloc_inode = exfat_alloc_inode, + .destroy_inode = exfat_destroy_inode, + .drop_inode = exfat_drop_inode, + .evict_inode = exfat_evict_inode, + .write_inode = exfat_write_inode, + .statfs = exfat_statfs, + .put_super = exfat_put_super, + .show_options = exfat_show_options, + .remount_fs = exfat_remount, +}; + +const struct file_operations exfat_dir_operations = { + .llseek = generic_file_llseek, + .read = generic_read_dir, + .iterate = exfat_iterate, + .unlocked_ioctl = exfat_ioctl, +}; + +const struct file_operations exfat_file_operations = { + .llseek = generic_file_llseek, + .read_iter = generic_file_read_iter, + .write_iter = generic_file_write_iter, + .mmap = generic_file_mmap, + .splice_read = generic_file_splice_read, + .unlocked_ioctl = exfat_ioctl, + .fsync = generic_file_fsync, +}; + +const struct inode_operations exfat_dir_inode_operations = +{ + .create = exfat_inode_create, + .mkdir = exfat_inode_mkdir, + .lookup = exfat_inode_lookup, + .rmdir = exfat_inode_rmdir, + .unlink = exfat_inode_unlink, + .rename = exfat_rename, + .setattr = exfat_setattr, + .getattr = exfat_getattr, +}; + +const struct inode_operations exfat_file_inode_operations = { + .setattr = exfat_setattr, + .getattr = exfat_getattr, +}; + +const struct address_space_operations exfat_address_space_operations = { + .readpage = exfat_readpage, + .readpages = exfat_readpages, + .write_begin = exfat_write_begin, + .write_end = exfat_write_end, + .writepage = exfat_writepage, + .writepages = exfat_writepages, +}; + +void exfat_msg(struct super_block *sb, const char *prefix, + const char *fmt, ...) +{ + struct va_format vaf; + va_list args; + + va_start(args, fmt); + vaf.fmt = fmt; + vaf.va = &args; + printk("%sexFAT-fs (%s): %pV\n", prefix, sb->s_id, &vaf); + va_end(args); +} + +void exfat_fs_error(struct super_block *sb, const char *fmt, ...) +{ + struct exfat_sb_info *sbi = EXFAT_SB(sb); + struct va_format vaf; + va_list args; + + va_start(args, fmt); + vaf.fmt = fmt; + vaf.va = &args; + exfat_msg(sb, KERN_ERR, "error: %pV", &vaf); + va_end(args); + + if (sbi->options.error_action == EXFAT_ERROR_ACTION_REMOUNT_RO && + !(sb->s_flags & MS_RDONLY)) { + sb->s_flags |= MS_RDONLY; + exfat_msg(sb, KERN_ERR, "remounted read-only due to fs error."); + } else if (sbi->options.error_action == EXFAT_ERROR_ACTION_PANIC) + panic("exFAT-fs (%s): panic due fs error.\n", sb->s_id); +} + +/* + * process checksum on buffer head. first indicates if the special + * treatment of the first sector needs to be done or not. + * + * first sector can be changed (volume flags, and heap use percent), + * those fields are excluded from the checksum to allow updating + * without recalculating the checksum. + */ +static u32 exfat_sb_checksum_process(struct buffer_head *bh, u32 checksum, + unsigned int size, + bool first) +{ + unsigned int i; + + for (i = 0; i < size; ++i) { + if (first && (i == 106 || i == 107 || i == 112)) + continue ; + checksum = ((checksum << 31) | (checksum >> 1)) + + (unsigned char)bh->b_data[i]; + } + return checksum; +} + +static int exfat_check_sb_checksum(struct super_block *sb) +{ + struct exfat_sb_info *sbi = EXFAT_SB(sb); + u32 checksum; + int i; + int err; + struct buffer_head *bh[EXFAT_CHECKSUM_SECTORS + 1]; + + /* + * fetch needed sectors, reuse first sector from sbi. + */ + err = -ENOMEM; + memset(bh, 0, sizeof (struct buffer_head*) * + (EXFAT_CHECKSUM_SECTORS + 1)); + bh[0] = sbi->sb_bh; + for (i = 1; i < EXFAT_CHECKSUM_SECTORS + 1; ++i) { + bh[i] = sb_bread(sb, i); + if (!bh[i]) + goto out; + } + + /* + * calculate checksum. + */ + checksum = exfat_sb_checksum_process(bh[0], 0, sbi->sectorsize, true); + for (i = 1; i < EXFAT_CHECKSUM_SECTORS; ++i) { + checksum = exfat_sb_checksum_process(bh[i], checksum, + sbi->sectorsize, false); + } + + /* + * compare with the checksum sector. + */ + err = -EINVAL; + for (i = 0; i < sbi->sectorsize; i += sizeof (u32)) { + __le32 val = *(u32*)(bh[EXFAT_CHECKSUM_SECTORS]->b_data + i); + + if (__le32_to_cpu(val) != checksum) { + exfat_msg(sb, KERN_INFO, "at offset %i, checksum " + "%08x != %08x", i, __le32_to_cpu(val), checksum); + goto out; + } + } + err = 0; + +out: + for (i = 1; i < EXFAT_CHECKSUM_SECTORS; ++i) + if (bh[i]) + brelse(bh[i]); + return err; +} + +static int exfat_check_sb(struct super_block *sb) +{ + struct exfat_sb_info *sbi = EXFAT_SB(sb); + struct exfat_vbr *vbr = sbi->vbr; + u16 fs_rev; + u16 flags; + int active_fat; + u16 num_fats; + + if (memcmp(vbr->jump, "\xeb\x76\x90", sizeof (vbr->jump))) { + exfat_msg(sb, KERN_INFO, "invalid jump field in vbr."); + return -EINVAL; + } + + if (memcmp(vbr->fsname, "EXFAT ", 8)) { + exfat_msg(sb, KERN_INFO, "invalid fsname field in vbr: %s.", + vbr->fsname); + return -EINVAL; + } + + fs_rev = __le16_to_cpu(vbr->fs_rev); + if (fs_rev != 0x0100) { + exfat_msg(sb, KERN_INFO, "filesystem version invalid: " + "have 0x%04x, need 0x0100", fs_rev); + return -EINVAL; + } + + flags = __le16_to_cpu(vbr->volume_flags); + active_fat = exfat_active_fat(flags); + if (active_fat != 0) { + exfat_msg(sb, KERN_INFO, "filesystems with active fat > 0 are " + "not supported."); + return -EINVAL; + } + + if (flags & EXFAT_FLAG_MEDIA_FAILURE) + exfat_msg(sb, KERN_WARNING, "filesystem had media failure(s)"); + + /* + * bytes per sectors are on the range 2^9 - 2^12 (512 - 4096) + */ + if (vbr->bytes_per_sector < 9 || vbr->bytes_per_sector > 12) { + exfat_msg(sb, KERN_ERR, "invalid byte per sectors: %u", + (1 << vbr->bytes_per_sector)); + return -EINVAL; + } + + /* + * sectors per cluster can be as low as 0, and must not result + * in a cluster size higher than 32MB (byte_per_sector + + * sectors_per_cluster must not be creater than 25) + */ + if (vbr->bytes_per_sector + vbr->sectors_per_cluster > 25) { + exfat_msg(sb, KERN_ERR, "invalid cluster size: %u", + 1 << (vbr->bytes_per_sector + vbr->sectors_per_cluster)); + return -EINVAL; + } + + num_fats = __le16_to_cpu(vbr->fat_num); + if (num_fats == 0) { + exfat_msg(sb, KERN_ERR, "superblock reports no FAT."); + return -EINVAL; + } + if (num_fats > 1) { + exfat_msg(sb, KERN_ERR, "TexFAT is not supported."); + return -EINVAL; + } + + if (memcmp(vbr->boot_sig, "\x55\xaa", 2)) { + exfat_msg(sb, KERN_ERR, "invalid end boot signature: %02x%02x.", + vbr->boot_sig[0], vbr->boot_sig[1]); + return -EINVAL; + } + + return 0; +} + +static int exfat_fill_root(struct super_block *sb, struct inode *root) +{ + struct exfat_sb_info *sbi = EXFAT_SB(sb); + u32 nclust; + u32 dummy; + loff_t links; + + root->i_ino = EXFAT_ROOT_INO; + root->i_version = 1; + EXFAT_I(root)->first_cluster = + __le32_to_cpu(sbi->root_dir_cluster); + EXFAT_I(root)->attributes = E_EXFAT_ATTR_DIRECTORY; + + root->i_uid = sbi->options.uid; + root->i_gid = sbi->options.gid; + + root->i_mode = exfat_make_mode(sbi, S_IRWXUGO, E_EXFAT_ATTR_DIRECTORY); + root->i_version++; + root->i_generation = 0; + + root->i_op = &exfat_dir_inode_operations; + root->i_fop = &exfat_dir_operations; + + /* + * root inode cannot use bitmap. + */ + EXFAT_I(root)->flags = EXFAT_I_ALLOC_POSSIBLE; + + /* + * set i_size + */ + nclust = 0; + while (__exfat_get_fat_cluster(root, nclust, &dummy, false) == 0) + ++nclust; + root->i_size = nclust << sbi->clusterbits; + root->i_blocks = nclust << (sbi->clusterbits - 9); + EXFAT_I(root)->allocated_clusters = nclust; + + /* + * +2 to account for '.' and '..' + */ + links = exfat_dir_links(root); + if (links < 0) + return links; + set_nlink(root, links + 2); + + root->i_mtime = root->i_atime = root->i_ctime = current_time(root); + + return 0; +} + +static loff_t exfat_file_max_byte(struct exfat_sb_info *sbi) +{ + u32 max_clusters = EXFAT_CLUSTER_LASTVALID - + EXFAT_CLUSTER_FIRSTVALID + 1; + + return (loff_t)max_clusters << sbi->clusterbits; +} + +static int exfat_show_options(struct seq_file *m, struct dentry *root) +{ + struct exfat_sb_info *sbi = EXFAT_SB(root->d_inode->i_sb); + + if (!uid_eq(sbi->options.uid, GLOBAL_ROOT_UID)) + seq_printf(m, ",uid=%u", + from_kuid_munged(&init_user_ns, sbi->options.uid)); + if (!gid_eq(sbi->options.gid, GLOBAL_ROOT_GID)) + seq_printf(m, ",gid=%u", + from_kgid_munged(&init_user_ns, sbi->options.gid)); + + seq_printf(m, ",fmask=%04o", sbi->options.fmask); + seq_printf(m, ",dmask=%04o", sbi->options.dmask); + + if (sbi->options.time_offset_set) + seq_printf(m, ",time_offset=%d", sbi->options.time_offset); + + switch (sbi->options.error_action) { + case EXFAT_ERROR_ACTION_PANIC: + seq_printf(m, ",errors=panic"); + break; + case EXFAT_ERROR_ACTION_REMOUNT_RO: + seq_printf(m, ",errors=remount-ro"); + break; + default: + seq_printf(m, ",errors=continue"); + break; + } + + return 0; +} + +enum { + Opt_exfat_uid, + Opt_exfat_gid, + Opt_exfat_dmask, + Opt_exfat_fmask, + Opt_exfat_time_offset, + Opt_exfat_error_continue, + Opt_exfat_error_remount_ro, + Opt_exfat_error_panic, + Opt_exfat_err, +}; + +static const match_table_t exfat_tokens = { + { Opt_exfat_uid, "uid=%u", }, + { Opt_exfat_gid, "gid=%u", }, + { Opt_exfat_dmask, "dmask=%04o", }, + { Opt_exfat_fmask, "fmask=%04o", }, + { Opt_exfat_time_offset, "time_offset=%d", }, + { Opt_exfat_error_continue, "errors=continue", }, + { Opt_exfat_error_remount_ro, "errors=remount-ro", }, + { Opt_exfat_error_panic, "errors=panic", }, + { Opt_exfat_err, NULL }, +}; + +static int exfat_parse_options(struct super_block *sb, char *opts, int silent) +{ + struct exfat_sb_info *sbi = EXFAT_SB(sb); + char *p; + + sbi->options.uid = current_uid(); + sbi->options.gid = current_gid(); + + sbi->options.dmask = current_umask(); + sbi->options.fmask = current_umask(); + sbi->options.time_offset_set = 0; + sbi->options.error_action = EXFAT_ERROR_ACTION_CONTINUE; + + while (1) { + int token; + substring_t args[MAX_OPT_ARGS]; + unsigned int optval; + + p = strsep(&opts, ","); + if (!p) + break; + token = match_token(p, exfat_tokens, args); + + switch (token) { + case Opt_exfat_uid: + if (match_int(&args[0], &optval)) + return -EINVAL; + sbi->options.uid = make_kuid(current_user_ns(), optval); + break; + + case Opt_exfat_gid: + if (match_int(&args[0], &optval)) + return -EINVAL; + sbi->options.gid = make_kgid(current_user_ns(), optval); + break; + + case Opt_exfat_dmask: + if (match_octal(&args[0], &optval)) + return -EINVAL; + sbi->options.dmask = optval; + break; + + case Opt_exfat_fmask: + if (match_octal(&args[0], &optval)) + return -EINVAL; + sbi->options.fmask = optval; + break; + + case Opt_exfat_time_offset: + if (match_int(&args[0], &optval)) + return -EINVAL; + if (optval < -12 * 60 && optval > 12 * 60) { + if (!silent) + exfat_msg(sb, KERN_INFO, "invalid " + "time_offset value %d: " + "should be between %d and %d", + optval, -12 * 60, 12 * 60); + return -EINVAL; + } + sbi->options.time_offset = optval; + sbi->options.time_offset_set = 1; + break; + + case Opt_exfat_error_continue: + sbi->options.error_action = EXFAT_ERROR_ACTION_CONTINUE; + break; + + case Opt_exfat_error_remount_ro: + sbi->options.error_action = + EXFAT_ERROR_ACTION_REMOUNT_RO; + break; + + case Opt_exfat_error_panic: + sbi->options.error_action = EXFAT_ERROR_ACTION_PANIC; + break; + + default: + if (!silent) + exfat_msg(sb, KERN_INFO, "Unrecognized mount " + "option %s or missing parameter.\n", + p); + return -EINVAL; + } + } + return 0; +} + +static void exfat_set_sb_dirty(struct super_block *sb, bool set, bool force) +{ + struct exfat_sb_info *sbi = EXFAT_SB(sb); + u16 flags; + + /* + * do not change anything if mounted read only and not + * forced. the force case would happen during remount. + */ + if ((sb->s_flags & MS_RDONLY) && !force) + return ; + + if (sbi->dirty) { + if (set) + exfat_msg(sb, KERN_WARNING, "Volume was not cleanly " + "umounted. fsck should probably be needed."); + return ; + } + + flags = __le16_to_cpu(sbi->vbr->volume_flags); + if (set) + flags |= EXFAT_FLAG_DIRTY; + else + flags &= ~EXFAT_FLAG_DIRTY; + sbi->vbr->volume_flags = __cpu_to_le16(flags); + + mark_buffer_dirty(sbi->sb_bh); + sync_dirty_buffer(sbi->sb_bh); +} + +static int exfat_remount(struct super_block *sb, int *flags, char *opts) +{ + int new_rdonly = *flags & MS_RDONLY; + + if (new_rdonly != (sb->s_flags & MS_RDONLY)) { + if (new_rdonly) + exfat_set_sb_dirty(sb, false, false); + else + /* + * sb->s_flag still has MS_RDONLY, so we need + * to force the dirty state + */ + exfat_set_sb_dirty(sb, true, true); + } + return 0; +} + +static int exfat_fill_super(struct super_block *sb, void *data, int silent) +{ + struct exfat_sb_info *sbi = NULL; + int ret = -ENOMEM; + struct inode *root = NULL; + int i; + + sbi = kzalloc(sizeof (*sbi), GFP_KERNEL); + if (!sbi) + return -ENOMEM; + + sb->s_fs_info = sbi; + if (exfat_parse_options(sb, data, silent) < 0) + return -EINVAL; + + mutex_init(&sbi->sb_mutex); + spin_lock_init(&sbi->inode_hash_lock); + + /* + * first block, before we know sector size. + */ + sbi->sb_bh = sb_bread(sb, 0); + if (!sbi->sb_bh) + goto fail; + + sbi->vbr = (struct exfat_vbr*)sbi->sb_bh->b_data; + sb->s_op = &exfat_super_ops; + + + ret = exfat_check_sb(sb); + if (ret) + goto fail; + + /* + * time granularity of FS for use by current_time(inode): in + * nsec so 1000000000 for 1 sec granularity. + */ + sb->s_time_gran = 1000 * 1000 * 1000; + + /* + * vbr seems sane, fill sbi. + */ + sbi->sectorsize = (1 << sbi->vbr->bytes_per_sector); + sbi->clustersize = sbi->sectorsize * + (1 << sbi->vbr->sectors_per_cluster); + + sbi->sectors_per_cluster = sbi->clustersize / sbi->sectorsize; + + sbi->sectorbits = sbi->vbr->bytes_per_sector; + sbi->clusterbits = sbi->vbr->sectors_per_cluster + sbi->sectorbits; + sbi->sectormask = sbi->sectorsize - 1; + sbi->clustermask = sbi->clustersize - 1; + + + sbi->fat_offset = __le32_to_cpu(sbi->vbr->fat_offset); + sbi->fat_length = __le32_to_cpu(sbi->vbr->fat_length); + + sbi->root_dir_cluster = __le32_to_cpu(sbi->vbr->cluster_root_dir); + + sbi->cluster_heap_offset = __le32_to_cpu(sbi->vbr->cluster_heap_offset); + sbi->cluster_count = __le32_to_cpu(sbi->vbr->cluster_count); + + sbi->dirty = !!(__le16_to_cpu(sbi->vbr->volume_flags) & + EXFAT_FLAG_DIRTY); + + /* + * now that we know sector size, reread superblock with + * correct sector size. + */ + ret = -EIO; + if (sb->s_blocksize != sbi->sectorsize) { + if (!sb_set_blocksize(sb, sbi->sectorsize)) { + exfat_msg(sb, KERN_INFO, "bad block size %d.", + sbi->sectorsize); + goto fail; + } + + brelse(sbi->sb_bh); + sbi->vbr = NULL; + + sbi->sb_bh = sb_bread(sb, 0); + if (!sbi->sb_bh) + goto fail; + sbi->vbr = (struct exfat_vbr*)sbi->sb_bh->b_data; + sb->s_fs_info = sbi; + } + + ret = exfat_check_sb_checksum(sb); + if (ret) + goto fail; + + sb->s_maxbytes = exfat_file_max_byte(sbi); + + ret = exfat_init_fat(sb); + if (ret) + goto fail; + + for (i = 0 ; i < EXFAT_HASH_SIZE; ++i) { + INIT_HLIST_HEAD(&sbi->inode_hash[i]); + } + + /* + * create root inode. + */ + root = new_inode(sb); + if (!root) + goto fail; + + exfat_fill_root(sb, root); + + ret = exfat_upcase_init(root); + if (ret) + goto fail_iput; + + ret = exfat_init_bitmap(root); + if (ret) + goto fail_iput; + + + sb->s_root = d_make_root(root); + if (!sb->s_root) + goto fail_iput; + + exfat_set_sb_dirty(sb, true, false); + return 0; + +fail_iput: + iput(root); + +fail: + if (sbi->sb_bh) + brelse(sbi->sb_bh); + if (sbi) + kfree(sbi); + return ret; +} + +static struct dentry *exfat_mount(struct file_system_type *fstype, + int flags, const char *dev_name, void *data) +{ + return mount_bdev(fstype, flags, dev_name, data, exfat_fill_super); +} + +static void exfat_put_super(struct super_block *sb) +{ + struct exfat_sb_info *sbi; + + sbi = EXFAT_SB(sb); + if (sbi) { + exfat_set_sb_dirty(sb, false, false); + exfat_exit_bitmap(sb); + brelse(sbi->sb_bh); + kfree(sbi->upcase_table); + kfree(sbi); + } +} + +static int exfat_statfs(struct dentry *dentry, struct kstatfs *kstat) +{ + struct super_block *sb = dentry->d_inode->i_sb; + struct exfat_sb_info *sbi = EXFAT_SB(sb); + u64 id = huge_encode_dev(sb->s_bdev->bd_dev); + + memset(kstat, 0, sizeof (*kstat)); + + + kstat->f_bsize = sbi->clustersize; + kstat->f_blocks = sbi->cluster_count; + kstat->f_bfree = sbi->free_clusters; + kstat->f_bavail = sbi->free_clusters; + kstat->f_namelen = 255; + kstat->f_fsid.val[0] = (u32)id; + kstat->f_fsid.val[1] = (u32)(id >> 32); + + return 0; +} + +static struct file_system_type exfat_fs_type = { + .owner = THIS_MODULE, + .name = "exfat", + .mount = exfat_mount, + .kill_sb = kill_block_super, + .fs_flags = FS_REQUIRES_DEV, +}; + +static int __init exfat_init(void) +{ + int error; + + /* some sanity check on internal structure sizes */ + BUILD_BUG_ON(sizeof (struct exfat_vbr) != 512); + + BUILD_BUG_ON(sizeof (struct exfat_volume_label_entry) != 0x20); + BUILD_BUG_ON(sizeof (struct exfat_bitmap_entry) != 0x20); + BUILD_BUG_ON(sizeof (struct exfat_upcase_entry) != 0x20); + BUILD_BUG_ON(sizeof (struct exfat_guid_entry) != 0x20); + BUILD_BUG_ON(sizeof (struct exfat_padding_entry) != 0x20); + BUILD_BUG_ON(sizeof (struct exfat_acl_entry) != 0x20); + BUILD_BUG_ON(sizeof (struct exfat_filedir_entry) != 0x20); + BUILD_BUG_ON(sizeof (struct exfat_stream_extension_entry) != 0x20); + BUILD_BUG_ON(sizeof (struct exfat_filename_entry) != 0x20); + + error = exfat_init_inodes(); + if (error) + return error; + + + error = register_filesystem(&exfat_fs_type); + if (error) + exfat_exit_inodes(); + return error; +} + +static void __exit exfat_exit(void) +{ + unregister_filesystem(&exfat_fs_type); + exfat_exit_inodes(); +} + +module_init(exfat_init); +module_exit(exfat_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Nicolas Schichan "); diff -Nruw linux-4.14.127-fbx/fs/exfat./time.c linux-4.14.127-fbx/fs/exfat/time.c --- linux-4.14.127-fbx/fs/exfat./time.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/fs/exfat/time.c 2019-01-14 15:09:09.119950445 +0100 @@ -0,0 +1,126 @@ + +#include +#include + +#include "exfat.h" +#include "exfat_fs.h" + + + +extern struct timezone sys_tz; + +/* + * The epoch of FAT timestamp is 1980. + * : bits : value + * date: 0 - 4: day (1 - 31) + * date: 5 - 8: month (1 - 12) + * date: 9 - 15: year (0 - 127) from 1980 + * time: 0 - 4: sec (0 - 29) 2sec counts + * time: 5 - 10: min (0 - 59) + * time: 11 - 15: hour (0 - 23) + */ +#define SECS_PER_MIN 60 +#define SECS_PER_HOUR (60 * 60) +#define SECS_PER_DAY (SECS_PER_HOUR * 24) +/* days between 1.1.70 and 1.1.80 (2 leap days) */ +#define DAYS_DELTA (365 * 10 + 2) +/* 120 (2100 - 1980) isn't leap year */ +#define YEAR_2100 120 +#define IS_LEAP_YEAR(y) (!((y) & 3) && (y) != YEAR_2100) + +/* Linear day numbers of the respective 1sts in non-leap years. */ +static time_t days_in_year[] = { + /* Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec */ + 0, 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334, 0, 0, 0, +}; + +/* Convert a FAT time/date pair to a UNIX date (seconds since 1 1 70). */ +void exfat_time_2unix(struct timespec *ts, u32 datetime, u8 time_cs, + s8 tz_offset) +{ + u16 date = (datetime >> 16); + u16 time = (datetime & 0xffff); + time_t second, day, leap_day, month, year; + + year = date >> 9; + month = max(1, (date >> 5) & 0xf); + day = max(1, date & 0x1f) - 1; + + if (((tz_offset & (1 << 6)) == 0)) + tz_offset &= ~(1 << 7); + + leap_day = (year + 3) / 4; + if (year > YEAR_2100) /* 2100 isn't leap year */ + leap_day--; + if (IS_LEAP_YEAR(year) && month > 2) + leap_day++; + + second = (time & 0x1f) << 1; + second += ((time >> 5) & 0x3f) * SECS_PER_MIN; + second += (time >> 11) * SECS_PER_HOUR; + second += (year * 365 + leap_day + + days_in_year[month] + day + + DAYS_DELTA) * SECS_PER_DAY; + + second -= tz_offset * 15 * SECS_PER_MIN; + + if (time_cs) { + ts->tv_sec = second + (time_cs / 100); + ts->tv_nsec = (time_cs % 100) * 10000000; + } else { + ts->tv_sec = second; + ts->tv_nsec = 0; + } +} + +/* Convert linear UNIX date to a FAT time/date pair. */ +void exfat_time_2exfat(struct exfat_sb_info *sbi, struct timespec *ts, + u32 *datetime, u8 *time_cs, s8 *tz_offset) +{ + struct tm tm; + u16 time; + u16 date; + int offset; + + if (sbi->options.time_offset_set) { + offset = -sbi->options.time_offset; + } else + offset = sys_tz.tz_minuteswest; + + time_to_tm(ts->tv_sec, -offset * SECS_PER_MIN, &tm); + + /* FAT can only support year between 1980 to 2107 */ + if (tm.tm_year < 1980 - 1900) { + time = 0; + date = cpu_to_le16((0 << 9) | (1 << 5) | 1); + if (time_cs) + *time_cs = 0; + *tz_offset = 0; + return; + } + if (tm.tm_year > 2107 - 1900) { + time = cpu_to_le16((23 << 11) | (59 << 5) | 29); + date = cpu_to_le16((127 << 9) | (12 << 5) | 31); + if (time_cs) + *time_cs = 199; + *tz_offset = 0; + return; + } + + /* from 1900 -> from 1980 */ + tm.tm_year -= 80; + /* 0~11 -> 1~12 */ + tm.tm_mon++; + /* 0~59 -> 0~29(2sec counts) */ + tm.tm_sec >>= 1; + + time = cpu_to_le16(tm.tm_hour << 11 | tm.tm_min << 5 | tm.tm_sec); + date = cpu_to_le16(tm.tm_year << 9 | tm.tm_mon << 5 | tm.tm_mday); + + *datetime = (date << 16) | time; + + if (time_cs) + *time_cs = (ts->tv_sec & 1) * 100 + ts->tv_nsec / 10000000; + *tz_offset = -offset / 15; + *tz_offset |= (1 << 7); +} diff -Nruw linux-4.14.127-fbx/fs/exfat./upcase.c linux-4.14.127-fbx/fs/exfat/upcase.c --- linux-4.14.127-fbx/fs/exfat./upcase.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/fs/exfat/upcase.c 2019-01-14 15:16:37.082082405 +0100 @@ -0,0 +1,137 @@ +/* + * upcase.c for exfat + * Created by on Wed Aug 7 11:51:37 2013 + */ + +#include +#include +#include + +#include "exfat.h" +#include "exfat_fs.h" + +static u32 exfat_calc_upcase_checksum(const u8 *data, u32 checksum, + size_t count) +{ + while (count) { + checksum = ((checksum << 31) | (checksum >> 1)) + *data; + --count; + ++data; + } + return checksum; +} + +static int exfat_load_upcase_table(struct super_block *sb, u32 disk_cluster, + u32 *out_checksum) +{ + struct exfat_sb_info *sbi = EXFAT_SB(sb); + struct buffer_head *bh; + sector_t start, sect, end; + u32 off = 0; + u32 byte_len = sbi->upcase_len * sizeof (__le16); + u32 checksum = 0; + + /* + * up-case table are not fragmented, so sequential cluster + * read will do here. + */ + start = exfat_cluster_sector(sbi, disk_cluster); + end = start + DIV_ROUND_UP(byte_len, + sbi->sectorsize); + for (sect = start; sect < end; ++sect) { + u32 len = sbi->sectorsize; + + if (sect == end - 1) + len = byte_len & sbi->sectormask; + + bh = sb_bread(sb, sect); + if (!bh) { + exfat_msg(sb, KERN_ERR, + "unable to read upcase sector %llu", + (unsigned long long)sect); + return -EIO; + } + memcpy((u8*)sbi->upcase_table + off, bh->b_data, + len); + + checksum = exfat_calc_upcase_checksum(bh->b_data, checksum, + len); + + off += len; + brelse(bh); + } + + BUG_ON(off != byte_len); + *out_checksum = checksum; + return 0; +} + +int exfat_upcase_init(struct inode *root) +{ + struct exfat_sb_info *sbi = EXFAT_SB(root->i_sb); + struct exfat_upcase_entry *upcase; + struct exfat_dir_ctx dctx; + int error; + u64 upcase_length; + u32 checksum; + + /* + * configure directory context and look for an upcase table + * entry. + */ + if (exfat_init_dir_ctx(root, &dctx, 0) < 0) + return -EIO; + + error = -EIO; + upcase = __exfat_dentry_next(&dctx, E_EXFAT_UPCASE_TABLE, 0xff, + true, NULL); + if (!upcase) + goto fail; + + /* + * check upcase table length. we need it to be non-zero, + * ending on a __le16 boundary and provide at most a + * conversion for the whole __le16 space. + */ + upcase_length = __le64_to_cpu(upcase->length); + if (upcase_length == 0 || + upcase_length & (sizeof (__le16) - 1) || + upcase_length > 0xffff * sizeof (__le16)) { + exfat_msg(root->i_sb, KERN_ERR, "invalid upcase length %llu", + (unsigned long long)upcase_length); + goto fail; + } + + /* + * load complete upcase table in memory. + */ + error = -ENOMEM; + sbi->upcase_len = upcase_length / sizeof (__le16); + sbi->upcase_table = kmalloc(upcase_length, GFP_NOFS); + if (!sbi->upcase_table) + goto fail; + + error = exfat_load_upcase_table(root->i_sb, + __le32_to_cpu(upcase->cluster_addr), + &checksum); + if (error) + goto fail; + + if (checksum != __le32_to_cpu(upcase->checksum)) { + exfat_msg(root->i_sb, KERN_INFO, + "upcase table checksum mismatch: have %08x, " + "expect %08x", checksum, + __le32_to_cpu(upcase->checksum)); + error = -EINVAL; + goto fail; + } + + exfat_cleanup_dir_ctx(&dctx); + return 0; + +fail: + if (sbi->upcase_table) + kfree(sbi->upcase_table); + exfat_cleanup_dir_ctx(&dctx); + return error; +} --- /dev/null 2019-09-30 09:50:43.919599165 +0200 +++ linux-4.14.127-fbx/include/linux/fbxatm_dev.h 2019-02-15 14:29:44.442665966 +0100 @@ -0,0 +1,434 @@ +#ifndef LINUX_FBXATM_DEV_H_ +#define LINUX_FBXATM_DEV_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * atm cell helper + */ +#define ATM_CELL_HDR_SIZE 5 + +#define ATM_GET_GFC(h) (((h)[0] & 0xf0) >> 4) +#define ATM_SET_GFC(h,v) do { \ + (h)[0] &= ~0xf0; \ + (h)[0] |= (v) << 4; \ + } while (0) + +#define ATM_GET_VPI(h) ((((h)[0] & 0x0f) << 4) | \ + (((h)[1] & 0xf0) >> 4)) +#define ATM_SET_VPI(h,v) do { \ + (h)[0] &= ~0xf; \ + (h)[1] &= ~0xf0; \ + (h)[0] |= (v) >> 4; \ + (h)[1] |= ((v) & 0xf) << 4; \ + } while (0) + +#define ATM_GET_VCI(h) ((((h)[1] & 0x0f) << 12) | \ + ((h)[2] << 4) | \ + ((((h)[3] & 0xf0) >> 4))) +#define ATM_SET_VCI(h,v) do { \ + (h)[1] &= ~0xf; \ + (h)[3] &= ~0xf0; \ + (h)[1] |= (v) >> 12; \ + (h)[2] = ((v) & 0xff0) >> 4; \ + (h)[3] |= ((v) & 0xf) << 4; \ + } while (0) + + +#define ATM_GET_PT(h) (((h)[3] & 0x0e) >> 1) +#define ATM_SET_PT(h,v) do { \ + (h)[3] &= ~0xe; \ + (h)[3] |= (v) << 1; \ + } while (0) + +#define ATM_GET_CLP(h) (((h)[3] & 0x01)) +#define ATM_SET_CLP(h,v) do { \ + (h)[3] &= ~1; \ + (h)[3] |= (v); \ + } while (0) + +#define ATM_GET_HEC(h) ((h)[4]) +#define ATM_SET_HEC(h,v) do { \ + (h)[4] = (v); \ + } while (0) + + +/* + * OAM definition + */ +#define OAM_VCI_SEG_F4 3 +#define OAM_VCI_END2END_F4 4 + +#define OAM_PTI_SEG_F5 0x4 +#define OAM_PTI_END2END_F5 0x5 + +#define OAM_TYPE_SHIFT 4 +#define OAM_TYPE_MASK (0xf << OAM_TYPE_SHIFT) +#define OAM_TYPE_FAULT_MANAGEMENT 0x1 +#define OAM_TYPE_PERF_MANAGEMENT 0x2 +#define OAM_TYPE_ACTIVATION 0x8 + +#define FUNC_TYPE_SHIFT 0 +#define FUNC_TYPE_MASK (0xf << FUNC_TYPE_SHIFT) +#define FUNC_TYPE_AIS 0x0 +#define FUNC_TYPE_FERF 0x1 +#define FUNC_TYPE_CONT_CHECK 0x4 +#define FUNC_TYPE_OAM_LOOPBACK 0x8 + +struct fbxatm_oam_cell_payload { + u8 cell_hdr[5]; + u8 cell_type; + u8 loopback_indication; + u8 correlation_tag[4]; + u8 loopback_id[16]; + u8 source_id[16]; + u8 reserved[8]; + u8 crc10[2]; +}; + +struct fbxatm_oam_cell { + struct fbxatm_oam_cell_payload payload; + struct list_head next; +}; + +struct fbxatm_oam_ping { + struct fbxatm_oam_ping_req req; + u32 correlation_id; + int replied; + wait_queue_head_t wq; + struct list_head next; +}; + +/* + * vcc/device stats + */ +struct fbxatm_vcc_stats { + unsigned long rx_bytes; + unsigned long tx_bytes; + unsigned long rx_aal5; + unsigned long tx_aal5; +}; + +struct fbxatm_dev_stats { + unsigned long rx_bytes; + unsigned long tx_bytes; + unsigned long rx_aal5; + unsigned long tx_aal5; + unsigned long rx_f4_oam; + unsigned long tx_f4_oam; + unsigned long rx_f5_oam; + unsigned long tx_f5_oam; + unsigned long rx_bad_oam; + unsigned long rx_bad_llid_oam; + unsigned long rx_other_oam; + unsigned long rx_dropped; + unsigned long tx_drop_nolink; +}; + +/* + * vcc user ops + */ +struct fbxatm_vcc_uops { + void (*link_change)(void *cb_data, int link, + unsigned int rx_cell_rate, + unsigned int tx_cell_rate); + void (*rx_pkt)(struct sk_buff *skb, void *cb_data); + void (*tx_done)(void *cb_data); +}; + +/* + * vcc status flags + */ +enum { + FBXATM_VCC_F_FULL = (1 << 0), + + FBXATM_VCC_F_LINK_UP = (1 << 1), +}; + + +/* + * vcc definition + */ +struct fbxatm_dev; + +struct fbxatm_vcc { + unsigned int vpi; + unsigned int vci; + + struct fbxatm_vcc_qos qos; + + struct fbxatm_vcc_stats stats; + + enum fbxatm_vcc_user user; + void *user_priv; + + struct fbxatm_dev *adev; + void *dev_priv; + + spinlock_t user_ops_lock; + const struct fbxatm_vcc_uops *user_ops; + void *user_cb_data; + + unsigned int to_drop_pkt; + + spinlock_t tx_lock; + unsigned long vcc_flags; + + struct list_head next; +}; + +/* + * fbxatm device operation + */ +struct fbxatm_dev_ops { + int (*open)(struct fbxatm_vcc *vcc); + + void (*close)(struct fbxatm_vcc *vcc); + + int (*ioctl)(struct fbxatm_dev *adev, + unsigned int cmd, void __user *arg); + + int (*send)(struct fbxatm_vcc *vcc, struct sk_buff *skb); + + int (*send_oam)(struct fbxatm_dev *adev, + struct fbxatm_oam_cell *cell); + + int (*init_procfs)(struct fbxatm_dev *adev); + void (*release_procfs)(struct fbxatm_dev *adev); + + struct module *owner; +}; + +/* + * device flags + */ +enum { + FBXATM_DEV_F_LINK_UP = (1 << 0), +}; + +/* + * fbxatm device definition + */ +struct fbxatm_dev { + int ifindex; + unsigned long dev_flags; + + unsigned int max_vcc; + unsigned int vci_mask; + unsigned int vpi_mask; + unsigned int max_priority; + unsigned int max_rx_priority; + unsigned int tx_headroom; + + char *name; + + /* unit: b/s */ + unsigned int link_rate_ds; + unsigned int link_rate_us; + + unsigned int link_cell_rate_ds; + unsigned int link_cell_rate_us; + + const struct fbxatm_dev_ops *ops; + + spinlock_t stats_lock; + struct fbxatm_dev_stats stats; + + struct list_head vcc_list; + + struct device dev; + + spinlock_t oam_lock; + struct list_head rx_oam_cells; + unsigned int rx_oam_cells_count; + struct work_struct oam_work; + + struct list_head oam_pending_ping; + u32 oam_correlation_id; + + struct proc_dir_entry *dev_proc_entry; + void *priv; + struct list_head next; +}; + +/* + * API for device drivers + */ +struct fbxatm_dev *fbxatm_alloc_device(int sizeof_priv); + +int fbxatm_register_device(struct fbxatm_dev *adev, + const char *base_name, + const struct fbxatm_dev_ops *ops); + +void fbxatm_free_device(struct fbxatm_dev *adev); + +void fbxatm_dev_set_link_up(struct fbxatm_dev *adev); + +void fbxatm_dev_set_link_down(struct fbxatm_dev *adev); + +int fbxatm_unregister_device(struct fbxatm_dev *adev); + +void fbxatm_netifrx_oam(struct fbxatm_dev *adev, + struct fbxatm_oam_cell *cell); + + +static inline int fbxatm_vcc_link_is_up(struct fbxatm_vcc *vcc) +{ + return test_bit(FBXATM_VCC_F_LINK_UP, &vcc->vcc_flags); +} + +#define FBXATMDEV_ALIGN 4 + +static inline void *fbxatm_dev_priv(struct fbxatm_dev *adev) +{ + return (u8 *)adev + ((sizeof(struct fbxatm_dev) + + (FBXATMDEV_ALIGN - 1)) + & ~(FBXATMDEV_ALIGN - 1)); +} + +/* + * API for FBXATM stack user + */ +struct fbxatm_ioctl { + int (*handler)(struct socket *sock, + unsigned int cmd, void __user *useraddr); + + void (*release)(struct socket *sock); + + struct module *owner; + struct list_head next; +}; + +void fbxatm_set_uops(struct fbxatm_vcc *vcc, + const struct fbxatm_vcc_uops *user_ops, + void *user_cb_data); + +struct fbxatm_vcc * +fbxatm_bind_to_vcc(const struct fbxatm_vcc_id *id, + enum fbxatm_vcc_user user); + +void fbxatm_unbind_vcc(struct fbxatm_vcc *vcc); + + +static inline int fbxatm_vcc_queue_full(struct fbxatm_vcc *vcc) +{ + return test_bit(FBXATM_VCC_F_FULL, &vcc->vcc_flags); +} + +#ifdef CONFIG_FBXATM_STACK +/* + * stack user callback to send data on given vcc + */ +static inline int fbxatm_send(struct fbxatm_vcc *vcc, struct sk_buff *skb) +{ + int ret; + unsigned int len; + + len = skb->len; + + spin_lock_bh(&vcc->tx_lock); + if (!test_bit(FBXATM_VCC_F_LINK_UP, &vcc->vcc_flags)) { + spin_unlock_bh(&vcc->tx_lock); + dev_kfree_skb(skb); + spin_lock(&vcc->adev->stats_lock); + vcc->adev->stats.tx_drop_nolink++; + spin_unlock(&vcc->adev->stats_lock); + return 0; + } + + ret = vcc->adev->ops->send(vcc, skb); + if (!ret) { + vcc->stats.tx_bytes += len; + vcc->stats.tx_aal5++; + } + spin_unlock_bh(&vcc->tx_lock); + + if (!ret) { + spin_lock_bh(&vcc->adev->stats_lock); + vcc->adev->stats.tx_bytes += len; + vcc->adev->stats.tx_aal5++; + spin_unlock_bh(&vcc->adev->stats_lock); + } + return ret; +} + +/* + * device callback when packet comes in + */ +static inline void fbxatm_netifrx(struct fbxatm_vcc *vcc, struct sk_buff *skb) +{ + unsigned int len; + + len = skb->len; + + spin_lock_bh(&vcc->user_ops_lock); + if (!vcc->user_ops) { + spin_unlock_bh(&vcc->user_ops_lock); + dev_kfree_skb(skb); + return; + } + + if (vcc->to_drop_pkt) { + vcc->to_drop_pkt--; + spin_unlock_bh(&vcc->user_ops_lock); + dev_kfree_skb(skb); + return; + } + + vcc->stats.rx_bytes += len; + vcc->stats.rx_aal5++; + + vcc->user_ops->rx_pkt(skb, vcc->user_cb_data); + spin_unlock_bh(&vcc->user_ops_lock); + + spin_lock_bh(&vcc->adev->stats_lock); + vcc->adev->stats.rx_bytes += len; + vcc->adev->stats.rx_aal5++; + spin_unlock_bh(&vcc->adev->stats_lock); +} + +/* + * device callback when tx is done on vcc + */ +static inline void fbxatm_tx_done(struct fbxatm_vcc *vcc) +{ + spin_lock_bh(&vcc->user_ops_lock); + if (vcc->user_ops) + vcc->user_ops->tx_done(vcc->user_cb_data); + spin_unlock_bh(&vcc->user_ops_lock); +} +#else +int fbxatm_send(struct fbxatm_vcc *vcc, struct sk_buff *skb); +void fbxatm_netifrx(struct fbxatm_vcc *vcc, struct sk_buff *skb); +void fbxatm_tx_done(struct fbxatm_vcc *vcc); +#endif + +static inline unsigned int fbxatm_rx_reserve(void) +{ +#ifdef CONFIG_FBXATM_STACK + /* normal stack, no headroom needed */ + return 0; +#else + /* remote stub, we need to send rx skb to another location, + * adding the fbxatm_remote header, an ethernet header (with + * possible vlan) */ + return ALIGN(sizeof (struct fbxatm_remote_hdr) + VLAN_ETH_HLEN, 4); +#endif +} + +void fbxatm_register_ioctl(struct fbxatm_ioctl *ioctl); + +void fbxatm_unregister_ioctl(struct fbxatm_ioctl *ioctl); + +#endif /* !LINUX_FBXATM_DEV_H_ */ --- /dev/null 2019-09-30 09:50:43.919599165 +0200 +++ linux-4.14.127-fbx/include/linux/fbxatm_remote.h 2019-02-15 14:29:44.442665966 +0100 @@ -0,0 +1,216 @@ +#ifndef FBXATM_REMOTE_H_ +#define FBXATM_REMOTE_H_ + +#include +#include +#include + +/* + * fbxatm remote protocol messages + */ +#define ETH_P_FBXATM_REMOTE 0x8844 +#define FBXATM_REMOTE_MAGIC 0xd76f8d2f + +enum fbxatm_remote_flags { + FBXATM_RFLAGS_ACK = (1 << 0), +}; + +enum fbxatm_remote_mtype { + /* driver => stub */ + FBXATM_RMT_CONNECT = 0, + + /* stub => driver */ + FBXATM_RMT_DEV_LINK, + FBXATM_RMT_DEV_RX_OAM, + + /* driver => stub */ + FBXATM_RMT_KEEPALIVE, + FBXATM_RMT_DEV_SEND_OAM, + FBXATM_RMT_VCC_ACTION, + + /* driver => stub */ + FBXATM_RMT_VCC_SEND, + + /* stub => driver */ + FBXATM_RMT_VCC_QEMPTY, + FBXATM_RMT_VCC_RX, +}; + +struct fbxatm_remote_hdr { + u32 magic; + u8 flags; + u8 seq; + u16 len; + u16 sport; + u16 dport; + + u32 session_id; + u32 mtype; +}; + +/* + * sent to destination port 0 + */ +struct fbxatm_remote_connect { + u8 name[32]; + + u16 dev_link_port; + u16 dev_rx_oam_port; +}; + +struct fbxatm_remote_connect_ack { + u16 vcc_action_port; + u16 dev_send_oam_port; + u16 keepalive_port; + u16 pad; + + u32 max_vcc; + u32 vci_mask; + u32 vpi_mask; + u32 max_priority; + u32 max_rx_priority; + + u32 link; + u32 link_rate_ds; + u32 link_rate_us; + u32 link_cell_rate_ds; + u32 link_cell_rate_us; +}; + +/* + * sent on dev_link port + */ +struct fbxatm_remote_dev_link { + u32 link; + u32 link_rate_ds; + u32 link_rate_us; + u32 link_cell_rate_ds; + u32 link_cell_rate_us; +}; + +/* + * sent on vcc_action port + */ +struct fbxatm_remote_vcc_action { + /* 1: open - 0: close */ + u32 action; + + /* + * open args + */ + u16 vcc_rx_port; + u16 vcc_qempty_port; + + /* from vcc id struct */ + u32 vpi; + u32 vci; + + /* from qos struct */ + u32 traffic_class; + u32 max_sdu; + u32 max_buffered_pkt; + u32 priority; + u32 rx_priority; + + /* + * close args + */ + u32 vcc_remote_id; +}; + +struct fbxatm_remote_vcc_action_ack { + u32 ret; + + /* open args ack */ + u32 vcc_remote_id; + u16 vcc_send_port; + u16 pad; +}; + +/* + * sent on vcc_send port + */ +struct fbxatm_remote_vcc_send_ack { + u32 full; +}; + +/* + * pseudo socket layer + */ +struct fbxatm_remote_sock; +struct fbxatm_remote_ctx; + +struct fbxatm_remote_sockaddr { + u16 lport; + u16 dport; + u32 mtype; + int infinite_retry; + int (*deliver)(void *priv, struct sk_buff *skb, + struct sk_buff **ack); + void (*response)(void *priv, struct sk_buff *skb); + void *priv; +}; + +struct sk_buff *fbxatm_remote_alloc_skb(struct fbxatm_remote_ctx *ctx, + unsigned int size); + +unsigned int fbxatm_remote_headroom(struct fbxatm_remote_ctx *ctx); + +void fbxatm_remote_sock_getaddr(struct fbxatm_remote_sock *sock, + struct fbxatm_remote_sockaddr *addr); + +void fbxatm_remote_sock_purge(struct fbxatm_remote_sock *sock); + +int fbxatm_remote_sock_pending(struct fbxatm_remote_sock *sock); + +struct fbxatm_remote_ctx *fbxatm_remote_alloc_ctx(struct net_device *netdev, + u8 *remote_mac, + u32 session_id, + void (*timeout)(void *priv), + void *priv); + +struct fbxatm_remote_sock * +fbxatm_remote_sock_bind(struct fbxatm_remote_ctx *ctx, + struct fbxatm_remote_sockaddr *addr, + int send_ack); + +struct fbxatm_remote_sock * +fbxatm_remote_sock_connect(struct fbxatm_remote_ctx *ctx, + struct fbxatm_remote_sockaddr *addr, + int need_ack); + +int fbxatm_remote_sock_send(struct fbxatm_remote_sock *sock, + struct sk_buff *skb); + +int fbxatm_remote_sock_send_ack(struct fbxatm_remote_sock *sock, + struct sk_buff *skb); + +int fbxatm_remote_sock_send_raw_ack(struct fbxatm_remote_ctx *ctx, + struct net_device *dev, + u8 *remote_mac, + struct fbxatm_remote_hdr *hdr, + struct sk_buff *ack); + +void fbxatm_remote_sock_close(struct fbxatm_remote_sock *sock); + +void fbxatm_remote_set_unknown_cb(void (*cb)(struct net_device *, + struct sk_buff *)); + +void fbxatm_remote_free_ctx(struct fbxatm_remote_ctx *ctx); + +void fbxatm_remote_ctx_set_dead(struct fbxatm_remote_ctx *ctx); + +int fbxatm_remote_init(void); + +void fbxatm_remote_exit(void); + +/* + * platform data for fbxatm_remote driver + */ +struct fbxatm_remote_pdata { + u8 remote_mac[ETH_ALEN]; + char netdev_name[IFNAMSIZ]; + char remote_name[32]; +}; + +#endif /* !FBXATM_REMOTE_H_ */ --- /dev/null 2019-09-30 09:50:43.919599165 +0200 +++ linux-4.14.127-fbx/include/linux/fbxgpio_core.h 2019-01-14 15:16:37.466084144 +0100 @@ -0,0 +1,45 @@ +/* + * fbxgpio.h for linux-freebox + * Created by on Wed Feb 21 22:09:46 2007 + * Freebox SA + */ + +#ifndef FBXGPIO_H +# define FBXGPIO_H + +# include + +/* can change pin direction */ +#define FBXGPIO_PIN_DIR_RW (1 << 0) +#define FBXGPIO_PIN_REVERSE_POL (1 << 1) + +struct fbxgpio_operations { + int (*get_datain)(int gpio); + void (*set_dataout)(int gpio, int val); + int (*get_dataout)(int gpio); + int (*set_direction)(int gpio, int dir); + int (*get_direction)(int gpio); +}; + + +struct fbxgpio_pin { + const struct fbxgpio_operations *ops; + const char *pin_name; + uint32_t flags; + int direction; + int pin_num; + bool claimed; + unsigned int cur_dataout; + struct device *dev; + struct device_node *of_node; +}; + + +#define GPIO_DIR_IN 0x1 +#define GPIO_DIR_OUT 0x0 + +struct fbxgpio_pin *fbxgpio_of_get(struct device_node *np, + const char *propname, + int index); + +#endif /* !FBXGPIO_H */ --- /dev/null 2019-09-30 09:50:43.919599165 +0200 +++ linux-4.14.127-fbx/include/linux/fbxprocfs.h 2019-01-14 15:09:09.471952229 +0100 @@ -0,0 +1,40 @@ +#ifndef FBXPROCFS_H_ +#define FBXPROCFS_H_ + +#include +#include +#include + +struct fbxprocfs_client +{ + const char *dirname; + struct module *owner; + struct proc_dir_entry *dir; + atomic_t refcount; + struct list_head list; +}; + +struct fbxprocfs_desc { + char *name; + unsigned long id; + int (*rfunc)(struct seq_file *, void *); + int (*wfunc)(struct file *, const char *, unsigned long, void *); +}; + +struct fbxprocfs_client *fbxprocfs_add_client(const char *dirname, + struct module *owner); + +int fbxprocfs_remove_client(struct fbxprocfs_client *client); + + +int +fbxprocfs_create_entries(struct fbxprocfs_client *client, + const struct fbxprocfs_desc *ro_desc, + const struct fbxprocfs_desc *rw_desc); + +int +fbxprocfs_remove_entries(struct fbxprocfs_client *client, + const struct fbxprocfs_desc *ro_desc, + const struct fbxprocfs_desc *rw_desc); + +#endif /* FBXPROCFS_H_ */ --- /dev/null 2019-09-30 09:50:43.919599165 +0200 +++ linux-4.14.127-fbx/include/linux/fbxserial.h 2019-02-15 14:29:44.442665966 +0100 @@ -0,0 +1,129 @@ +#ifndef FBXSERIAL_H_ +#define FBXSERIAL_H_ + +#include +#include + +/* + * some part of serial may vary, we use abstract struct to store this, + * data content depends on type. + */ +#define EXTINFO_SIZE 128 +#define EXTINFO_MAX_COUNT 16 + +/* + * extdev desc + */ +#define EXTINFO_TYPE_EXTDEV 1 + +#define EXTDEV_TYPE_BUNDLE 1 +#define EXTDEV_TYPE_MAX 2 + +struct fbx_serial_extinfo { + u32 type; + + union { + /* extdev */ + struct { + u32 type; + u32 model; + char serial[64]; + } extdev; + + /* raw access */ + unsigned char data[EXTINFO_SIZE]; + } u; +} __attribute__ ((packed));; + + +/* + * master serial structure + */ + +#define FBXSERIAL_VERSION 1 + +#define FBXSERIAL_MAGIC 0x2d9521ab + +#define MAC_ADDR_SIZE 6 +#define RANDOM_DATA_SIZE 32 + +/* + * this is the maximum size we accept to check crc32 against, so + * structure may no grow larger than this + */ +#define FBXSERIAL_MAX_SIZE 8192 + +struct fbx_serial { + u32 crc32; + u32 magic; + u32 struct_version; + u32 len; + + /* board serial */ + u16 type; + u8 version; + u8 manufacturer; + u16 year; + u8 week; + u32 number; + u32 flags; + + /* mac address base */ + u8 mac_addr_base[MAC_ADDR_SIZE]; + + /* mac address count */ + u8 mac_count; + + /* random data */ + u8 random_data[RANDOM_DATA_SIZE]; + + /* last update of data (seconds since epoch) */ + u32 last_modified; + + /* count of following extinfo tag */ + u32 extinfo_count; + + /* beginning of extended info */ + struct fbx_serial_extinfo extinfos[EXTINFO_MAX_COUNT]; + +} __attribute__ ((packed)); + + +/* + * default value to use in case magic is wrong (no cksum in that case) + */ +static inline void fbxserial_set_default(struct fbx_serial *s) +{ + memset(s, 0, sizeof (*s)); + s->magic = FBXSERIAL_MAGIC; + s->struct_version = FBXSERIAL_VERSION; + s->len = sizeof (*s); + s->manufacturer = '_'; + memcpy(s->mac_addr_base, "\x00\x07\xCB\x00\x00\xFD", 6); + s->mac_count = 1; +} + +void +fbxserialinfo_get_random(unsigned char *data, unsigned int len); + +const void * +fbxserialinfo_get_mac_addr(unsigned int index); + +int +fbxserialinfo_read(const void *data, struct fbx_serial *out); + +struct fbx_serial *fbxserialinfo_get(void); + +/* + * implemented in board specific code + */ +#ifdef CONFIG_ARCH_HAS_FBXSERIAL +extern const struct fbx_serial *arch_get_fbxserial(void); +#else +static inline const struct fbx_serial *arch_get_fbxserial(void) +{ + return NULL; +} +#endif + +#endif /* FBXSERIAL_H_ */ --- /dev/null 2019-09-30 09:50:43.919599165 +0200 +++ linux-4.14.127-fbx/include/linux/phy/phy-utmi-cp110.h 2019-02-15 14:29:44.582666521 +0100 @@ -0,0 +1,16 @@ +/* + * phy-utmi-cp110.h for cp110-utmi + * Created by on Tue Jul 25 15:21:59 2017 + */ + +#ifndef __LINUX_PHY_PHY_UTMI_CP110_H +# define __LINUX_PHY_PHY_UTMI_CP110_H + +enum utmi_cp110_mode { + UTMI_PHY_USB2_HOST, + UTMI_PHY_USB2_DEVICE, + + UTMI_PHY_MAX, +}; + +#endif /* !__LINUX_PHY_PHY_UTMI_CP110_H */ --- /dev/null 2019-09-30 09:50:43.919599165 +0200 +++ linux-4.14.127-fbx/include/linux/smsc_cap1066.h 2019-02-15 14:29:44.630666711 +0100 @@ -0,0 +1,12 @@ +#ifndef SMSC_CAP1066_H_ +#define SMSC_CAP1066_H_ + +#define CAP1066_MAX_BTNS 6 + +struct smsc_cap1066_pdata { + u32 key_map[CAP1066_MAX_BTNS]; + unsigned int irq_gpio; + bool has_irq_gpio; +}; + +#endif /* ! SMSC_CAP1066_H_ */ --- /dev/null 2019-09-30 09:50:43.919599165 +0200 +++ linux-4.14.127-fbx/include/net/ip6_ffn.h 2019-02-15 14:29:44.690666949 +0100 @@ -0,0 +1,53 @@ +#ifndef IP6_FFN_H_ +#define IP6_FFN_H_ + +#include +#include +#include +#include + +struct ffn6_data { + u32 new_sip[4]; + u32 new_dip[4]; + + u16 new_sport; + u16 new_dport; + __sum16 adjustment; + u8 new_tos; + u32 new_skb_prio; + u32 new_mark; + + u32 force_skb_prio : 1; + u32 alter : 1; + u32 tos_change : 1; + struct dst_entry *dst; + struct nf_conn *ct; + enum ip_conntrack_info ctinfo; + + void (*priv_destructor)(void *); + u32 ffn_priv_area[8]; +}; + +struct ffn6_lookup_entry { + u32 sip[4]; + u32 dip[4]; + u16 sport; + u16 dport; + u8 protocol; + u8 added_when; +#ifdef CONFIG_IPV6_FFN_PROCFS + uint64_t forwarded_bytes; + uint32_t forwarded_packets; +#endif + struct list_head next; + struct ffn6_data manip; + struct list_head all_next; +}; + +extern spinlock_t ffn6_lock; +struct ffn6_lookup_entry *__ffn6_get(const u32 *sip, + const u32 *dip, + u16 sport, u16 dport, + int is_tcp); + +#endif /* ! IP6_FFN_H_*/ --- /dev/null 2019-09-30 09:50:43.919599165 +0200 +++ linux-4.14.127-fbx/include/net/ip_ffn.h 2019-02-15 14:29:44.694666965 +0100 @@ -0,0 +1,51 @@ +#ifndef IP_FFN_H_ +#define IP_FFN_H_ + +#include +#include +#include +#include + +struct ffn_data { + u32 new_sip; + u32 new_dip; + u16 new_sport; + u16 new_dport; + u8 new_tos; + u8 force_skb_prio : 1; + u8 alter : 1; + u8 tos_change : 1; + __sum16 ip_adjustment; + __sum16 l4_adjustment; + unsigned int new_skb_prio; + u32 new_mark; + struct dst_entry *dst; + struct nf_conn *ct; + enum ip_conntrack_info ctinfo; + + void (*priv_destructor)(void *); + u32 ffn_priv_area[8]; +}; + +struct ffn_lookup_entry { + int added_when; + u32 sip; + u32 dip; + u16 sport; + u16 dport; + u8 protocol; +#ifdef CONFIG_IP_FFN_PROCFS + uint64_t forwarded_bytes; + uint32_t forwarded_packets; +#endif + struct list_head next; + struct ffn_data manip; + struct list_head all_next; +}; + +extern spinlock_t ffn_lock; +struct ffn_lookup_entry *__ffn_get(u32 sip, u32 dip, + u16 sport, u16 dport, + int is_tcp); + +#endif /* ! IP_FFN_H_*/ --- /dev/null 2019-09-30 09:50:43.919599165 +0200 +++ linux-4.14.127-fbx/include/uapi/linux/bcm63xx_rdp_ioctl.h 2019-02-15 14:29:44.766667250 +0100 @@ -0,0 +1,77 @@ +#ifndef LINUX_BCM63XX_RDP_IOCTL_H_ +#define LINUX_BCM63XX_RDP_IOCTL_H_ + +#include + +enum { + RDP_IOC_OP_GET_INFO, + RDP_IOC_OP_SET_EMAC, + + RDP_IOC_OP_READ8, + RDP_IOC_OP_READ16, + RDP_IOC_OP_READ32, + RDP_IOC_OP_WRITE8, + RDP_IOC_OP_WRITE16, + RDP_IOC_OP_WRITE32, + + RDP_IOC_OP_READ_TM_32, + RDP_IOC_OP_WRITE_TM_32, + RDP_IOC_OP_READ_MC_32, + RDP_IOC_OP_WRITE_MC_32, + + RDP_IOC_OP_RESET, + + RDP_IOC_DMA_MAP, + RDP_IOC_DMA_GET_INFO, + RDP_IOC_DMA_FLUSH_ALL, + RDP_IOC_DMA_READ_BUFFER, + RDP_IOC_DMA_WRITE_BUFFER, + + RDP_IOC_OP_MAP_INTERRUPTS, +}; + +struct bcm_rdp_pioctl_dma_result { + __u32 id; + __u32 size; + __u32 virt_addr; + __u32 dma_addr; +}; + +struct bcm_rdp_pioctl_get_info_result { + __u32 tm_dma_addr; + __u32 tm_size; + __u32 mc_dma_addr; + __u32 mc_size; +}; + +struct bcm_rdp_pioctl { + union { + /* for get_info op */ + struct { + void __user *buf_addr; + } get_info; + + /* for get_info op */ + struct { + unsigned int id; + unsigned int state; + } set_emac; + + /* for read/write op */ + struct { + __u32 offset; + __u32 size; + void __user *buf_addr; + } io; + + /* for dma op */ + struct { + __u32 id; + __u32 size; + void __user *buf_addr; + } dma; + } u; +}; + +#endif /* LINUX_BCM63XX_RDP_IOCTL_H_ */ + --- /dev/null 2019-09-30 09:50:43.919599165 +0200 +++ linux-4.14.127-fbx/include/uapi/linux/exfat_user.h 2019-01-14 15:09:09.731953546 +0100 @@ -0,0 +1,47 @@ +/* + * exfat_user.h for exfat + * Created by on Fri Aug 23 15:31:08 2013 + */ + +#ifndef __EXFAT_USER_H +# define __EXFAT_USER_H + +struct exfat_fragment { + uint32_t fcluster_start; + uint32_t dcluster_start; + uint32_t nr_clusters; + uint64_t sector_start; +}; + +struct exfat_fragment_head { + uint32_t fcluster_start; + uint32_t nr_fragments; + uint32_t sector_size; + uint32_t cluster_size; + struct exfat_fragment fragments[0]; +}; + +struct exfat_bitmap_data { + uint32_t start_cluster; + uint32_t nr_clusters; + uint64_t sector_start; + uint64_t nr_sectors; +}; + +struct exfat_bitmap_head { + uint32_t start_cluster; + uint32_t nr_entries; + struct exfat_bitmap_data entries[0]; +}; + +struct exfat_dirent_head { + uint32_t offset; + uint32_t nr_entries; + uint8_t entries[0]; +}; + +#define EXFAT_IOCGETFRAGMENTS _IOR('X', 0x01, struct exfat_fragment_head) +#define EXFAT_IOCGETBITMAP _IOR('X', 0x02, struct exfat_bitmap_head) +#define EXFAT_IOCGETDIRENTS _IOR('X', 0x03, struct exfat_dirent_head) + +#endif /* !__EXFAT_USER_H */ --- /dev/null 2019-09-30 09:50:43.919599165 +0200 +++ linux-4.14.127-fbx/include/uapi/linux/fbxatm.h 2019-01-14 15:16:37.746085412 +0100 @@ -0,0 +1,159 @@ +/* + * Generic fbxatm definition, exported to userspace + */ +#ifndef LINUX_FBXATM_H_ +#define LINUX_FBXATM_H_ + +#include +#include + +#define FBXATM_IOCTL_MAGIC 0xd3 + +/* allow userspace usage without up to date kernel headers */ +#ifndef PF_FBXATM +#define PF_FBXATM 32 +#define AF_FBXATM PF_FBXATM +#endif + +struct fbxatm_vcc_id { + int dev_idx; + __u32 vpi; + __u32 vci; +}; + +enum fbxatm_vcc_user { + FBXATM_VCC_USER_NONE = 0, + FBXATM_VCC_USER_2684, + FBXATM_VCC_USER_PPPOA, +}; + +enum fbxatm_vcc_traffic_class { + FBXATM_VCC_TC_UBR_NO_PCR = 0, + FBXATM_VCC_TC_UBR, +}; + +struct fbxatm_vcc_qos { + __u32 traffic_class; + __u32 max_sdu; + __u32 max_buffered_pkt; + __u32 priority; + __u32 rx_priority; +}; + + +/* + * VCC related + */ +struct fbxatm_vcc_params { + /* ADD/DEL/GET */ + struct fbxatm_vcc_id id; + + /* ADD/GET */ + struct fbxatm_vcc_qos qos; + + /* GET */ + enum fbxatm_vcc_user user; +}; + +#define FBXATM_IOCADD _IOW(FBXATM_IOCTL_MAGIC, 1, \ + struct fbxatm_vcc_params) + +#define FBXATM_IOCDEL _IOR(FBXATM_IOCTL_MAGIC, 2, \ + struct fbxatm_vcc_params) + +#define FBXATM_IOCGET _IOWR(FBXATM_IOCTL_MAGIC, 3, \ + struct fbxatm_vcc_params) + + +struct fbxatm_vcc_drop_params { + struct fbxatm_vcc_id id; + unsigned int drop_count; +}; + +#define FBXATM_IOCDROP _IOWR(FBXATM_IOCTL_MAGIC, 5, \ + struct fbxatm_vcc_drop_params) + +/* + * OAM related + */ +enum fbxatm_oam_ping_type { + FBXATM_OAM_PING_SEG_F4 = 0, + FBXATM_OAM_PING_SEG_F5, + FBXATM_OAM_PING_E2E_F4, + FBXATM_OAM_PING_E2E_F5, +}; + +struct fbxatm_oam_ping_req { + /* only dev_idx for F4 */ + struct fbxatm_vcc_id id; + + __u8 llid[16]; + enum fbxatm_oam_ping_type type; +}; + +#define FBXATM_IOCOAMPING _IOWR(FBXATM_IOCTL_MAGIC, 10, \ + struct fbxatm_oam_ping_req) + + +/* + * PPPOA related + */ +enum fbxatm_pppoa_encap { + FBXATM_EPPPOA_AUTODETECT = 0, + FBXATM_EPPPOA_VCMUX, + FBXATM_EPPPOA_LLC, +}; + +struct fbxatm_pppoa_vcc_params { + struct fbxatm_vcc_id id; + __u32 encap; + __u32 cur_encap; +}; + +#define FBXATM_PPPOA_IOCADD _IOW(FBXATM_IOCTL_MAGIC, 20, \ + struct fbxatm_pppoa_vcc_params) + +#define FBXATM_PPPOA_IOCDEL _IOW(FBXATM_IOCTL_MAGIC, 21, \ + struct fbxatm_pppoa_vcc_params) + +#define FBXATM_PPPOA_IOCGET _IOWR(FBXATM_IOCTL_MAGIC, 22, \ + struct fbxatm_pppoa_vcc_params) + + + +/* + * 2684 related + */ +enum fbxatm_2684_encap { + FBXATM_E2684_VCMUX = 0, + FBXATM_E2684_LLC, +}; + +enum fbxatm_2684_payload { + FBXATM_P2684_BRIDGE = 0, + FBXATM_P2684_ROUTED, +}; + +#define FBXATM_2684_MAX_VCC 8 + +struct fbxatm_2684_vcc_params { + struct fbxatm_vcc_id id_list[FBXATM_2684_MAX_VCC]; + size_t id_count; + + __u32 encap; + __u32 payload; + char dev_name[IFNAMSIZ]; + __u8 perm_addr[6]; +}; + + +#define FBXATM_2684_IOCADD _IOW(FBXATM_IOCTL_MAGIC, 30, \ + struct fbxatm_2684_vcc_params) + +#define FBXATM_2684_IOCDEL _IOW(FBXATM_IOCTL_MAGIC, 31, \ + struct fbxatm_2684_vcc_params) + +#define FBXATM_2684_IOCGET _IOWR(FBXATM_IOCTL_MAGIC, 32, \ + struct fbxatm_2684_vcc_params) + +#endif /* LINUX_FBXATM_H_ */ --- /dev/null 2019-09-30 09:50:43.919599165 +0200 +++ linux-4.14.127-fbx/include/uapi/linux/fbxbridge.h 2019-02-15 14:29:44.778667298 +0100 @@ -0,0 +1,72 @@ +#ifndef _UAPI_FBXBRIDGE_H +# define _UAPI_FBXBRIDGE_H + +#include +#include + +#define MAX_ALIASES 3 + +#define FBXBRIDGE_FLAGS_FILTER (1 << 0) +#define FBXBRIDGE_FLAGS_DHCPD (1 << 1) +#define FBXBRIDGE_FLAGS_NETFILTER (1 << 2) + +/* + * ioctl command + */ + +enum fbxbridge_ioctl_cmd +{ + E_CMD_BR_CHG = 0, + E_CMD_BR_DEV_CHG, + E_CMD_BR_PARAMS, +}; + +struct fbxbridge_ioctl_chg +{ + char brname[IFNAMSIZ]; + __u32 action; +}; + +struct fbxbridge_ioctl_dev_chg +{ + char brname[IFNAMSIZ]; + char devname[IFNAMSIZ]; + __u32 wan; + __u32 action; +}; + +struct fbxbridge_port_info +{ + char name[IFNAMSIZ]; + __u32 present; +}; + +struct fbxbridge_ioctl_params +{ + int action; + char brname[IFNAMSIZ]; + + /* config */ + __u32 flags; + __be32 dns1_addr; + __be32 dns2_addr; + __be32 ip_aliases[MAX_ALIASES]; + __u32 dhcpd_renew_time; + __u32 dhcpd_rebind_time; + __u32 dhcpd_lease_time; + __u32 inputmark; + + /* status */ + struct fbxbridge_port_info wan_dev; + struct fbxbridge_port_info lan_dev; + __u8 lan_hwaddr[ETH_ALEN]; + __u32 have_hw_addr; +}; + +struct fbxbridge_ioctl_req +{ + enum fbxbridge_ioctl_cmd cmd; + unsigned long arg; +}; + +#endif /* _UAPI_FBXBRIDGE_H */ --- /dev/null 2019-09-30 09:50:43.919599165 +0200 +++ linux-4.14.127-fbx/include/uapi/linux/fbxjtag.h 2019-02-15 14:29:44.778667298 +0100 @@ -0,0 +1,89 @@ +#ifndef FBXJTAG_H_ +# define FBXJTAG_H_ + +#ifdef __KERNEL__ +# include +#endif + +# define JTAG_RESET_STEPS 16 +# define JTAG_DATA_READ_SIZE 128 +# define JTAG_INST_READ_SIZE 128 +# define JTAG_DEF_CLOCK_DELAY 500 +# define JTAG_DEF_WAIT_TMS 0 + +enum jtag_main_state { + JTAG_STATE_TEST_MASK = 0x10, + JTAG_STATE_RUN_MASK = 0x20, + JTAG_STATE_DR_MASK = 0x40, + JTAG_STATE_IR_MASK = 0x80, +}; +#define JTAG_STATE_MASK 0xF0 + +enum jtag_sub_state { + JTAG_SUB_STATE_SELECT = 0x0, + JTAG_SUB_STATE_CAPTURE = 0x1, + JTAG_SUB_STATE_SHIFT = 0x2, + JTAG_SUB_STATE_EXIT1 = 0x3, + JTAG_SUB_STATE_PAUSE = 0x4, + JTAG_SUB_STATE_EXIT2 = 0x5, + JTAG_SUB_STATE_UPDATE = 0x6, +}; +#define JTAG_SUB_STATE_MASK 0xF + +enum jtag_state { + JTAG_STATE_UNDEF = 0, + JTAG_STATE_TEST_LOGIC_RESET = JTAG_STATE_TEST_MASK, + JTAG_STATE_RUN_TEST_IDLE = JTAG_STATE_RUN_MASK, + + JTAG_STATE_SELECT_DR = JTAG_STATE_DR_MASK | JTAG_SUB_STATE_SELECT, + JTAG_STATE_CAPTURE_DR = JTAG_STATE_DR_MASK | JTAG_SUB_STATE_CAPTURE, + JTAG_STATE_SHIFT_DR = JTAG_STATE_DR_MASK | JTAG_SUB_STATE_SHIFT, + JTAG_STATE_EXIT1_DR = JTAG_STATE_DR_MASK | JTAG_SUB_STATE_EXIT1, + JTAG_STATE_PAUSE_DR = JTAG_STATE_DR_MASK | JTAG_SUB_STATE_PAUSE, + JTAG_STATE_EXIT2_DR = JTAG_STATE_DR_MASK | JTAG_SUB_STATE_EXIT2, + JTAG_STATE_UPDATE_DR = JTAG_STATE_DR_MASK | JTAG_SUB_STATE_UPDATE, + + JTAG_STATE_SELECT_IR = JTAG_STATE_IR_MASK | JTAG_SUB_STATE_SELECT, + JTAG_STATE_CAPTURE_IR = JTAG_STATE_IR_MASK | JTAG_SUB_STATE_CAPTURE, + JTAG_STATE_SHIFT_IR = JTAG_STATE_IR_MASK | JTAG_SUB_STATE_SHIFT, + JTAG_STATE_EXIT1_IR = JTAG_STATE_IR_MASK | JTAG_SUB_STATE_EXIT1, + JTAG_STATE_PAUSE_IR = JTAG_STATE_IR_MASK | JTAG_SUB_STATE_PAUSE, + JTAG_STATE_EXIT2_IR = JTAG_STATE_IR_MASK | JTAG_SUB_STATE_EXIT2, + JTAG_STATE_UPDATE_IR = JTAG_STATE_IR_MASK | JTAG_SUB_STATE_UPDATE, + + JTAG_STATE_MAX +}; + +#define JTAG_STATE_IN_DR(state) ((state) & JTAG_STATE_DR_MASK) +#define JTAG_STATE_IN_IR(state) ((state) & JTAG_STATE_IR_MASK) + +#ifdef __KERNEL__ + +#define JTAG_BUF_SIZE 2048 + +struct fbxjtag_data { + const char *name; + struct { + struct fbxgpio_pin *tck; + struct fbxgpio_pin *tms; + struct fbxgpio_pin *tdi; + struct fbxgpio_pin *tdo; + } gpios; + u32 clock_delay; + u32 wait_tms; + u32 data_read_size; + u32 instruction_read_size; + bool last_tms_dataout; + struct device *dev; + enum jtag_state state; + char nb_reset; + char dr_buf[JTAG_BUF_SIZE]; + unsigned dr_w; + unsigned dr_r; + char ir_buf[JTAG_BUF_SIZE]; + unsigned ir_r; + unsigned ir_w; +}; +#endif + +#endif /* !FBXJTAG_H_ */ diff -Nruw linux-4.14.127-fbx/include/uapi/linux/hdmi-cec./Kbuild linux-4.14.127-fbx/include/uapi/linux/hdmi-cec/Kbuild --- linux-4.14.127-fbx/include/uapi/linux/hdmi-cec./Kbuild 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/include/uapi/linux/hdmi-cec/Kbuild 2019-02-15 14:29:44.778667298 +0100 @@ -0,0 +1 @@ +header-y += hdmi-cec.h dev.h diff -Nruw linux-4.14.127-fbx/include/uapi/linux/hdmi-cec./dev.h linux-4.14.127-fbx/include/uapi/linux/hdmi-cec/dev.h --- linux-4.14.127-fbx/include/uapi/linux/hdmi-cec./dev.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/include/uapi/linux/hdmi-cec/dev.h 2019-02-15 14:29:44.778667298 +0100 @@ -0,0 +1,30 @@ +#ifndef __HDMI_CEC_DEV_H +#define __HDMI_CEC_DEV_H + +#include +#include + +#define CEC_IOCTL_BASE 'C' + +#define CEC_SET_LOGICAL_ADDRESS _IOW(CEC_IOCTL_BASE, 0, int) +#define CEC_RESET_DEVICE _IOW(CEC_IOCTL_BASE, 3, int) +#define CEC_GET_COUNTERS _IOR(CEC_IOCTL_BASE, 4, struct cec_counters) +#define CEC_SET_RX_MODE _IOW(CEC_IOCTL_BASE, 5, enum cec_rx_mode) +#define CEC_GET_TX_STATUS _IOW(CEC_IOCTL_BASE, 6, struct cec_tx_status) +#define CEC_SET_DETACHED_CONFIG _IOW(CEC_IOCTL_BASE, 7, struct cec_detached_config) + +#define CEC_MAX_DEVS (10) + +#ifdef __KERNEL__ + +struct cec_adapter; + +int __init cec_cdev_init(void); +void __exit cec_cdev_exit(void); + +int cec_create_adapter_node(struct cec_adapter *); +void cec_remove_adapter_node(struct cec_adapter *); + +#endif /* __KERNEL__ */ + +#endif /* __HDMI_CEC_DEV_H */ diff -Nruw linux-4.14.127-fbx/include/uapi/linux/hdmi-cec./hdmi-cec.h linux-4.14.127-fbx/include/uapi/linux/hdmi-cec/hdmi-cec.h --- linux-4.14.127-fbx/include/uapi/linux/hdmi-cec./hdmi-cec.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-4.14.127-fbx/include/uapi/linux/hdmi-cec/hdmi-cec.h 2019-02-15 14:29:44.778667298 +0100 @@ -0,0 +1,153 @@ +#ifndef __UAPI_HDMI_CEC_H +#define __UAPI_HDMI_CEC_H + +#include +#include + +/* Common defines for HDMI CEC */ +#define CEC_BCAST_ADDR (0x0f) +#define CEC_ADDR_MAX CEC_BCAST_ADDR + +#define CEC_MAX_MSG_LEN (16) /* 16 blocks */ + +enum cec_rx_msg_flags { + /* + * an ACK was received for this message + */ + CEC_RX_F_ACKED = (1 << 0), + + /* + * message was fully received + */ + CEC_RX_F_COMPLETE = (1 << 1), +}; + +/** + * struct cec_rx_msg - user-space exposed cec message cookie + * @data: cec message payload + * @len: cec message length + * @valid: 0 for invalid message + * @flags: flag field (cec_rx_msg_flags) + */ +struct cec_rx_msg { + __u8 data[CEC_MAX_MSG_LEN]; + __u8 len; + __u8 valid; + __u8 flags; + +} __attribute__((packed)); + +enum cec_tx_status_flags { + /* + * message was nacked at some point + */ + CEC_TX_F_NACK = (1 << 0), + + /* + * abort sending because total time to send was elapsed + */ + CEC_TX_F_TIMEOUT = (1 << 1), + + /* + * abort sending because maximum number of retry has passed + */ + CEC_TX_F_MAX_RETRIES = (1 << 2), + + /* + * abort sending because of arbitration loss + */ + CEC_TX_F_ARBITRATION_LOST = (1 << 3), + + /* + * message failed for other reason + */ + CEC_TX_F_UNKNOWN_ERROR = (1 << 7), +}; + +/** + * struct cec_tx_msg - user-space exposed cec message cookie + * @expire_ms: how long we try to send message (milliseconds) + * @data: cec message payload + * @len: cec message length + * @success: 0 => message was sent, else => failed to send message + * @flags: flag field (cec_tx_msg_flags) + * @tries: number of try done to send message + */ +struct cec_tx_msg { + __u16 expire_ms; + __u8 data[CEC_MAX_MSG_LEN]; + __u8 len; + __u8 success; + __u8 flags; + __u8 tries; +} __attribute__((packed)); + +struct cec_tx_status { + __u8 sent; + __u8 success; + __u8 flags; + __u8 tries; +} __attribute__((packed)); + +#define DETACH_CFG_F_W